Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3, |
| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 22 | SDTCisInt<0>, SDTCisInt<3>]>; |
| 23 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 24 | def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 25 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 26 | def SDTX86Cmov : SDTypeProfile<1, 3, |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 28 | SDTCisVT<3, i8>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 29 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 30 | def SDTX86BrCond : SDTypeProfile<0, 2, |
| 31 | [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 32 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 33 | def SDTX86SetCC : SDTypeProfile<1, 1, |
| 34 | [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 35 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 36 | def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 37 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 38 | def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; |
| 39 | def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>, |
| 40 | SDTCisVT<1, i32> ]>; |
| 41 | |
| 42 | def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; |
| 43 | |
| 44 | def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>; |
| 45 | def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>; |
| 46 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 47 | def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 48 | SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 49 | def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, |
| 50 | SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 51 | def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>, |
| 52 | SDTCisVT<2, OtherVT>]>; |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 53 | def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 54 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 55 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; |
| 56 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 57 | def SDTX86RdTsc : SDTypeProfile<0, 0, []>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 58 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 59 | def X86addflag : SDNode<"X86ISD::ADD_FLAG", SDTIntBinOp , |
| 60 | [SDNPCommutative, SDNPAssociative, SDNPOutFlag]>; |
| 61 | def X86subflag : SDNode<"X86ISD::SUB_FLAG", SDTIntBinOp, |
| 62 | [SDNPOutFlag]>; |
| 63 | def X86adc : SDNode<"X86ISD::ADC" , SDTIntBinOp , |
Evan Cheng | 41b6dc8 | 2006-01-19 06:53:20 +0000 | [diff] [blame] | 64 | [SDNPCommutative, SDNPAssociative, SDNPInFlag]>; |
| 65 | def X86sbb : SDNode<"X86ISD::SBB" , SDTIntBinOp, |
| 66 | [SDNPInFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 67 | |
| 68 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; |
| 69 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 70 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 71 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, |
| 72 | [SDNPOutFlag]>; |
| 73 | def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, |
| 74 | [SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 75 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 76 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 77 | [SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 78 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 79 | [SDNPHasChain, SDNPInFlag]>; |
Evan Cheng | 5ee4ccc | 2006-01-12 08:27:59 +0000 | [diff] [blame] | 80 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 81 | [SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 82 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 83 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, |
| 84 | [SDNPHasChain, SDNPOptInFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 85 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 86 | def X86callseq_start : |
| 87 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, |
| 88 | [SDNPHasChain]>; |
| 89 | def X86callseq_end : |
| 90 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, |
Chris Lattner | af63bb0 | 2006-01-24 05:17:12 +0000 | [diff] [blame] | 91 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 92 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 93 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, |
| 94 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 95 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 96 | def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet, |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 97 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 98 | def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet, |
| 99 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 100 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 101 | def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, |
| 102 | [SDNPHasChain]>; |
| 103 | def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, |
Evan Cheng | 42ef0bc | 2006-01-17 00:19:47 +0000 | [diff] [blame] | 104 | [SDNPHasChain, SDNPInFlag]>; |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 105 | def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 106 | [SDNPHasChain]>; |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 107 | def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, |
| 108 | [SDNPHasChain]>; |
| 109 | def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, |
| 110 | [SDNPHasChain]>; |
| 111 | def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, |
| 112 | [SDNPHasChain]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 113 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 114 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, |
| 115 | [SDNPHasChain, SDNPInFlag]>; |
| 116 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, |
| 117 | [SDNPHasChain, SDNPInFlag]>; |
| 118 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 119 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc, |
| 120 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 121 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 122 | //===----------------------------------------------------------------------===// |
| 123 | // X86 Operand Definitions. |
| 124 | // |
| 125 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 126 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 127 | // |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 128 | class X86MemOperand<string printMethod> : Operand<i32> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 129 | let PrintMethod = printMethod; |
Chris Lattner | 6adaf79 | 2005-11-19 07:01:30 +0000 | [diff] [blame] | 130 | let NumMIOperands = 4; |
| 131 | let MIOperandInfo = (ops R32, i8imm, R32, i32imm); |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 132 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 133 | |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 134 | def i8mem : X86MemOperand<"printi8mem">; |
| 135 | def i16mem : X86MemOperand<"printi16mem">; |
| 136 | def i32mem : X86MemOperand<"printi32mem">; |
| 137 | def i64mem : X86MemOperand<"printi64mem">; |
| 138 | def f32mem : X86MemOperand<"printf32mem">; |
| 139 | def f64mem : X86MemOperand<"printf64mem">; |
| 140 | def f80mem : X86MemOperand<"printf80mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 141 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 142 | def SSECC : Operand<i8> { |
| 143 | let PrintMethod = "printSSECC"; |
| 144 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 145 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 146 | // A couple of more descriptive operand definitions. |
| 147 | // 16-bits but only 8 bits are significant. |
| 148 | def i16i8imm : Operand<i16>; |
| 149 | // 32-bits but only 8 bits are significant. |
| 150 | def i32i8imm : Operand<i32>; |
| 151 | |
Chris Lattner | e4ead0c | 2004-08-11 06:59:12 +0000 | [diff] [blame] | 152 | // PCRelative calls need special operand formatting. |
| 153 | let PrintMethod = "printCallOperand" in |
| 154 | def calltarget : Operand<i32>; |
| 155 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 156 | // Branch targets have OtherVT type. |
| 157 | def brtarget : Operand<OtherVT>; |
| 158 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 159 | //===----------------------------------------------------------------------===// |
| 160 | // X86 Complex Pattern Definitions. |
| 161 | // |
| 162 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 163 | // Define X86 specific addressing mode. |
Evan Cheng | 670fd8f | 2005-12-08 02:15:07 +0000 | [diff] [blame] | 164 | def addr : ComplexPattern<i32, 4, "SelectAddr", []>; |
Evan Cheng | 502c5bb | 2005-12-15 08:31:04 +0000 | [diff] [blame] | 165 | def leaaddr : ComplexPattern<i32, 4, "SelectLEAAddr", |
Evan Cheng | 002fe9b | 2006-01-12 07:56:47 +0000 | [diff] [blame] | 166 | [add, frameindex, constpool]>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 167 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 168 | //===----------------------------------------------------------------------===// |
| 169 | // X86 Instruction Format Definitions. |
| 170 | // |
| 171 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 172 | // Format specifies the encoding used by the instruction. This is part of the |
| 173 | // ad-hoc solution used to emit machine instruction encodings by our machine |
| 174 | // code emitter. |
| 175 | class Format<bits<5> val> { |
| 176 | bits<5> Value = val; |
| 177 | } |
| 178 | |
| 179 | def Pseudo : Format<0>; def RawFrm : Format<1>; |
| 180 | def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; |
| 181 | def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; |
| 182 | def MRMSrcMem : Format<6>; |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 183 | def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; |
| 184 | def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; |
| 185 | def MRM6r : Format<22>; def MRM7r : Format<23>; |
| 186 | def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; |
| 187 | def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; |
| 188 | def MRM6m : Format<30>; def MRM7m : Format<31>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 189 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 190 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 191 | // X86 Instruction Predicate Definitions. |
Evan Cheng | 559806f | 2006-01-27 08:10:46 +0000 | [diff] [blame^] | 192 | def HasSSE1 : Predicate<"Subtarget->hasSSE()">; |
| 193 | def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; |
| 194 | def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; |
| 195 | def FPStack : Predicate<"!Subtarget->hasSSE2()">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 196 | |
| 197 | //===----------------------------------------------------------------------===// |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 198 | // X86 specific pattern fragments. |
| 199 | // |
| 200 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 201 | // ImmType - This specifies the immediate type used by an instruction. This is |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 202 | // part of the ad-hoc solution used to emit machine instruction encodings by our |
| 203 | // machine code emitter. |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 204 | class ImmType<bits<2> val> { |
| 205 | bits<2> Value = val; |
| 206 | } |
| 207 | def NoImm : ImmType<0>; |
| 208 | def Imm8 : ImmType<1>; |
| 209 | def Imm16 : ImmType<2>; |
| 210 | def Imm32 : ImmType<3>; |
| 211 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 212 | // FPFormat - This specifies what form this FP instruction has. This is used by |
| 213 | // the Floating-Point stackifier pass. |
| 214 | class FPFormat<bits<3> val> { |
| 215 | bits<3> Value = val; |
| 216 | } |
| 217 | def NotFP : FPFormat<0>; |
| 218 | def ZeroArgFP : FPFormat<1>; |
| 219 | def OneArgFP : FPFormat<2>; |
| 220 | def OneArgFPRW : FPFormat<3>; |
| 221 | def TwoArgFP : FPFormat<4>; |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 222 | def CompareFP : FPFormat<5>; |
| 223 | def CondMovFP : FPFormat<6>; |
| 224 | def SpecialFP : FPFormat<7>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 225 | |
| 226 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 227 | class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> |
| 228 | : Instruction { |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 229 | let Namespace = "X86"; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 230 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 231 | bits<8> Opcode = opcod; |
| 232 | Format Form = f; |
| 233 | bits<5> FormBits = Form.Value; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 234 | ImmType ImmT = i; |
| 235 | bits<2> ImmTypeBits = ImmT.Value; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 236 | |
Chris Lattner | c96bb81 | 2004-08-11 07:12:04 +0000 | [diff] [blame] | 237 | dag OperandList = ops; |
| 238 | string AsmString = AsmStr; |
| 239 | |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 240 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 241 | // Attributes specific to X86 instructions... |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 242 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 243 | bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 244 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 245 | bits<4> Prefix = 0; // Which prefix byte does this inst have? |
| 246 | FPFormat FPForm; // What flavor of FP instruction is this? |
| 247 | bits<3> FPFormBits = 0; |
| 248 | } |
| 249 | |
| 250 | class Imp<list<Register> uses, list<Register> defs> { |
| 251 | list<Register> Uses = uses; |
| 252 | list<Register> Defs = defs; |
| 253 | } |
| 254 | |
| 255 | |
| 256 | // Prefix byte classes which are used to indicate to the ad-hoc machine code |
| 257 | // emitter that various prefix bytes are required. |
| 258 | class OpSize { bit hasOpSizePrefix = 1; } |
| 259 | class TB { bits<4> Prefix = 1; } |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 260 | class REP { bits<4> Prefix = 2; } |
| 261 | class D8 { bits<4> Prefix = 3; } |
| 262 | class D9 { bits<4> Prefix = 4; } |
| 263 | class DA { bits<4> Prefix = 5; } |
| 264 | class DB { bits<4> Prefix = 6; } |
| 265 | class DC { bits<4> Prefix = 7; } |
| 266 | class DD { bits<4> Prefix = 8; } |
| 267 | class DE { bits<4> Prefix = 9; } |
| 268 | class DF { bits<4> Prefix = 10; } |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 269 | class XD { bits<4> Prefix = 11; } |
| 270 | class XS { bits<4> Prefix = 12; } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 271 | |
| 272 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 273 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 274 | // Pattern fragments... |
| 275 | // |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 276 | |
| 277 | // X86 specific condition code. These correspond to CondCode in |
| 278 | // X86ISelLowering.h. They must be kept in synch. |
| 279 | def X86_COND_A : PatLeaf<(i8 0)>; |
| 280 | def X86_COND_AE : PatLeaf<(i8 1)>; |
| 281 | def X86_COND_B : PatLeaf<(i8 2)>; |
| 282 | def X86_COND_BE : PatLeaf<(i8 3)>; |
| 283 | def X86_COND_E : PatLeaf<(i8 4)>; |
| 284 | def X86_COND_G : PatLeaf<(i8 5)>; |
| 285 | def X86_COND_GE : PatLeaf<(i8 6)>; |
| 286 | def X86_COND_L : PatLeaf<(i8 7)>; |
| 287 | def X86_COND_LE : PatLeaf<(i8 8)>; |
| 288 | def X86_COND_NE : PatLeaf<(i8 9)>; |
| 289 | def X86_COND_NO : PatLeaf<(i8 10)>; |
| 290 | def X86_COND_NP : PatLeaf<(i8 11)>; |
| 291 | def X86_COND_NS : PatLeaf<(i8 12)>; |
| 292 | def X86_COND_O : PatLeaf<(i8 13)>; |
| 293 | def X86_COND_P : PatLeaf<(i8 14)>; |
| 294 | def X86_COND_S : PatLeaf<(i8 15)>; |
| 295 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 296 | def i16immSExt8 : PatLeaf<(i16 imm), [{ |
| 297 | // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 298 | // sign extended field. |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 299 | return (int)N->getValue() == (signed char)N->getValue(); |
| 300 | }]>; |
| 301 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 302 | def i32immSExt8 : PatLeaf<(i32 imm), [{ |
| 303 | // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 304 | // sign extended field. |
| 305 | return (int)N->getValue() == (signed char)N->getValue(); |
| 306 | }]>; |
| 307 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 308 | def i16immZExt8 : PatLeaf<(i16 imm), [{ |
| 309 | // i16immZExt8 predicate - True if the 16-bit immediate fits in a 8-bit zero |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 310 | // extended field. |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 311 | return (unsigned)N->getValue() == (unsigned char)N->getValue(); |
| 312 | }]>; |
| 313 | |
Evan Cheng | 650d688 | 2006-01-05 02:08:37 +0000 | [diff] [blame] | 314 | def fp32imm0 : PatLeaf<(f32 fpimm), [{ |
| 315 | return N->isExactlyValue(+0.0); |
| 316 | }]>; |
| 317 | |
| 318 | def fp64imm0 : PatLeaf<(f64 fpimm), [{ |
| 319 | return N->isExactlyValue(+0.0); |
| 320 | }]>; |
| 321 | |
| 322 | def fp64immneg0 : PatLeaf<(f64 fpimm), [{ |
| 323 | return N->isExactlyValue(-0.0); |
| 324 | }]>; |
| 325 | |
| 326 | def fp64imm1 : PatLeaf<(f64 fpimm), [{ |
| 327 | return N->isExactlyValue(+1.0); |
| 328 | }]>; |
| 329 | |
| 330 | def fp64immneg1 : PatLeaf<(f64 fpimm), [{ |
| 331 | return N->isExactlyValue(-1.0); |
| 332 | }]>; |
| 333 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 334 | // Helper fragments for loads. |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 335 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; |
| 336 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>; |
| 337 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 338 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; |
| 339 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 340 | |
| 341 | def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>; |
| 342 | def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>; |
| 343 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>; |
| 344 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i8))>; |
| 345 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i16))>; |
| 346 | |
Evan Cheng | e5d9343 | 2006-01-17 07:02:46 +0000 | [diff] [blame] | 347 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextload node:$ptr, i1))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 348 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i1))>; |
| 349 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i1))>; |
| 350 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>; |
| 351 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>; |
| 352 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>; |
| 353 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 354 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>; |
| 355 | def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>; |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 356 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 357 | //===----------------------------------------------------------------------===// |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 358 | // Instruction templates... |
| 359 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 360 | class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 361 | : X86Inst<o, f, NoImm, ops, asm> { |
| 362 | let Pattern = pattern; |
| 363 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 364 | class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 365 | : X86Inst<o, f, Imm8 , ops, asm> { |
| 366 | let Pattern = pattern; |
| 367 | } |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 368 | class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 369 | : X86Inst<o, f, Imm16, ops, asm> { |
| 370 | let Pattern = pattern; |
| 371 | } |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 372 | class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern> |
| 373 | : X86Inst<o, f, Imm32, ops, asm> { |
| 374 | let Pattern = pattern; |
| 375 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 376 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 377 | //===----------------------------------------------------------------------===// |
| 378 | // Instruction list... |
| 379 | // |
| 380 | |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 381 | def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 382 | [(X86callseq_start imm:$amt)]>; |
Chris Lattner | 43ef131 | 2005-09-14 21:10:24 +0000 | [diff] [blame] | 383 | def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2), |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 384 | "#ADJCALLSTACKUP", |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 385 | [(X86callseq_end imm:$amt1, imm:$amt2)]>; |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 386 | def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>; |
| 387 | def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 388 | def IMPLICIT_DEF_R8 : I<0, Pseudo, (ops R8:$dst), |
| 389 | "#IMPLICIT_DEF $dst", |
| 390 | [(set R8:$dst, (undef))]>; |
| 391 | def IMPLICIT_DEF_R16 : I<0, Pseudo, (ops R16:$dst), |
| 392 | "#IMPLICIT_DEF $dst", |
| 393 | [(set R16:$dst, (undef))]>; |
| 394 | def IMPLICIT_DEF_R32 : I<0, Pseudo, (ops R32:$dst), |
| 395 | "#IMPLICIT_DEF $dst", |
| 396 | [(set R32:$dst, (undef))]>; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 397 | def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst), |
| 398 | "#IMPLICIT_DEF $dst", |
| 399 | [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>; |
| 400 | def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst), |
| 401 | "#IMPLICIT_DEF $dst", |
| 402 | [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>; |
| 403 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 404 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 405 | // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the |
| 406 | // scheduler into a branch sequence. |
| 407 | let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. |
| 408 | def CMOV_FR32 : I<0, Pseudo, |
| 409 | (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond), |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 410 | "#CMOV_FR32 PSEUDO!", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 411 | [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 412 | def CMOV_FR64 : I<0, Pseudo, |
| 413 | (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond), |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 414 | "#CMOV_FR64 PSEUDO!", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 415 | [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 416 | } |
| 417 | |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 418 | let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. |
| 419 | def FP_TO_INT16_IN_MEM : I<0, Pseudo, |
| 420 | (ops i16mem:$dst, RFP:$src), |
| 421 | "#FP_TO_INT16_IN_MEM PSEUDO!", |
| 422 | [(X86fp_to_i16mem RFP:$src, addr:$dst)]>; |
| 423 | def FP_TO_INT32_IN_MEM : I<0, Pseudo, |
| 424 | (ops i32mem:$dst, RFP:$src), |
| 425 | "#FP_TO_INT32_IN_MEM PSEUDO!", |
| 426 | [(X86fp_to_i32mem RFP:$src, addr:$dst)]>; |
| 427 | def FP_TO_INT64_IN_MEM : I<0, Pseudo, |
| 428 | (ops i64mem:$dst, RFP:$src), |
| 429 | "#FP_TO_INT64_IN_MEM PSEUDO!", |
| 430 | [(X86fp_to_i64mem RFP:$src, addr:$dst)]>; |
| 431 | } |
| 432 | |
| 433 | |
Alkis Evlogimenos | e0bb3e7 | 2003-12-20 16:22:59 +0000 | [diff] [blame] | 434 | let isTerminator = 1 in |
| 435 | let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 436 | def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>; |
Chris Lattner | 62cce39 | 2004-07-31 02:10:53 +0000 | [diff] [blame] | 437 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 438 | |
| 439 | // Nop |
| 440 | def NOOP : I<0x90, RawFrm, (ops), "nop", []>; |
| 441 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 442 | //===----------------------------------------------------------------------===// |
| 443 | // Control Flow Instructions... |
| 444 | // |
| 445 | |
Chris Lattner | 1be4811 | 2005-05-13 17:56:48 +0000 | [diff] [blame] | 446 | // Return instructions. |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 447 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
| 448 | hasCtrlDep = 1, noResults = 1 in { |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 449 | def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>; |
| 450 | def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", |
| 451 | [(X86retflag imm:$amt)]>; |
Evan Cheng | 171049d | 2005-12-23 22:14:32 +0000 | [diff] [blame] | 452 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 453 | |
| 454 | // All branches are RawFrm, Void, Branch, and Terminators |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 455 | let isBranch = 1, isTerminator = 1, noResults = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 456 | class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> : |
| 457 | I<opcode, RawFrm, ops, asm, pattern>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 458 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 459 | // Conditional branches |
Chris Lattner | 62cce39 | 2004-07-31 02:10:53 +0000 | [diff] [blame] | 460 | let isBarrier = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 461 | def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 462 | |
| 463 | def JE : IBr<0x84, (ops brtarget:$dst), "je $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 464 | [(X86brcond bb:$dst, X86_COND_E)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 465 | def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 466 | [(X86brcond bb:$dst, X86_COND_NE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 467 | def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 468 | [(X86brcond bb:$dst, X86_COND_L)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 469 | def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 470 | [(X86brcond bb:$dst, X86_COND_LE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 471 | def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 472 | [(X86brcond bb:$dst, X86_COND_G)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 473 | def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 474 | [(X86brcond bb:$dst, X86_COND_GE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 475 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 476 | def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 477 | [(X86brcond bb:$dst, X86_COND_B)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 478 | def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 479 | [(X86brcond bb:$dst, X86_COND_BE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 480 | def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 481 | [(X86brcond bb:$dst, X86_COND_A)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 482 | def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 483 | [(X86brcond bb:$dst, X86_COND_AE)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 484 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 485 | def JS : IBr<0x88, (ops brtarget:$dst), "js $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 486 | [(X86brcond bb:$dst, X86_COND_S)]>, TB; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 487 | def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 488 | [(X86brcond bb:$dst, X86_COND_NS)]>, TB; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 489 | def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 490 | [(X86brcond bb:$dst, X86_COND_P)]>, TB; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 491 | def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 492 | [(X86brcond bb:$dst, X86_COND_NP)]>, TB; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 493 | def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 494 | [(X86brcond bb:$dst, X86_COND_O)]>, TB; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 495 | def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 496 | [(X86brcond bb:$dst, X86_COND_NO)]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 497 | |
| 498 | //===----------------------------------------------------------------------===// |
| 499 | // Call Instructions... |
| 500 | // |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 501 | let isCall = 1, noResults = 1 in |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 502 | // All calls clobber the non-callee saved registers... |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 503 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 504 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in { |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 505 | def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst", |
| 506 | []>; |
| 507 | def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 508 | [(X86call R32:$dst)]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 509 | def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 510 | [(X86call (loadi32 addr:$dst))]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 511 | } |
| 512 | |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 513 | // Tail call stuff. |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 514 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 515 | def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL", []>; |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 516 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 517 | def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>; |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 518 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 519 | def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), |
| 520 | "jmp {*}$dst # TAIL CALL", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 521 | |
| 522 | // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every |
| 523 | // way, except that it is marked as being a terminator. This causes the epilog |
| 524 | // inserter to insert reloads of callee saved registers BEFORE this. We need |
| 525 | // this until we have a more accurate way of tracking where the stack pointer is |
| 526 | // within a function. |
| 527 | let isTerminator = 1, isTwoAddress = 1 in |
| 528 | def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 529 | "add{l} {$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 530 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 531 | //===----------------------------------------------------------------------===// |
| 532 | // Miscellaneous Instructions... |
| 533 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 534 | def LEAVE : I<0xC9, RawFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 535 | (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 536 | def POP32r : I<0x58, AddRegFrm, |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 537 | (ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 538 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 539 | let isTwoAddress = 1 in // R32 = bswap R32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 540 | def BSWAP32r : I<0xC8, AddRegFrm, |
Nate Begeman | d88fc03 | 2006-01-14 03:14:10 +0000 | [diff] [blame] | 541 | (ops R32:$dst, R32:$src), |
| 542 | "bswap{l} $dst", |
| 543 | [(set R32:$dst, (bswap R32:$src))]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 544 | |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 545 | def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 546 | (ops R8:$src1, R8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 547 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 548 | def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 549 | (ops R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 550 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 551 | def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32 |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 552 | (ops R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 553 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 554 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 555 | def XCHG8mr : I<0x86, MRMDestMem, |
| 556 | (ops i8mem:$src1, R8:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 557 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 558 | def XCHG16mr : I<0x87, MRMDestMem, |
| 559 | (ops i16mem:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 560 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 561 | def XCHG32mr : I<0x87, MRMDestMem, |
| 562 | (ops i32mem:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 563 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 564 | def XCHG8rm : I<0x86, MRMSrcMem, |
| 565 | (ops R8:$src1, i8mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 566 | "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 567 | def XCHG16rm : I<0x87, MRMSrcMem, |
| 568 | (ops R16:$src1, i16mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 569 | "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 570 | def XCHG32rm : I<0x87, MRMSrcMem, |
| 571 | (ops R32:$src1, i32mem:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 572 | "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 573 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 574 | def LEA16r : I<0x8D, MRMSrcMem, |
| 575 | (ops R16:$dst, i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 576 | "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 577 | def LEA32r : I<0x8D, MRMSrcMem, |
| 578 | (ops R32:$dst, i32mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 579 | "lea{l} {$src|$dst}, {$dst|$src}", |
| 580 | [(set R32:$dst, leaaddr:$src)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 581 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 582 | def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", |
| 583 | [(X86rep_movs i8)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 584 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 585 | def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", |
| 586 | [(X86rep_movs i16)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 587 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 588 | def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}", |
| 589 | [(X86rep_movs i32)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 590 | Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 591 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 592 | def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", |
| 593 | [(X86rep_stos i8)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 594 | Imp<[AL,ECX,EDI], [ECX,EDI]>, REP; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 595 | def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", |
| 596 | [(X86rep_stos i16)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 597 | Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 598 | def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", |
| 599 | [(X86rep_stos i32)]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 600 | Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP; |
| 601 | |
Chris Lattner | b89abef | 2004-02-14 04:45:37 +0000 | [diff] [blame] | 602 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 603 | //===----------------------------------------------------------------------===// |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 604 | // Input/Output Instructions... |
| 605 | // |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 606 | def IN8rr : I<0xEC, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 607 | "in{b} {%dx, %al|%AL, %DX}", |
| 608 | [(set AL, (readport DX))]>, Imp<[DX], [AL]>; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 609 | def IN16rr : I<0xED, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 610 | "in{w} {%dx, %ax|%AX, %DX}", |
| 611 | [(set AX, (readport DX))]>, Imp<[DX], [AX]>, OpSize; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 612 | def IN32rr : I<0xED, RawFrm, (ops), |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 613 | "in{l} {%dx, %eax|%EAX, %DX}", |
| 614 | [(set EAX, (readport DX))]>, Imp<[DX],[EAX]>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 615 | |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 616 | def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port), |
| 617 | "in{b} {$port, %al|%AL, $port}", |
| 618 | [(set AL, (readport i16immZExt8:$port))]>, |
| 619 | Imp<[], [AL]>; |
| 620 | def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port), |
| 621 | "in{w} {$port, %ax|%AX, $port}", |
| 622 | [(set AX, (readport i16immZExt8:$port))]>, |
| 623 | Imp<[], [AX]>, OpSize; |
| 624 | def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port), |
| 625 | "in{l} {$port, %eax|%EAX, $port}", |
| 626 | [(set EAX, (readport i16immZExt8:$port))]>, |
| 627 | Imp<[],[EAX]>; |
Chris Lattner | 440bbc2 | 2004-04-13 17:19:31 +0000 | [diff] [blame] | 628 | |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 629 | def OUT8rr : I<0xEE, RawFrm, (ops), |
| 630 | "out{b} {%al, %dx|%DX, %AL}", |
| 631 | [(writeport AL, DX)]>, Imp<[DX, AL], []>; |
| 632 | def OUT16rr : I<0xEF, RawFrm, (ops), |
| 633 | "out{w} {%ax, %dx|%DX, %AX}", |
| 634 | [(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize; |
| 635 | def OUT32rr : I<0xEF, RawFrm, (ops), |
| 636 | "out{l} {%eax, %dx|%DX, %EAX}", |
| 637 | [(writeport EAX, DX)]>, Imp<[DX, EAX], []>; |
Chris Lattner | ffff708 | 2004-08-01 07:44:35 +0000 | [diff] [blame] | 638 | |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 639 | def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port), |
| 640 | "out{b} {%al, $port|$port, %AL}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 641 | [(writeport AL, i16immZExt8:$port)]>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 642 | Imp<[AL], []>; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 643 | def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), |
| 644 | "out{w} {%ax, $port|$port, %AX}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 645 | [(writeport AX, i16immZExt8:$port)]>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 646 | Imp<[AX], []>, OpSize; |
Evan Cheng | 8d20223 | 2005-12-05 23:09:43 +0000 | [diff] [blame] | 647 | def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), |
| 648 | "out{l} {%eax, $port|$port, %EAX}", |
Evan Cheng | 5a38e02 | 2005-12-13 00:25:07 +0000 | [diff] [blame] | 649 | [(writeport EAX, i16immZExt8:$port)]>, |
Evan Cheng | a5386b0 | 2005-12-20 07:38:38 +0000 | [diff] [blame] | 650 | Imp<[EAX], []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 651 | |
| 652 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 653 | // Move Instructions... |
| 654 | // |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 655 | def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 656 | "mov{b} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 657 | def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 658 | "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 659 | def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 660 | "mov{l} {$src, $dst|$dst, $src}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 661 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 662 | "mov{b} {$src, $dst|$dst, $src}", |
| 663 | [(set R8:$dst, imm:$src)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 664 | def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 665 | "mov{w} {$src, $dst|$dst, $src}", |
| 666 | [(set R16:$dst, imm:$src)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 667 | def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 668 | "mov{l} {$src, $dst|$dst, $src}", |
| 669 | [(set R32:$dst, imm:$src)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 670 | def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 671 | "mov{b} {$src, $dst|$dst, $src}", |
| 672 | [(store (i8 imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 673 | def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 674 | "mov{w} {$src, $dst|$dst, $src}", |
| 675 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 676 | def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 677 | "mov{l} {$src, $dst|$dst, $src}", |
| 678 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 679 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 680 | def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 681 | "mov{b} {$src, $dst|$dst, $src}", |
| 682 | [(set R8:$dst, (load addr:$src))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 683 | def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 684 | "mov{w} {$src, $dst|$dst, $src}", |
| 685 | [(set R16:$dst, (load addr:$src))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 686 | def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 687 | "mov{l} {$src, $dst|$dst, $src}", |
| 688 | [(set R32:$dst, (load addr:$src))]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 689 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 690 | def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 691 | "mov{b} {$src, $dst|$dst, $src}", |
| 692 | [(store R8:$src, addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 693 | def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 694 | "mov{w} {$src, $dst|$dst, $src}", |
| 695 | [(store R16:$src, addr:$dst)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 696 | def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 697 | "mov{l} {$src, $dst|$dst, $src}", |
| 698 | [(store R32:$src, addr:$dst)]>; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 699 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 700 | //===----------------------------------------------------------------------===// |
| 701 | // Fixed-Register Multiplication and Division Instructions... |
| 702 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 703 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 704 | // Extra precision multiplication |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 705 | def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src", |
| 706 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 707 | // This probably ought to be moved to a def : Pat<> if the |
| 708 | // syntax can be accepted. |
| 709 | [(set AL, (mul AL, R8:$src))]>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 710 | Imp<[AL],[AX]>; // AL,AH = AL*R8 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 711 | def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 712 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 713 | def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>, |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 714 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 715 | def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 716 | "mul{b} $src", |
| 717 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 718 | // This probably ought to be moved to a def : Pat<> if the |
| 719 | // syntax can be accepted. |
| 720 | [(set AL, (mul AL, (loadi8 addr:$src)))]>, |
| 721 | Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 722 | def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 723 | "mul{w} $src", []>, Imp<[AX],[AX,DX]>, |
| 724 | OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 725 | def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 726 | "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32] |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 727 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 728 | def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 729 | Imp<[AL],[AX]>; // AL,AH = AL*R8 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 730 | def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 731 | Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 732 | def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src", []>, |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 733 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 |
| 734 | def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 735 | "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 736 | def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 737 | "imul{w} $src", []>, Imp<[AX],[AX,DX]>, |
| 738 | OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 739 | def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 740 | "imul{l} $src", []>, |
| 741 | Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 742 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 743 | // unsigned division/remainder |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 744 | def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 745 | "div{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 746 | def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 747 | "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 748 | def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 749 | "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 750 | def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 751 | "div{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 752 | def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 753 | "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 754 | def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 755 | "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 756 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 757 | // Signed division/remainder. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 758 | def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 759 | "idiv{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 760 | def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 761 | "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 762 | def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 763 | "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 764 | def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 765 | "idiv{b} $src", []>, Imp<[AX],[AX]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 766 | def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 767 | "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 768 | def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 769 | "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 770 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 771 | // Sign-extenders for division. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 772 | def CBW : I<0x98, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 773 | "{cbtw|cbw}", []>, Imp<[AL],[AH]>; // AX = signext(AL) |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 774 | def CWD : I<0x99, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 775 | "{cwtd|cwd}", []>, Imp<[AX],[DX]>; // DX:AX = signext(AX) |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 776 | def CDQ : I<0x99, RawFrm, (ops), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 777 | "{cltd|cdq}", []>, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 778 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 779 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 780 | //===----------------------------------------------------------------------===// |
| 781 | // Two address Instructions... |
| 782 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 783 | let isTwoAddress = 1 in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 784 | |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 785 | // Conditional moves |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 786 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16 |
| 787 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 788 | "cmovb {$src2, $dst|$dst, $src2}", |
| 789 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 790 | X86_COND_B))]>, |
| 791 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 792 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16] |
| 793 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 794 | "cmovb {$src2, $dst|$dst, $src2}", |
| 795 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 796 | X86_COND_B))]>, |
| 797 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 798 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32 |
| 799 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 800 | "cmovb {$src2, $dst|$dst, $src2}", |
| 801 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 802 | X86_COND_B))]>, |
| 803 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 804 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32] |
| 805 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 806 | "cmovb {$src2, $dst|$dst, $src2}", |
| 807 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 808 | X86_COND_B))]>, |
| 809 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 810 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 811 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16 |
| 812 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 813 | "cmovae {$src2, $dst|$dst, $src2}", |
| 814 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 815 | X86_COND_AE))]>, |
| 816 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 817 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16] |
| 818 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 819 | "cmovae {$src2, $dst|$dst, $src2}", |
| 820 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 821 | X86_COND_AE))]>, |
| 822 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 823 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32 |
| 824 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 825 | "cmovae {$src2, $dst|$dst, $src2}", |
| 826 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 827 | X86_COND_AE))]>, |
| 828 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 829 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32] |
| 830 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 831 | "cmovae {$src2, $dst|$dst, $src2}", |
| 832 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 833 | X86_COND_AE))]>, |
| 834 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 835 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 836 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16 |
| 837 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 838 | "cmove {$src2, $dst|$dst, $src2}", |
| 839 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 840 | X86_COND_E))]>, |
| 841 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 842 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16] |
| 843 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 844 | "cmove {$src2, $dst|$dst, $src2}", |
| 845 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 846 | X86_COND_E))]>, |
| 847 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 848 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32 |
| 849 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 850 | "cmove {$src2, $dst|$dst, $src2}", |
| 851 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 852 | X86_COND_E))]>, |
| 853 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 854 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32] |
| 855 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 856 | "cmove {$src2, $dst|$dst, $src2}", |
| 857 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 858 | X86_COND_E))]>, |
| 859 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 860 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 861 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16 |
| 862 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 863 | "cmovne {$src2, $dst|$dst, $src2}", |
| 864 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 865 | X86_COND_NE))]>, |
| 866 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 867 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16] |
| 868 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 869 | "cmovne {$src2, $dst|$dst, $src2}", |
| 870 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 871 | X86_COND_NE))]>, |
| 872 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 873 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32 |
| 874 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 875 | "cmovne {$src2, $dst|$dst, $src2}", |
| 876 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 877 | X86_COND_NE))]>, |
| 878 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 879 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32] |
| 880 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 881 | "cmovne {$src2, $dst|$dst, $src2}", |
| 882 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 883 | X86_COND_NE))]>, |
| 884 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 885 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 886 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16 |
| 887 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 888 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 889 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 890 | X86_COND_BE))]>, |
| 891 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 892 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16] |
| 893 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 894 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 895 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 896 | X86_COND_BE))]>, |
| 897 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 898 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32 |
| 899 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 900 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 901 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 902 | X86_COND_BE))]>, |
| 903 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 904 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32] |
| 905 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 906 | "cmovbe {$src2, $dst|$dst, $src2}", |
| 907 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 908 | X86_COND_BE))]>, |
| 909 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 910 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 911 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16 |
| 912 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 913 | "cmova {$src2, $dst|$dst, $src2}", |
| 914 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 915 | X86_COND_A))]>, |
| 916 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 917 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16] |
| 918 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 919 | "cmova {$src2, $dst|$dst, $src2}", |
| 920 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 921 | X86_COND_A))]>, |
| 922 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 923 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32 |
| 924 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 925 | "cmova {$src2, $dst|$dst, $src2}", |
| 926 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 927 | X86_COND_A))]>, |
| 928 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 929 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32] |
| 930 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 931 | "cmova {$src2, $dst|$dst, $src2}", |
| 932 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 933 | X86_COND_A))]>, |
| 934 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 935 | |
| 936 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16 |
| 937 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 938 | "cmovl {$src2, $dst|$dst, $src2}", |
| 939 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 940 | X86_COND_L))]>, |
| 941 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 942 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16] |
| 943 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 944 | "cmovl {$src2, $dst|$dst, $src2}", |
| 945 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 946 | X86_COND_L))]>, |
| 947 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 948 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32 |
| 949 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 950 | "cmovl {$src2, $dst|$dst, $src2}", |
| 951 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 952 | X86_COND_L))]>, |
| 953 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 954 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32] |
| 955 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 956 | "cmovl {$src2, $dst|$dst, $src2}", |
| 957 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 958 | X86_COND_L))]>, |
| 959 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 960 | |
| 961 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16 |
| 962 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 963 | "cmovge {$src2, $dst|$dst, $src2}", |
| 964 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 965 | X86_COND_GE))]>, |
| 966 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 967 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16] |
| 968 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 969 | "cmovge {$src2, $dst|$dst, $src2}", |
| 970 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 971 | X86_COND_GE))]>, |
| 972 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 973 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32 |
| 974 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 975 | "cmovge {$src2, $dst|$dst, $src2}", |
| 976 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 977 | X86_COND_GE))]>, |
| 978 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 979 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32] |
| 980 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 981 | "cmovge {$src2, $dst|$dst, $src2}", |
| 982 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 983 | X86_COND_GE))]>, |
| 984 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 985 | |
| 986 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16 |
| 987 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 988 | "cmovle {$src2, $dst|$dst, $src2}", |
| 989 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 990 | X86_COND_LE))]>, |
| 991 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 992 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16] |
| 993 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 994 | "cmovle {$src2, $dst|$dst, $src2}", |
| 995 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 996 | X86_COND_LE))]>, |
| 997 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 998 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32 |
| 999 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 1000 | "cmovle {$src2, $dst|$dst, $src2}", |
| 1001 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1002 | X86_COND_LE))]>, |
| 1003 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1004 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32] |
| 1005 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 1006 | "cmovle {$src2, $dst|$dst, $src2}", |
| 1007 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1008 | X86_COND_LE))]>, |
| 1009 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1010 | |
| 1011 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16 |
| 1012 | (ops R16:$dst, R16:$src1, R16:$src2), |
| 1013 | "cmovg {$src2, $dst|$dst, $src2}", |
| 1014 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1015 | X86_COND_G))]>, |
| 1016 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1017 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16] |
| 1018 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 1019 | "cmovg {$src2, $dst|$dst, $src2}", |
| 1020 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1021 | X86_COND_G))]>, |
| 1022 | TB, OpSize; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1023 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32 |
| 1024 | (ops R32:$dst, R32:$src1, R32:$src2), |
| 1025 | "cmovg {$src2, $dst|$dst, $src2}", |
| 1026 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1027 | X86_COND_G))]>, |
| 1028 | TB; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 1029 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32] |
| 1030 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 1031 | "cmovg {$src2, $dst|$dst, $src2}", |
| 1032 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1033 | X86_COND_G))]>, |
| 1034 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 1035 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1036 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16 |
| 1037 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1038 | "cmovs {$src2, $dst|$dst, $src2}", |
| 1039 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1040 | X86_COND_S))]>, |
| 1041 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1042 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16] |
| 1043 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1044 | "cmovs {$src2, $dst|$dst, $src2}", |
| 1045 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1046 | X86_COND_S))]>, |
| 1047 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1048 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32 |
| 1049 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1050 | "cmovs {$src2, $dst|$dst, $src2}", |
| 1051 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1052 | X86_COND_S))]>, |
| 1053 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1054 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32] |
| 1055 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1056 | "cmovs {$src2, $dst|$dst, $src2}", |
| 1057 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1058 | X86_COND_S))]>, |
| 1059 | TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1060 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1061 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16 |
| 1062 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1063 | "cmovns {$src2, $dst|$dst, $src2}", |
| 1064 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1065 | X86_COND_NS))]>, |
| 1066 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1067 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16] |
| 1068 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1069 | "cmovns {$src2, $dst|$dst, $src2}", |
| 1070 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1071 | X86_COND_NS))]>, |
| 1072 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1073 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32 |
| 1074 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1075 | "cmovns {$src2, $dst|$dst, $src2}", |
| 1076 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1077 | X86_COND_NS))]>, |
| 1078 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1079 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32] |
| 1080 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1081 | "cmovns {$src2, $dst|$dst, $src2}", |
| 1082 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1083 | X86_COND_NS))]>, |
| 1084 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 1085 | |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1086 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16 |
| 1087 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1088 | "cmovp {$src2, $dst|$dst, $src2}", |
| 1089 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1090 | X86_COND_P))]>, |
| 1091 | TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1092 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16] |
| 1093 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1094 | "cmovp {$src2, $dst|$dst, $src2}", |
| 1095 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1096 | X86_COND_P))]>, |
| 1097 | TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1098 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32 |
| 1099 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1100 | "cmovp {$src2, $dst|$dst, $src2}", |
| 1101 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1102 | X86_COND_P))]>, |
| 1103 | TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1104 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32] |
| 1105 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1106 | "cmovp {$src2, $dst|$dst, $src2}", |
| 1107 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1108 | X86_COND_P))]>, |
| 1109 | TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1110 | |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1111 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16 |
| 1112 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1113 | "cmovnp {$src2, $dst|$dst, $src2}", |
| 1114 | [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1115 | X86_COND_NP))]>, |
| 1116 | TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1117 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16] |
| 1118 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1119 | "cmovnp {$src2, $dst|$dst, $src2}", |
| 1120 | [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1121 | X86_COND_NP))]>, |
| 1122 | TB, OpSize; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1123 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32 |
| 1124 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1125 | "cmovnp {$src2, $dst|$dst, $src2}", |
| 1126 | [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1127 | X86_COND_NP))]>, |
| 1128 | TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1129 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32] |
| 1130 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1131 | "cmovnp {$src2, $dst|$dst, $src2}", |
| 1132 | [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1133 | X86_COND_NP))]>, |
| 1134 | TB; |
Chris Lattner | 57fbfb5 | 2005-01-10 22:09:33 +0000 | [diff] [blame] | 1135 | |
| 1136 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1137 | // unary instructions |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1138 | def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst", |
| 1139 | [(set R8:$dst, (ineg R8:$src))]>; |
| 1140 | def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst", |
| 1141 | [(set R16:$dst, (ineg R16:$src))]>, OpSize; |
| 1142 | def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst", |
| 1143 | [(set R32:$dst, (ineg R32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1144 | let isTwoAddress = 0 in { |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1145 | def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1146 | [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1147 | def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1148 | [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1149 | def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1150 | [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>; |
| 1151 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1152 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1153 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1154 | def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst", |
| 1155 | [(set R8:$dst, (not R8:$src))]>; |
| 1156 | def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst", |
| 1157 | [(set R16:$dst, (not R16:$src))]>, OpSize; |
| 1158 | def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst", |
| 1159 | [(set R32:$dst, (not R32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1160 | let isTwoAddress = 0 in { |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1161 | def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1162 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1163 | def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1164 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Evan Cheng | 5ce4edb | 2005-12-13 00:54:44 +0000 | [diff] [blame] | 1165 | def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1166 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1167 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1168 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1169 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1170 | def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst", |
| 1171 | [(set R8:$dst, (add R8:$src, 1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1172 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1173 | def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst", |
| 1174 | [(set R16:$dst, (add R16:$src, 1))]>, OpSize; |
| 1175 | def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst", |
| 1176 | [(set R32:$dst, (add R32:$src, 1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1177 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1178 | let isTwoAddress = 0 in { |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1179 | def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1180 | [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1181 | def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1182 | [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1183 | def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1184 | [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1185 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1186 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1187 | def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst", |
| 1188 | [(set R8:$dst, (add R8:$src, -1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1189 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1190 | def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst", |
| 1191 | [(set R16:$dst, (add R16:$src, -1))]>, OpSize; |
| 1192 | def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst", |
| 1193 | [(set R32:$dst, (add R32:$src, -1))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1194 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1195 | |
| 1196 | let isTwoAddress = 0 in { |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1197 | def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1198 | [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1199 | def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1200 | [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize; |
Evan Cheng | 6cad276 | 2005-12-13 01:02:47 +0000 | [diff] [blame] | 1201 | def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1202 | [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1203 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1204 | |
| 1205 | // Logical operators... |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1206 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1207 | def AND8rr : I<0x20, MRMDestReg, |
| 1208 | (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1209 | "and{b} {$src2, $dst|$dst, $src2}", |
| 1210 | [(set R8:$dst, (and R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1211 | def AND16rr : I<0x21, MRMDestReg, |
| 1212 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1213 | "and{w} {$src2, $dst|$dst, $src2}", |
| 1214 | [(set R16:$dst, (and R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1215 | def AND32rr : I<0x21, MRMDestReg, |
| 1216 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1217 | "and{l} {$src2, $dst|$dst, $src2}", |
| 1218 | [(set R32:$dst, (and R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1219 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1220 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1221 | def AND8rm : I<0x22, MRMSrcMem, |
| 1222 | (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1223 | "and{b} {$src2, $dst|$dst, $src2}", |
| 1224 | [(set R8:$dst, (and R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1225 | def AND16rm : I<0x23, MRMSrcMem, |
| 1226 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1227 | "and{w} {$src2, $dst|$dst, $src2}", |
| 1228 | [(set R16:$dst, (and R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1229 | def AND32rm : I<0x23, MRMSrcMem, |
| 1230 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1231 | "and{l} {$src2, $dst|$dst, $src2}", |
| 1232 | [(set R32:$dst, (and R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1233 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1234 | def AND8ri : Ii8<0x80, MRM4r, |
| 1235 | (ops R8 :$dst, R8 :$src1, i8imm :$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1236 | "and{b} {$src2, $dst|$dst, $src2}", |
| 1237 | [(set R8:$dst, (and R8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1238 | def AND16ri : Ii16<0x81, MRM4r, |
| 1239 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1240 | "and{w} {$src2, $dst|$dst, $src2}", |
| 1241 | [(set R16:$dst, (and R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1242 | def AND32ri : Ii32<0x81, MRM4r, |
| 1243 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1244 | "and{l} {$src2, $dst|$dst, $src2}", |
| 1245 | [(set R32:$dst, (and R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1246 | def AND16ri8 : Ii8<0x83, MRM4r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1247 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1248 | "and{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1249 | [(set R16:$dst, (and R16:$src1, i16immSExt8:$src2))]>, |
| 1250 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1251 | def AND32ri8 : Ii8<0x83, MRM4r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1252 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1253 | "and{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1254 | [(set R32:$dst, (and R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1255 | |
| 1256 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1257 | def AND8mr : I<0x20, MRMDestMem, |
| 1258 | (ops i8mem :$dst, R8 :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1259 | "and{b} {$src, $dst|$dst, $src}", |
| 1260 | [(store (and (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1261 | def AND16mr : I<0x21, MRMDestMem, |
| 1262 | (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1263 | "and{w} {$src, $dst|$dst, $src}", |
| 1264 | [(store (and (load addr:$dst), R16:$src), addr:$dst)]>, |
| 1265 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1266 | def AND32mr : I<0x21, MRMDestMem, |
| 1267 | (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1268 | "and{l} {$src, $dst|$dst, $src}", |
| 1269 | [(store (and (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1270 | def AND8mi : Ii8<0x80, MRM4m, |
| 1271 | (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1272 | "and{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1273 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1274 | def AND16mi : Ii16<0x81, MRM4m, |
| 1275 | (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1276 | "and{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1277 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1278 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1279 | def AND32mi : Ii32<0x81, MRM4m, |
| 1280 | (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1281 | "and{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1282 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1283 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1284 | (ops i16mem:$dst, i16i8imm :$src), |
| 1285 | "and{w} {$src, $dst|$dst, $src}", |
| 1286 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1287 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1288 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1289 | (ops i32mem:$dst, i32i8imm :$src), |
| 1290 | "and{l} {$src, $dst|$dst, $src}", |
Evan Cheng | e3703d4 | 2006-01-14 01:18:49 +0000 | [diff] [blame] | 1291 | [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1292 | } |
| 1293 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1294 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1295 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1296 | def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1297 | "or{b} {$src2, $dst|$dst, $src2}", |
| 1298 | [(set R8:$dst, (or R8:$src1, R8:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1299 | def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1300 | "or{w} {$src2, $dst|$dst, $src2}", |
| 1301 | [(set R16:$dst, (or R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1302 | def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1303 | "or{l} {$src2, $dst|$dst, $src2}", |
| 1304 | [(set R32:$dst, (or R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1305 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1306 | def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1307 | "or{b} {$src2, $dst|$dst, $src2}", |
| 1308 | [(set R8:$dst, (or R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1309 | def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1310 | "or{w} {$src2, $dst|$dst, $src2}", |
| 1311 | [(set R16:$dst, (or R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1312 | def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1313 | "or{l} {$src2, $dst|$dst, $src2}", |
| 1314 | [(set R32:$dst, (or R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1315 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1316 | def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1317 | "or{b} {$src2, $dst|$dst, $src2}", |
| 1318 | [(set R8:$dst, (or R8:$src1, imm:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1319 | def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1320 | "or{w} {$src2, $dst|$dst, $src2}", |
| 1321 | [(set R16:$dst, (or R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1322 | def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1323 | "or{l} {$src2, $dst|$dst, $src2}", |
| 1324 | [(set R32:$dst, (or R32:$src1, imm:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1325 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1326 | def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1327 | "or{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1328 | [(set R16:$dst, (or R16:$src1, i16immSExt8:$src2))]>, OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1329 | def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1330 | "or{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1331 | [(set R32:$dst, (or R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1332 | let isTwoAddress = 0 in { |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1333 | def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1334 | "or{b} {$src, $dst|$dst, $src}", |
| 1335 | [(store (or (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1336 | def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1337 | "or{w} {$src, $dst|$dst, $src}", |
| 1338 | [(store (or (load addr:$dst), R16:$src), addr:$dst)]>, OpSize; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1339 | def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1340 | "or{l} {$src, $dst|$dst, $src}", |
| 1341 | [(store (or (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1342 | def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1343 | "or{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1344 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1345 | def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1346 | "or{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1347 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1348 | OpSize; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 1349 | def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1350 | "or{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1351 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1352 | def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src), |
| 1353 | "or{w} {$src, $dst|$dst, $src}", |
| 1354 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1355 | OpSize; |
| 1356 | def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src), |
| 1357 | "or{l} {$src, $dst|$dst, $src}", |
| 1358 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1359 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1360 | |
| 1361 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1362 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1363 | def XOR8rr : I<0x30, MRMDestReg, |
| 1364 | (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1365 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 1366 | [(set R8:$dst, (xor R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1367 | def XOR16rr : I<0x31, MRMDestReg, |
| 1368 | (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1369 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 1370 | [(set R16:$dst, (xor R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1371 | def XOR32rr : I<0x31, MRMDestReg, |
| 1372 | (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1373 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 1374 | [(set R32:$dst, (xor R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1375 | } |
| 1376 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1377 | def XOR8rm : I<0x32, MRMSrcMem , |
| 1378 | (ops R8 :$dst, R8:$src1, i8mem :$src2), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1379 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 1380 | [(set R8:$dst, (xor R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1381 | def XOR16rm : I<0x33, MRMSrcMem , |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1382 | (ops R16:$dst, R16:$src1, i16mem:$src2), |
| 1383 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 1384 | [(set R16:$dst, (xor R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1385 | def XOR32rm : I<0x33, MRMSrcMem , |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1386 | (ops R32:$dst, R32:$src1, i32mem:$src2), |
| 1387 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 1388 | [(set R32:$dst, (xor R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1389 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1390 | def XOR8ri : Ii8<0x80, MRM6r, |
| 1391 | (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1392 | "xor{b} {$src2, $dst|$dst, $src2}", |
| 1393 | [(set R8:$dst, (xor R8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1394 | def XOR16ri : Ii16<0x81, MRM6r, |
| 1395 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1396 | "xor{w} {$src2, $dst|$dst, $src2}", |
| 1397 | [(set R16:$dst, (xor R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1398 | def XOR32ri : Ii32<0x81, MRM6r, |
| 1399 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1400 | "xor{l} {$src2, $dst|$dst, $src2}", |
| 1401 | [(set R32:$dst, (xor R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1402 | def XOR16ri8 : Ii8<0x83, MRM6r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1403 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1404 | "xor{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1405 | [(set R16:$dst, (xor R16:$src1, i16immSExt8:$src2))]>, |
| 1406 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1407 | def XOR32ri8 : Ii8<0x83, MRM6r, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1408 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1409 | "xor{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1410 | [(set R32:$dst, (xor R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1411 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1412 | def XOR8mr : I<0x30, MRMDestMem, |
| 1413 | (ops i8mem :$dst, R8 :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1414 | "xor{b} {$src, $dst|$dst, $src}", |
| 1415 | [(store (xor (load addr:$dst), R8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1416 | def XOR16mr : I<0x31, MRMDestMem, |
| 1417 | (ops i16mem:$dst, R16:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1418 | "xor{w} {$src, $dst|$dst, $src}", |
| 1419 | [(store (xor (load addr:$dst), R16:$src), addr:$dst)]>, |
| 1420 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1421 | def XOR32mr : I<0x31, MRMDestMem, |
| 1422 | (ops i32mem:$dst, R32:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1423 | "xor{l} {$src, $dst|$dst, $src}", |
| 1424 | [(store (xor (load addr:$dst), R32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1425 | def XOR8mi : Ii8<0x80, MRM6m, |
| 1426 | (ops i8mem :$dst, i8imm :$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1427 | "xor{b} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1428 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1429 | def XOR16mi : Ii16<0x81, MRM6m, |
| 1430 | (ops i16mem:$dst, i16imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1431 | "xor{w} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1432 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1433 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1434 | def XOR32mi : Ii32<0x81, MRM6m, |
| 1435 | (ops i32mem:$dst, i32imm:$src), |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1436 | "xor{l} {$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1437 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1438 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1439 | (ops i16mem:$dst, i16i8imm :$src), |
| 1440 | "xor{w} {$src, $dst|$dst, $src}", |
| 1441 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1442 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1443 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1444 | (ops i32mem:$dst, i32i8imm :$src), |
| 1445 | "xor{l} {$src, $dst|$dst, $src}", |
| 1446 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1447 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1448 | |
| 1449 | // Shift instructions |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1450 | def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1451 | "shl{b} {%cl, $dst|$dst, %CL}", |
| 1452 | [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1453 | def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1454 | "shl{w} {%cl, $dst|$dst, %CL}", |
| 1455 | [(set R16:$dst, (shl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1456 | def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1457 | "shl{l} {%cl, $dst|$dst, %CL}", |
| 1458 | [(set R32:$dst, (shl R32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1459 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1460 | def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1461 | "shl{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1462 | [(set R8:$dst, (shl R8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1463 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1464 | def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1465 | "shl{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1466 | [(set R16:$dst, (shl R16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1467 | def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1468 | "shl{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1469 | [(set R32:$dst, (shl R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1470 | } |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1471 | |
| 1472 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1473 | def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1474 | "shl{b} {%cl, $dst|$dst, %CL}", |
| 1475 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1476 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1477 | def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1478 | "shl{w} {%cl, $dst|$dst, %CL}", |
| 1479 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1480 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1481 | def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1482 | "shl{l} {%cl, $dst|$dst, %CL}", |
| 1483 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1484 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1485 | def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1486 | "shl{b} {$src, $dst|$dst, $src}", |
| 1487 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1488 | def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1489 | "shl{w} {$src, $dst|$dst, $src}", |
| 1490 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1491 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1492 | def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1493 | "shl{l} {$src, $dst|$dst, $src}", |
| 1494 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1495 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1496 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1497 | def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1498 | "shr{b} {%cl, $dst|$dst, %CL}", |
| 1499 | [(set R8:$dst, (srl R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1500 | def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1501 | "shr{w} {%cl, $dst|$dst, %CL}", |
| 1502 | [(set R16:$dst, (srl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1503 | def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1504 | "shr{l} {%cl, $dst|$dst, %CL}", |
| 1505 | [(set R32:$dst, (srl R32:$src, CL))]>, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1506 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1507 | def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1508 | "shr{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1509 | [(set R8:$dst, (srl R8:$src1, (i8 imm:$src2)))]>; |
| 1510 | def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1511 | "shr{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1512 | [(set R16:$dst, (srl R16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 1513 | def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1514 | "shr{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1515 | [(set R32:$dst, (srl R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1516 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1517 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1518 | def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1519 | "shr{b} {%cl, $dst|$dst, %CL}", |
| 1520 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1521 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1522 | def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1523 | "shr{w} {%cl, $dst|$dst, %CL}", |
| 1524 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1525 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1526 | def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1527 | "shr{l} {%cl, $dst|$dst, %CL}", |
| 1528 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1529 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1530 | def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1531 | "shr{b} {$src, $dst|$dst, $src}", |
| 1532 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1533 | def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1534 | "shr{w} {$src, $dst|$dst, $src}", |
| 1535 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1536 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1537 | def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1538 | "shr{l} {$src, $dst|$dst, $src}", |
| 1539 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1540 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1541 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1542 | def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1543 | "sar{b} {%cl, $dst|$dst, %CL}", |
| 1544 | [(set R8:$dst, (sra R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1545 | def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1546 | "sar{w} {%cl, $dst|$dst, %CL}", |
| 1547 | [(set R16:$dst, (sra R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1548 | def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), |
Evan Cheng | 640f299 | 2005-12-01 00:43:55 +0000 | [diff] [blame] | 1549 | "sar{l} {%cl, $dst|$dst, %CL}", |
| 1550 | [(set R32:$dst, (sra R32:$src, CL))]>, Imp<[CL],[]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1551 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1552 | def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1553 | "sar{b} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1554 | [(set R8:$dst, (sra R8:$src1, (i8 imm:$src2)))]>; |
| 1555 | def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1556 | "sar{w} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1557 | [(set R16:$dst, (sra R16:$src1, (i8 imm:$src2)))]>, |
| 1558 | OpSize; |
| 1559 | def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1560 | "sar{l} {$src2, $dst|$dst, $src2}", |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1561 | [(set R32:$dst, (sra R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1562 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1563 | def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1564 | "sar{b} {%cl, $dst|$dst, %CL}", |
| 1565 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1566 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1567 | def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1568 | "sar{w} {%cl, $dst|$dst, %CL}", |
| 1569 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1570 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1571 | def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1572 | "sar{l} {%cl, $dst|$dst, %CL}", |
| 1573 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1574 | Imp<[CL],[]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1575 | def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1576 | "sar{b} {$src, $dst|$dst, $src}", |
| 1577 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1578 | def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1579 | "sar{w} {$src, $dst|$dst, $src}", |
| 1580 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1581 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1582 | def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1583 | "sar{l} {$src, $dst|$dst, $src}", |
| 1584 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1585 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1586 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1587 | // Rotate instructions |
| 1588 | // FIXME: provide shorter instructions when imm8 == 1 |
| 1589 | def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1590 | "rol{b} {%cl, $dst|$dst, %CL}", |
| 1591 | [(set R8:$dst, (rotl R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1592 | def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1593 | "rol{w} {%cl, $dst|$dst, %CL}", |
| 1594 | [(set R16:$dst, (rotl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1595 | def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1596 | "rol{l} {%cl, $dst|$dst, %CL}", |
| 1597 | [(set R32:$dst, (rotl R32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1598 | |
| 1599 | def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1600 | "rol{b} {$src2, $dst|$dst, $src2}", |
| 1601 | [(set R8:$dst, (rotl R8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1602 | def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1603 | "rol{w} {$src2, $dst|$dst, $src2}", |
| 1604 | [(set R16:$dst, (rotl R16:$src1, (i8 imm:$src2)))]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1605 | def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1606 | "rol{l} {$src2, $dst|$dst, $src2}", |
| 1607 | [(set R32:$dst, (rotl R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1608 | |
| 1609 | let isTwoAddress = 0 in { |
| 1610 | def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1611 | "rol{b} {%cl, $dst|$dst, %CL}", |
| 1612 | [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1613 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1614 | def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1615 | "rol{w} {%cl, $dst|$dst, %CL}", |
| 1616 | [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1617 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1618 | def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1619 | "rol{l} {%cl, $dst|$dst, %CL}", |
| 1620 | [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1621 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1622 | def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1623 | "rol{b} {$src, $dst|$dst, $src}", |
| 1624 | [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1625 | def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1626 | "rol{w} {$src, $dst|$dst, $src}", |
| 1627 | [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1628 | OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1629 | def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1630 | "rol{l} {$src, $dst|$dst, $src}", |
| 1631 | [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1632 | } |
| 1633 | |
| 1634 | def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1635 | "ror{b} {%cl, $dst|$dst, %CL}", |
| 1636 | [(set R8:$dst, (rotr R8:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1637 | def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1638 | "ror{w} {%cl, $dst|$dst, %CL}", |
| 1639 | [(set R16:$dst, (rotr R16:$src, CL))]>, Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1640 | def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1641 | "ror{l} {%cl, $dst|$dst, %CL}", |
| 1642 | [(set R32:$dst, (rotr R32:$src, CL))]>, Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1643 | |
| 1644 | def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1645 | "ror{b} {$src2, $dst|$dst, $src2}", |
| 1646 | [(set R8:$dst, (rotr R8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1647 | def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1648 | "ror{w} {$src2, $dst|$dst, $src2}", |
| 1649 | [(set R16:$dst, (rotr R16:$src1, (i8 imm:$src2)))]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1650 | def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1651 | "ror{l} {$src2, $dst|$dst, $src2}", |
| 1652 | [(set R32:$dst, (rotr R32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1653 | let isTwoAddress = 0 in { |
| 1654 | def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1655 | "ror{b} {%cl, $dst|$dst, %CL}", |
| 1656 | [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>, |
| 1657 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1658 | def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1659 | "ror{w} {%cl, $dst|$dst, %CL}", |
| 1660 | [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 1661 | Imp<[CL],[]>, OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1662 | def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1663 | "ror{l} {%cl, $dst|$dst, %CL}", |
| 1664 | [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>, |
| 1665 | Imp<[CL],[]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1666 | def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1667 | "ror{b} {$src, $dst|$dst, $src}", |
| 1668 | [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1669 | def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1670 | "ror{w} {$src, $dst|$dst, $src}", |
| 1671 | [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1672 | OpSize; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1673 | def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src), |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1674 | "ror{l} {$src, $dst|$dst, $src}", |
| 1675 | [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1676 | } |
| 1677 | |
| 1678 | |
| 1679 | |
| 1680 | // Double shift instructions (generalizations of rotate) |
| 1681 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1682 | def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1683 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1684 | [(set R32:$dst, (X86shld R32:$src1, R32:$src2, CL))]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1685 | Imp<[CL],[]>, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1686 | def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1687 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1688 | [(set R32:$dst, (X86shrd R32:$src1, R32:$src2, CL))]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1689 | Imp<[CL],[]>, TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1690 | def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1691 | "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1692 | [(set R16:$dst, (X86shld R16:$src1, R16:$src2, CL))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1693 | Imp<[CL],[]>, TB, OpSize; |
| 1694 | def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1695 | "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1696 | [(set R16:$dst, (X86shrd R16:$src1, R16:$src2, CL))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1697 | Imp<[CL],[]>, TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1698 | |
| 1699 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1700 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
| 1701 | (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1702 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1703 | [(set R32:$dst, (X86shld R32:$src1, R32:$src2, |
| 1704 | (i8 imm:$src3)))]>, |
| 1705 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1706 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
| 1707 | (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1708 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1709 | [(set R32:$dst, (X86shrd R32:$src1, R32:$src2, |
| 1710 | (i8 imm:$src3)))]>, |
| 1711 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1712 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
| 1713 | (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1714 | "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1715 | [(set R16:$dst, (X86shld R16:$src1, R16:$src2, |
| 1716 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1717 | TB, OpSize; |
| 1718 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
| 1719 | (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1720 | "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1721 | [(set R16:$dst, (X86shrd R16:$src1, R16:$src2, |
| 1722 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1723 | TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1724 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 1725 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1726 | let isTwoAddress = 0 in { |
| 1727 | def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1728 | "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1729 | [(store (X86shld (loadi32 addr:$dst), R32:$src2, CL), |
| 1730 | addr:$dst)]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1731 | Imp<[CL],[]>, TB; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1732 | def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1733 | "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1734 | [(store (X86shrd (loadi32 addr:$dst), R32:$src2, CL), |
| 1735 | addr:$dst)]>, |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1736 | Imp<[CL],[]>, TB; |
| 1737 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
| 1738 | (ops i32mem:$dst, R32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1739 | "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1740 | [(store (X86shld (loadi32 addr:$dst), R32:$src2, |
| 1741 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1742 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1743 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
| 1744 | (ops i32mem:$dst, R32:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1745 | "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1746 | [(store (X86shrd (loadi32 addr:$dst), R32:$src2, |
| 1747 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1748 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1749 | |
| 1750 | def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1751 | "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1752 | [(store (X86shld (loadi16 addr:$dst), R16:$src2, CL), |
| 1753 | addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1754 | Imp<[CL],[]>, TB, OpSize; |
| 1755 | def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1756 | "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", |
| 1757 | [(store (X86shrd (loadi16 addr:$dst), R16:$src2, CL), |
| 1758 | addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1759 | Imp<[CL],[]>, TB, OpSize; |
| 1760 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
| 1761 | (ops i16mem:$dst, R16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1762 | "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1763 | [(store (X86shld (loadi16 addr:$dst), R16:$src2, |
| 1764 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1765 | TB, OpSize; |
| 1766 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
| 1767 | (ops i16mem:$dst, R16:$src2, i8imm:$src3), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1768 | "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1769 | [(store (X86shrd (loadi16 addr:$dst), R16:$src2, |
| 1770 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1771 | TB, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1772 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1773 | |
| 1774 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1775 | // Arithmetic. |
| 1776 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1777 | def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1778 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1779 | [(set R8:$dst, (add R8:$src1, R8:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1780 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1781 | def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1782 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1783 | [(set R16:$dst, (add R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1784 | def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1785 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1786 | [(set R32:$dst, (add R32:$src1, R32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1787 | } // end isConvertibleToThreeAddress |
| 1788 | } // end isCommutable |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1789 | def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1790 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1791 | [(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1792 | def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1793 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1794 | [(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1795 | def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | ab24ed2 | 2005-12-09 22:48:48 +0000 | [diff] [blame] | 1796 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1797 | [(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1798 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1799 | def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1800 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1801 | [(set R8:$dst, (add R8:$src1, imm:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1802 | |
| 1803 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1804 | def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1805 | "add{w} {$src2, $dst|$dst, $src2}", |
| 1806 | [(set R16:$dst, (add R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1807 | def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1808 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1809 | [(set R32:$dst, (add R32:$src1, imm:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1810 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1811 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1812 | // FIXME: move ADD16ri8 above ADD16ri to optimize for space. |
| 1813 | def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1814 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1815 | [(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>, |
| 1816 | OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1817 | def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1818 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1819 | [(set R32:$dst, (add R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1820 | |
| 1821 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1822 | def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1823 | "add{b} {$src2, $dst|$dst, $src2}", |
| 1824 | [(store (add (load addr:$dst), R8:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1825 | def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1826 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1827 | [(store (add (load addr:$dst), R16:$src2), addr:$dst)]>, |
| 1828 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1829 | def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1830 | "add{l} {$src2, $dst|$dst, $src2}", |
| 1831 | [(store (add (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1832 | def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1833 | "add{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1834 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1835 | def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1836 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1837 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1838 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1839 | def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1840 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1841 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1842 | def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1843 | "add{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1844 | [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1845 | OpSize; |
Evan Cheng | ee93f9d | 2005-12-12 19:45:23 +0000 | [diff] [blame] | 1846 | def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1847 | "add{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1848 | [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1849 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1850 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1851 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1852 | def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1853 | "adc{l} {$src2, $dst|$dst, $src2}", |
| 1854 | [(set R32:$dst, (X86adc R32:$src1, R32:$src2))]>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1855 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1856 | def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1857 | "adc{l} {$src2, $dst|$dst, $src2}", |
| 1858 | [(set R32:$dst, (X86adc R32:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1859 | def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1860 | "adc{l} {$src2, $dst|$dst, $src2}", |
| 1861 | [(set R32:$dst, (X86adc R32:$src1, imm:$src2))]>; |
| 1862 | def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1863 | "adc{l} {$src2, $dst|$dst, $src2}", |
| 1864 | [(set R32:$dst, (X86adc R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1865 | |
| 1866 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1867 | def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1868 | "adc{l} {$src2, $dst|$dst, $src2}", |
| 1869 | [(store (X86adc (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1870 | def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1871 | "adc{l} {$src2, $dst|$dst, $src2}", |
| 1872 | [(store (X86adc (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
| 1873 | def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1874 | "adc{l} {$src2, $dst|$dst, $src2}", |
| 1875 | [(store (X86adc (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1876 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1877 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1878 | def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1879 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1880 | [(set R8:$dst, (sub R8:$src1, R8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1881 | def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1882 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1883 | [(set R16:$dst, (sub R16:$src1, R16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1884 | def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1885 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1886 | [(set R32:$dst, (sub R32:$src1, R32:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1887 | def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1888 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1889 | [(set R8:$dst, (sub R8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1890 | def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1891 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1892 | [(set R16:$dst, (sub R16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1893 | def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1894 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1895 | [(set R32:$dst, (sub R32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1896 | |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1897 | def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1898 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1899 | [(set R8:$dst, (sub R8:$src1, imm:$src2))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1900 | def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 1901 | "sub{w} {$src2, $dst|$dst, $src2}", |
| 1902 | [(set R16:$dst, (sub R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1903 | def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 1904 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1905 | [(set R32:$dst, (sub R32:$src1, imm:$src2))]>; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1906 | def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1907 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1908 | [(set R16:$dst, (sub R16:$src1, i16immSExt8:$src2))]>, |
| 1909 | OpSize; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1910 | def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1911 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1912 | [(set R32:$dst, (sub R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1913 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1914 | def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1915 | "sub{b} {$src2, $dst|$dst, $src2}", |
| 1916 | [(store (sub (load addr:$dst), R8:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1917 | def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1918 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1919 | [(store (sub (load addr:$dst), R16:$src2), addr:$dst)]>, |
| 1920 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1921 | def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1922 | "sub{l} {$src2, $dst|$dst, $src2}", |
| 1923 | [(store (sub (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1924 | def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1925 | "sub{b} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1926 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1927 | def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1928 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1929 | [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1930 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1931 | def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1932 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1933 | [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1934 | def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1935 | "sub{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1936 | [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1937 | OpSize; |
Evan Cheng | d160d48 | 2005-12-12 21:54:05 +0000 | [diff] [blame] | 1938 | def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1939 | "sub{l} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1940 | [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1941 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1942 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1943 | def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1944 | "sbb{l} {$src2, $dst|$dst, $src2}", |
| 1945 | [(set R32:$dst, (X86sbb R32:$src1, R32:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1946 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1947 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1948 | def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1949 | "sbb{l} {$src2, $dst|$dst, $src2}", |
| 1950 | [(store (X86sbb (load addr:$dst), R32:$src2), addr:$dst)]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1951 | def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1952 | "sbb{b} {$src2, $dst|$dst, $src2}", |
| 1953 | [(store (X86sbb (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1954 | def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1955 | "sbb{w} {$src2, $dst|$dst, $src2}", |
| 1956 | [(store (X86sbb (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
| 1957 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1958 | def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1959 | "sbb{l} {$src2, $dst|$dst, $src2}", |
| 1960 | [(store (X86sbb (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
| 1961 | def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i16i8imm :$src2), |
| 1962 | "sbb{w} {$src2, $dst|$dst, $src2}", |
| 1963 | [(store (X86sbb (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 1964 | OpSize; |
| 1965 | def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2), |
| 1966 | "sbb{l} {$src2, $dst|$dst, $src2}", |
| 1967 | [(store (X86sbb (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1968 | } |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1969 | def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1970 | "sbb{b} {$src2, $dst|$dst, $src2}", |
| 1971 | [(set R8:$dst, (X86sbb R8:$src1, imm:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1972 | def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1973 | "sbb{w} {$src2, $dst|$dst, $src2}", |
| 1974 | [(set R16:$dst, (X86sbb R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1975 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1976 | def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1977 | "sbb{l} {$src2, $dst|$dst, $src2}", |
| 1978 | [(set R32:$dst, (X86sbb R32:$src1, (load addr:$src2)))]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 1979 | def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2), |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1980 | "sbb{l} {$src2, $dst|$dst, $src2}", |
| 1981 | [(set R32:$dst, (X86sbb R32:$src1, imm:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 1982 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1983 | def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 1984 | "sbb{w} {$src2, $dst|$dst, $src2}", |
| 1985 | [(set R16:$dst, (X86sbb R16:$src1, i16immSExt8:$src2))]>, |
| 1986 | OpSize; |
| 1987 | def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 1988 | "sbb{l} {$src2, $dst|$dst, $src2}", |
| 1989 | [(set R32:$dst, (X86sbb R32:$src1, i32immSExt8:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1990 | |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1991 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1992 | def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1993 | "imul{w} {$src2, $dst|$dst, $src2}", |
| 1994 | [(set R16:$dst, (mul R16:$src1, R16:$src2))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1995 | def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 1996 | "imul{l} {$src2, $dst|$dst, $src2}", |
| 1997 | [(set R32:$dst, (mul R32:$src1, R32:$src2))]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 1998 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1999 | def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2000 | "imul{w} {$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2001 | [(set R16:$dst, (mul R16:$src1, (load addr:$src2)))]>, |
| 2002 | TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2003 | def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2004 | "imul{l} {$src2, $dst|$dst, $src2}", |
| 2005 | [(set R32:$dst, (mul R32:$src1, (load addr:$src2)))]>, TB; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2006 | |
| 2007 | } // end Two Address instructions |
| 2008 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2009 | // Suprisingly enough, these are not two address instructions! |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2010 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16 |
| 2011 | (ops R16:$dst, R16:$src1, i16imm:$src2), |
Chris Lattner | 78432fe | 2005-11-17 02:01:55 +0000 | [diff] [blame] | 2012 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2013 | [(set R16:$dst, (mul R16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2014 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32 |
| 2015 | (ops R32:$dst, R32:$src1, i32imm:$src2), |
Chris Lattner | 7a12537 | 2005-11-16 22:59:19 +0000 | [diff] [blame] | 2016 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 2017 | [(set R32:$dst, (mul R32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2018 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8 |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 2019 | (ops R16:$dst, R16:$src1, i16i8imm:$src2), |
| 2020 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2021 | [(set R16:$dst, (mul R16:$src1, i16immSExt8:$src2))]>, |
| 2022 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2023 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8 |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 2024 | (ops R32:$dst, R32:$src1, i32i8imm:$src2), |
| 2025 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2026 | [(set R32:$dst, (mul R32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2027 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2028 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2029 | (ops R16:$dst, i16mem:$src1, i16imm:$src2), |
| 2030 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 2031 | [(set R16:$dst, (mul (load addr:$src1), imm:$src2))]>, |
| 2032 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2033 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32 |
| 2034 | (ops R32:$dst, i32mem:$src1, i32imm:$src2), |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2035 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
| 2036 | [(set R32:$dst, (mul (load addr:$src1), imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2037 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2038 | (ops R16:$dst, i16mem:$src1, i16i8imm :$src2), |
| 2039 | "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2040 | [(set R16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>, |
| 2041 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2042 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8 |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2043 | (ops R32:$dst, i32mem:$src1, i32i8imm: $src2), |
| 2044 | "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2045 | [(set R32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2046 | |
| 2047 | //===----------------------------------------------------------------------===// |
| 2048 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2049 | // |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2050 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 2051 | def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2052 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2053 | [(X86test R8:$src1, R8:$src2)]>; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 2054 | def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2055 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2056 | [(X86test R16:$src1, R16:$src2)]>, OpSize; |
Chris Lattner | 36b6890 | 2004-08-10 21:21:30 +0000 | [diff] [blame] | 2057 | def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2058 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2059 | [(X86test R32:$src1, R32:$src2)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2060 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2061 | def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2062 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2063 | [(X86test (loadi8 addr:$src1), R8:$src2)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2064 | def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2065 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2066 | [(X86test (loadi16 addr:$src1), R16:$src2)]>, |
| 2067 | OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2068 | def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2069 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2070 | [(X86test (loadi32 addr:$src1), R32:$src2)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2071 | def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2072 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2073 | [(X86test R8:$src1, (loadi8 addr:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2074 | def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2075 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2076 | [(X86test R16:$src1, (loadi16 addr:$src2))]>, |
| 2077 | OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2078 | def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2079 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2080 | [(X86test R32:$src1, (loadi32 addr:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2081 | |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2082 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8 |
| 2083 | (ops R8:$src1, i8imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2084 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2085 | [(X86test R8:$src1, imm:$src2)]>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2086 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16 |
| 2087 | (ops R16:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2088 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2089 | [(X86test R16:$src1, imm:$src2)]>, OpSize; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2090 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32 |
| 2091 | (ops R32:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2092 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2093 | [(X86test R32:$src1, imm:$src2)]>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2094 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2095 | (ops i8mem:$src1, i8imm:$src2), |
| 2096 | "test{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2097 | [(X86test (loadi8 addr:$src1), imm:$src2)]>; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2098 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
| 2099 | (ops i16mem:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2100 | "test{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2101 | [(X86test (loadi16 addr:$src1), imm:$src2)]>, |
| 2102 | OpSize; |
Chris Lattner | 707c6fe | 2004-10-04 01:38:10 +0000 | [diff] [blame] | 2103 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
| 2104 | (ops i32mem:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2105 | "test{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2106 | [(X86test (loadi32 addr:$src1), imm:$src2)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2107 | |
| 2108 | |
| 2109 | // Condition code ops, incl. set if equal/not equal/... |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2110 | def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH |
| 2111 | def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2112 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2113 | def SETEr : I<0x94, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2114 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2115 | "sete $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2116 | [(set R8:$dst, (X86setcc X86_COND_E))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2117 | TB; // R8 = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2118 | def SETEm : I<0x94, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2119 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2120 | "sete $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2121 | [(store (X86setcc X86_COND_E), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2122 | TB; // [mem8] = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2123 | def SETNEr : I<0x95, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2124 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2125 | "setne $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2126 | [(set R8:$dst, (X86setcc X86_COND_NE))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2127 | TB; // R8 = != |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2128 | def SETNEm : I<0x95, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2129 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2130 | "setne $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2131 | [(store (X86setcc X86_COND_NE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2132 | TB; // [mem8] = != |
| 2133 | def SETLr : I<0x9C, MRM0r, |
| 2134 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2135 | "setl $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2136 | [(set R8:$dst, (X86setcc X86_COND_L))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2137 | TB; // R8 = < signed |
| 2138 | def SETLm : I<0x9C, MRM0m, |
| 2139 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2140 | "setl $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2141 | [(store (X86setcc X86_COND_L), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2142 | TB; // [mem8] = < signed |
| 2143 | def SETGEr : I<0x9D, MRM0r, |
| 2144 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2145 | "setge $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2146 | [(set R8:$dst, (X86setcc X86_COND_GE))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2147 | TB; // R8 = >= signed |
| 2148 | def SETGEm : I<0x9D, MRM0m, |
| 2149 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2150 | "setge $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2151 | [(store (X86setcc X86_COND_GE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2152 | TB; // [mem8] = >= signed |
| 2153 | def SETLEr : I<0x9E, MRM0r, |
| 2154 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2155 | "setle $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2156 | [(set R8:$dst, (X86setcc X86_COND_LE))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2157 | TB; // R8 = <= signed |
| 2158 | def SETLEm : I<0x9E, MRM0m, |
| 2159 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2160 | "setle $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2161 | [(store (X86setcc X86_COND_LE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2162 | TB; // [mem8] = <= signed |
| 2163 | def SETGr : I<0x9F, MRM0r, |
| 2164 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2165 | "setg $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2166 | [(set R8:$dst, (X86setcc X86_COND_G))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2167 | TB; // R8 = > signed |
| 2168 | def SETGm : I<0x9F, MRM0m, |
| 2169 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2170 | "setg $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2171 | [(store (X86setcc X86_COND_G), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2172 | TB; // [mem8] = > signed |
| 2173 | |
| 2174 | def SETBr : I<0x92, MRM0r, |
| 2175 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2176 | "setb $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2177 | [(set R8:$dst, (X86setcc X86_COND_B))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2178 | TB; // R8 = < unsign |
| 2179 | def SETBm : I<0x92, MRM0m, |
| 2180 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2181 | "setb $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2182 | [(store (X86setcc X86_COND_B), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2183 | TB; // [mem8] = < unsign |
| 2184 | def SETAEr : I<0x93, MRM0r, |
| 2185 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2186 | "setae $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2187 | [(set R8:$dst, (X86setcc X86_COND_AE))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2188 | TB; // R8 = >= unsign |
| 2189 | def SETAEm : I<0x93, MRM0m, |
| 2190 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2191 | "setae $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2192 | [(store (X86setcc X86_COND_AE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2193 | TB; // [mem8] = >= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2194 | def SETBEr : I<0x96, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2195 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2196 | "setbe $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2197 | [(set R8:$dst, (X86setcc X86_COND_BE))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2198 | TB; // R8 = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2199 | def SETBEm : I<0x96, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2200 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2201 | "setbe $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2202 | [(store (X86setcc X86_COND_BE), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2203 | TB; // [mem8] = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2204 | def SETAr : I<0x97, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2205 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2206 | "seta $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2207 | [(set R8:$dst, (X86setcc X86_COND_A))]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2208 | TB; // R8 = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2209 | def SETAm : I<0x97, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2210 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2211 | "seta $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2212 | [(store (X86setcc X86_COND_A), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2213 | TB; // [mem8] = > signed |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2214 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2215 | def SETSr : I<0x98, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2216 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2217 | "sets $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2218 | [(set R8:$dst, (X86setcc X86_COND_S))]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2219 | TB; // R8 = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2220 | def SETSm : I<0x98, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2221 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2222 | "sets $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2223 | [(store (X86setcc X86_COND_S), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2224 | TB; // [mem8] = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2225 | def SETNSr : I<0x99, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2226 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2227 | "setns $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2228 | [(set R8:$dst, (X86setcc X86_COND_NS))]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2229 | TB; // R8 = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2230 | def SETNSm : I<0x99, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2231 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2232 | "setns $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2233 | [(store (X86setcc X86_COND_NS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2234 | TB; // [mem8] = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2235 | def SETPr : I<0x9A, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2236 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2237 | "setp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2238 | [(set R8:$dst, (X86setcc X86_COND_P))]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2239 | TB; // R8 = parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2240 | def SETPm : I<0x9A, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2241 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2242 | "setp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2243 | [(store (X86setcc X86_COND_P), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2244 | TB; // [mem8] = parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2245 | def SETNPr : I<0x9B, MRM0r, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2246 | (ops R8 :$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2247 | "setnp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2248 | [(set R8:$dst, (X86setcc X86_COND_NP))]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2249 | TB; // R8 = not parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2250 | def SETNPm : I<0x9B, MRM0m, |
Chris Lattner | 9fb2422 | 2005-12-21 05:34:58 +0000 | [diff] [blame] | 2251 | (ops i8mem:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2252 | "setnp $dst", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2253 | [(store (X86setcc X86_COND_NP), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2254 | TB; // [mem8] = not parity |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2255 | |
| 2256 | // Integer comparisons |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2257 | def CMP8rr : I<0x38, MRMDestReg, |
| 2258 | (ops R8 :$src1, R8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2259 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2260 | [(X86cmp R8:$src1, R8:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2261 | def CMP16rr : I<0x39, MRMDestReg, |
| 2262 | (ops R16:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2263 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2264 | [(X86cmp R16:$src1, R16:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2265 | def CMP32rr : I<0x39, MRMDestReg, |
| 2266 | (ops R32:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2267 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2268 | [(X86cmp R32:$src1, R32:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2269 | def CMP8mr : I<0x38, MRMDestMem, |
| 2270 | (ops i8mem :$src1, R8 :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2271 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2272 | [(X86cmp (loadi8 addr:$src1), R8:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2273 | def CMP16mr : I<0x39, MRMDestMem, |
| 2274 | (ops i16mem:$src1, R16:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2275 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2276 | [(X86cmp (loadi16 addr:$src1), R16:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2277 | def CMP32mr : I<0x39, MRMDestMem, |
| 2278 | (ops i32mem:$src1, R32:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2279 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2280 | [(X86cmp (loadi32 addr:$src1), R32:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2281 | def CMP8rm : I<0x3A, MRMSrcMem, |
| 2282 | (ops R8 :$src1, i8mem :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2283 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2284 | [(X86cmp R8:$src1, (loadi8 addr:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2285 | def CMP16rm : I<0x3B, MRMSrcMem, |
| 2286 | (ops R16:$src1, i16mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2287 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2288 | [(X86cmp R16:$src1, (loadi16 addr:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2289 | def CMP32rm : I<0x3B, MRMSrcMem, |
| 2290 | (ops R32:$src1, i32mem:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2291 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2292 | [(X86cmp R32:$src1, (loadi32 addr:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2293 | def CMP8ri : Ii8<0x80, MRM7r, |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2294 | (ops R8:$src1, i8imm:$src2), |
| 2295 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2296 | [(X86cmp R8:$src1, imm:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2297 | def CMP16ri : Ii16<0x81, MRM7r, |
| 2298 | (ops R16:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2299 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2300 | [(X86cmp R16:$src1, imm:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2301 | def CMP32ri : Ii32<0x81, MRM7r, |
| 2302 | (ops R32:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2303 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2304 | [(X86cmp R32:$src1, imm:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2305 | def CMP8mi : Ii8 <0x80, MRM7m, |
| 2306 | (ops i8mem :$src1, i8imm :$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2307 | "cmp{b} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2308 | [(X86cmp (loadi8 addr:$src1), imm:$src2)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2309 | def CMP16mi : Ii16<0x81, MRM7m, |
| 2310 | (ops i16mem:$src1, i16imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2311 | "cmp{w} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2312 | [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2313 | def CMP32mi : Ii32<0x81, MRM7m, |
| 2314 | (ops i32mem:$src1, i32imm:$src2), |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 2315 | "cmp{l} {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2316 | [(X86cmp (loadi32 addr:$src1), imm:$src2)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2317 | |
| 2318 | // Sign/Zero extenders |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2319 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2320 | "movs{bw|x} {$src, $dst|$dst, $src}", |
| 2321 | [(set R16:$dst, (sext R8:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2322 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2323 | "movs{bw|x} {$src, $dst|$dst, $src}", |
| 2324 | [(set R16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2325 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2326 | "movs{bl|x} {$src, $dst|$dst, $src}", |
| 2327 | [(set R32:$dst, (sext R8:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2328 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2329 | "movs{bl|x} {$src, $dst|$dst, $src}", |
| 2330 | [(set R32:$dst, (sextloadi32i8 addr:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2331 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2332 | "movs{wl|x} {$src, $dst|$dst, $src}", |
| 2333 | [(set R32:$dst, (sext R16:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2334 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2335 | "movs{wl|x} {$src, $dst|$dst, $src}", |
| 2336 | [(set R32:$dst, (sextloadi32i16 addr:$src))]>, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 2337 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2338 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2339 | "movz{bw|x} {$src, $dst|$dst, $src}", |
| 2340 | [(set R16:$dst, (zext R8:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2341 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2342 | "movz{bw|x} {$src, $dst|$dst, $src}", |
| 2343 | [(set R16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2344 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2345 | "movz{bl|x} {$src, $dst|$dst, $src}", |
| 2346 | [(set R32:$dst, (zext R8:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2347 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2348 | "movz{bl|x} {$src, $dst|$dst, $src}", |
| 2349 | [(set R32:$dst, (zextloadi32i8 addr:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2350 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2351 | "movz{wl|x} {$src, $dst|$dst, $src}", |
| 2352 | [(set R32:$dst, (zext R16:$src))]>, TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2353 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2354 | "movz{wl|x} {$src, $dst|$dst, $src}", |
| 2355 | [(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB; |
| 2356 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2357 | //===----------------------------------------------------------------------===// |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2358 | // XMM Floating point support (requires SSE / SSE2) |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2359 | //===----------------------------------------------------------------------===// |
| 2360 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2361 | def MOVSSrr : I<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2362 | "movss {$src, $dst|$dst, $src}", []>, |
| 2363 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2364 | def MOVSDrr : I<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2365 | "movsd {$src, $dst|$dst, $src}", []>, |
| 2366 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2367 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2368 | def MOVSSrm : I<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src), |
| 2369 | "movss {$src, $dst|$dst, $src}", |
| 2370 | [(set FR32:$dst, (loadf32 addr:$src))]>, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2371 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2372 | def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src), |
| 2373 | "movss {$src, $dst|$dst, $src}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2374 | [(store FR32:$src, addr:$dst)]>, |
| 2375 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2376 | def MOVSDrm : I<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src), |
| 2377 | "movsd {$src, $dst|$dst, $src}", |
| 2378 | [(set FR64:$dst, (loadf64 addr:$src))]>, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2379 | Requires<[HasSSE2]>, XD; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2380 | def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src), |
| 2381 | "movsd {$src, $dst|$dst, $src}", |
| 2382 | [(store FR64:$src, addr:$dst)]>, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2383 | Requires<[HasSSE2]>, XD; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2384 | |
| 2385 | def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2386 | "cvttsd2si {$src, $dst|$dst, $src}", |
| 2387 | [(set R32:$dst, (fp_to_sint FR64:$src))]>, |
| 2388 | Requires<[HasSSE2]>, XD; |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 2389 | def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2390 | "cvttsd2si {$src, $dst|$dst, $src}", |
| 2391 | [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>, |
| 2392 | Requires<[HasSSE2]>, XD; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2393 | def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2394 | "cvttss2si {$src, $dst|$dst, $src}", |
| 2395 | [(set R32:$dst, (fp_to_sint FR32:$src))]>, |
| 2396 | Requires<[HasSSE1]>, XS; |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 2397 | def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2398 | "cvttss2si {$src, $dst|$dst, $src}", |
| 2399 | [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>, |
| 2400 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2401 | def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2402 | "cvtsd2ss {$src, $dst|$dst, $src}", |
| 2403 | [(set FR32:$dst, (fround FR64:$src))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2404 | Requires<[HasSSE2]>, XS; |
| 2405 | def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2406 | "cvtsd2ss {$src, $dst|$dst, $src}", |
| 2407 | [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2408 | Requires<[HasSSE2]>, XS; |
| 2409 | def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2410 | "cvtss2sd {$src, $dst|$dst, $src}", |
| 2411 | [(set FR64:$dst, (fextend FR32:$src))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2412 | Requires<[HasSSE2]>, XD; |
| 2413 | def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2414 | "cvtss2sd {$src, $dst|$dst, $src}", |
| 2415 | [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2416 | Requires<[HasSSE2]>, XD; |
| 2417 | def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2418 | "cvtsi2ss {$src, $dst|$dst, $src}", |
| 2419 | [(set FR32:$dst, (sint_to_fp R32:$src))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2420 | Requires<[HasSSE2]>, XS; |
| 2421 | def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2422 | "cvtsi2ss {$src, $dst|$dst, $src}", |
| 2423 | [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2424 | Requires<[HasSSE2]>, XS; |
| 2425 | def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2426 | "cvtsi2sd {$src, $dst|$dst, $src}", |
| 2427 | [(set FR64:$dst, (sint_to_fp R32:$src))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2428 | Requires<[HasSSE2]>, XD; |
| 2429 | def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2430 | "cvtsi2sd {$src, $dst|$dst, $src}", |
| 2431 | [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2432 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 2433 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2434 | def SQRTSSrm : I<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2435 | "sqrtss {$src, $dst|$dst, $src}", |
| 2436 | [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>, |
| 2437 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2438 | def SQRTSSrr : I<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2439 | "sqrtss {$src, $dst|$dst, $src}", |
| 2440 | [(set FR32:$dst, (fsqrt FR32:$src))]>, |
| 2441 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2442 | def SQRTSDrm : I<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2443 | "sqrtsd {$src, $dst|$dst, $src}", |
| 2444 | [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>, |
| 2445 | Requires<[HasSSE2]>, XD; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2446 | def SQRTSDrr : I<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2447 | "sqrtsd {$src, $dst|$dst, $src}", |
| 2448 | [(set FR64:$dst, (fsqrt FR64:$src))]>, |
| 2449 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2450 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2451 | def UCOMISDrr: I<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2), |
| 2452 | "ucomisd {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2453 | [(X86cmp FR64:$src1, FR64:$src2)]>, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2454 | Requires<[HasSSE2]>, TB, OpSize; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2455 | def UCOMISDrm: I<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2), |
| 2456 | "ucomisd {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2457 | [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>, |
| 2458 | Requires<[HasSSE2]>, TB, OpSize; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2459 | def UCOMISSrr: I<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2), |
| 2460 | "ucomiss {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2461 | [(X86cmp FR32:$src1, FR32:$src2)]>, |
| 2462 | Requires<[HasSSE1]>, TB; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2463 | def UCOMISSrm: I<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2), |
| 2464 | "ucomiss {$src2, $src1|$src1, $src2}", |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2465 | [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>, |
| 2466 | Requires<[HasSSE1]>, TB; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2467 | |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2468 | // Pseudo-instructions that map fld0 to xorps/xorpd for sse. |
Nate Begeman | 1c73c7b | 2005-08-03 23:26:28 +0000 | [diff] [blame] | 2469 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok. |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2470 | def FLD0SS : I<0x57, MRMSrcReg, (ops FR32:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2471 | "xorps $dst, $dst", [(set FR32:$dst, fp32imm0)]>, |
Evan Cheng | 650d688 | 2006-01-05 02:08:37 +0000 | [diff] [blame] | 2472 | Requires<[HasSSE1]>, TB; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2473 | def FLD0SD : I<0x57, MRMSrcReg, (ops FR64:$dst), |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2474 | "xorpd $dst, $dst", [(set FR64:$dst, fp64imm0)]>, |
Evan Cheng | 650d688 | 2006-01-05 02:08:37 +0000 | [diff] [blame] | 2475 | Requires<[HasSSE2]>, TB, OpSize; |
Nate Begeman | 1c73c7b | 2005-08-03 23:26:28 +0000 | [diff] [blame] | 2476 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2477 | let isTwoAddress = 1 in { |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2478 | // SSE Scalar Arithmetic |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2479 | let isCommutable = 1 in { |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2480 | def ADDSSrr : I<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2481 | "addss {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2482 | [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>, |
| 2483 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2484 | def ADDSDrr : I<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2485 | "addsd {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2486 | [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>, |
| 2487 | Requires<[HasSSE2]>, XD; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2488 | def MULSSrr : I<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2489 | "mulss {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2490 | [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>, |
| 2491 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2492 | def MULSDrr : I<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2493 | "mulsd {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2494 | [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>, |
| 2495 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2496 | } |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2497 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2498 | def ADDSSrm : I<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), |
| 2499 | "addss {$src2, $dst|$dst, $src2}", |
| 2500 | [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>, |
| 2501 | Requires<[HasSSE1]>, XS; |
| 2502 | def ADDSDrm : I<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2), |
| 2503 | "addsd {$src2, $dst|$dst, $src2}", |
| 2504 | [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>, |
| 2505 | Requires<[HasSSE2]>, XD; |
| 2506 | def MULSSrm : I<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), |
| 2507 | "mulss {$src2, $dst|$dst, $src2}", |
| 2508 | [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>, |
| 2509 | Requires<[HasSSE1]>, XS; |
| 2510 | def MULSDrm : I<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2), |
| 2511 | "mulsd {$src2, $dst|$dst, $src2}", |
| 2512 | [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>, |
| 2513 | Requires<[HasSSE2]>, XD; |
| 2514 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2515 | def DIVSSrr : I<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2516 | "divss {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2517 | [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>, |
| 2518 | Requires<[HasSSE1]>, XS; |
| 2519 | def DIVSSrm : I<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), |
| 2520 | "divss {$src2, $dst|$dst, $src2}", |
| 2521 | [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>, |
| 2522 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2523 | def DIVSDrr : I<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2524 | "divsd {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2525 | [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>, |
| 2526 | Requires<[HasSSE2]>, XD; |
| 2527 | def DIVSDrm : I<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2), |
| 2528 | "divsd {$src2, $dst|$dst, $src2}", |
| 2529 | [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>, |
| 2530 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2531 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2532 | def SUBSSrr : I<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2533 | "subss {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2534 | [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>, |
| 2535 | Requires<[HasSSE1]>, XS; |
| 2536 | def SUBSSrm : I<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), |
| 2537 | "subss {$src2, $dst|$dst, $src2}", |
| 2538 | [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>, |
| 2539 | Requires<[HasSSE1]>, XS; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2540 | def SUBSDrr : I<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2541 | "subsd {$src2, $dst|$dst, $src2}", |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2542 | [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>, |
| 2543 | Requires<[HasSSE2]>, XD; |
| 2544 | def SUBSDrm : I<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2), |
| 2545 | "subsd {$src2, $dst|$dst, $src2}", |
| 2546 | [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>, |
| 2547 | Requires<[HasSSE2]>, XD; |
| 2548 | |
| 2549 | // SSE Logical |
| 2550 | let isCommutable = 1 in { |
| 2551 | def ANDPSrr : I<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
| 2552 | "andps {$src2, $dst|$dst, $src2}", []>, |
| 2553 | Requires<[HasSSE1]>, TB; |
| 2554 | def ANDPDrr : I<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
| 2555 | "andpd {$src2, $dst|$dst, $src2}", []>, |
| 2556 | Requires<[HasSSE2]>, TB, OpSize; |
| 2557 | def ORPSrr : I<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
| 2558 | "orps {$src2, $dst|$dst, $src2}", []>, |
| 2559 | Requires<[HasSSE1]>, TB; |
| 2560 | def ORPDrr : I<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
| 2561 | "orpd {$src2, $dst|$dst, $src2}", []>, |
| 2562 | Requires<[HasSSE2]>, TB, OpSize; |
| 2563 | def XORPSrr : I<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
| 2564 | "xorps {$src2, $dst|$dst, $src2}", []>, |
| 2565 | Requires<[HasSSE1]>, TB; |
| 2566 | def XORPDrr : I<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
| 2567 | "xorpd {$src2, $dst|$dst, $src2}", []>, |
| 2568 | Requires<[HasSSE2]>, TB, OpSize; |
| 2569 | } |
| 2570 | def ANDNPSrr : I<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), |
| 2571 | "andnps {$src2, $dst|$dst, $src2}", []>, |
| 2572 | Requires<[HasSSE1]>, TB; |
| 2573 | def ANDNPDrr : I<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2), |
| 2574 | "andnpd {$src2, $dst|$dst, $src2}", []>, |
| 2575 | Requires<[HasSSE2]>, TB, OpSize; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2576 | |
| 2577 | def CMPSSrr : I<0xC2, MRMSrcReg, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2578 | (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2579 | "cmp${cc}ss {$src, $dst|$dst, $src}", []>, |
| 2580 | Requires<[HasSSE1]>, XS; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2581 | def CMPSSrm : I<0xC2, MRMSrcMem, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2582 | (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2583 | "cmp${cc}ss {$src, $dst|$dst, $src}", []>, |
| 2584 | Requires<[HasSSE1]>, XS; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2585 | def CMPSDrr : I<0xC2, MRMSrcReg, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2586 | (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2587 | "cmp${cc}sd {$src, $dst|$dst, $src}", []>, |
| 2588 | Requires<[HasSSE1]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2589 | def CMPSDrm : I<0xC2, MRMSrcMem, |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 2590 | (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2591 | "cmp${cc}sd {$src, $dst|$dst, $src}", []>, |
| 2592 | Requires<[HasSSE2]>, XD; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 2593 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2594 | |
| 2595 | //===----------------------------------------------------------------------===// |
Chris Lattner | c515ad1 | 2005-12-21 07:50:26 +0000 | [diff] [blame] | 2596 | // Floating Point Stack Support |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2597 | //===----------------------------------------------------------------------===// |
| 2598 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2599 | // Floating point support. All FP Stack operations are represented with two |
| 2600 | // instructions here. The first instruction, generated by the instruction |
| 2601 | // selector, uses "RFP" registers: a traditional register file to reference |
| 2602 | // floating point values. These instructions are all psuedo instructions and |
| 2603 | // use the "Fp" prefix. The second instruction is defined with FPI, which is |
| 2604 | // the actual instruction emitted by the assembler. The FP stackifier pass |
| 2605 | // converts one to the other after register allocation occurs. |
| 2606 | // |
| 2607 | // Note that the FpI instruction should have instruction selection info (e.g. |
| 2608 | // a pattern) and the FPI instruction should have emission info (e.g. opcode |
| 2609 | // encoding and asm printing info). |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2610 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2611 | // FPI - Floating Point Instruction template. |
| 2612 | class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {} |
| 2613 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2614 | // FpI_ - Floating Point Psuedo Instruction template. Not Predicated. |
| 2615 | class FpI_<dag ops, FPFormat fp, list<dag> pattern> |
| 2616 | : X86Inst<0, Pseudo, NoImm, ops, ""> { |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2617 | let FPForm = fp; let FPFormBits = FPForm.Value; |
| 2618 | let Pattern = pattern; |
| 2619 | } |
| 2620 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2621 | // Random Pseudo Instructions. |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2622 | def FpGETRESULT : FpI_<(ops RFP:$dst), SpecialFP, |
| 2623 | [(set RFP:$dst, X86fpget)]>; // FPR = ST(0) |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 2624 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2625 | let noResults = 1 in |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2626 | def FpSETRESULT : FpI_<(ops RFP:$src), SpecialFP, |
| 2627 | [(X86fpset RFP:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 2628 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2629 | // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack. |
| 2630 | class FpI<dag ops, FPFormat fp, list<dag> pattern> : |
| 2631 | FpI_<ops, fp, pattern>, Requires<[FPStack]>; |
| 2632 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2633 | |
Evan Cheng | 171049d | 2005-12-23 22:14:32 +0000 | [diff] [blame] | 2634 | def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2 |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2635 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2636 | // Arithmetic |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2637 | // Add, Sub, Mul, Div. |
| 2638 | def FpADD : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, |
| 2639 | [(set RFP:$dst, (fadd RFP:$src1, RFP:$src2))]>; |
| 2640 | def FpSUB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, |
| 2641 | [(set RFP:$dst, (fsub RFP:$src1, RFP:$src2))]>; |
| 2642 | def FpMUL : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, |
| 2643 | [(set RFP:$dst, (fmul RFP:$src1, RFP:$src2))]>; |
| 2644 | def FpDIV : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, |
| 2645 | [(set RFP:$dst, (fdiv RFP:$src1, RFP:$src2))]>; |
| 2646 | |
| 2647 | class FPST0rInst<bits<8> o, string asm> |
| 2648 | : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8; |
| 2649 | class FPrST0Inst<bits<8> o, string asm> |
| 2650 | : FPI<o, AddRegFrm, (ops RST:$op), asm>, DC; |
| 2651 | class FPrST0PInst<bits<8> o, string asm> |
| 2652 | : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE; |
| 2653 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2654 | // Binary Ops with a memory source. |
| 2655 | def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2656 | [(set RFP:$dst, (fadd RFP:$src1, |
| 2657 | (extloadf64f32 addr:$src2)))]>; |
| 2658 | // ST(0) = ST(0) + [mem32] |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2659 | def FpADD64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2660 | [(set RFP:$dst, (fadd RFP:$src1, (loadf64 addr:$src2)))]>; |
| 2661 | // ST(0) = ST(0) + [mem64] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2662 | def FpMUL32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2663 | [(set RFP:$dst, (fmul RFP:$src1, |
| 2664 | (extloadf64f32 addr:$src2)))]>; |
| 2665 | // ST(0) = ST(0) * [mem32] |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2666 | def FpMUL64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2667 | [(set RFP:$dst, (fmul RFP:$src1, (loadf64 addr:$src2)))]>; |
| 2668 | // ST(0) = ST(0) * [mem64] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2669 | def FpSUB32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2670 | [(set RFP:$dst, (fsub RFP:$src1, |
| 2671 | (extloadf64f32 addr:$src2)))]>; |
| 2672 | // ST(0) = ST(0) - [mem32] |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2673 | def FpSUB64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2674 | [(set RFP:$dst, (fsub RFP:$src1, (loadf64 addr:$src2)))]>; |
| 2675 | // ST(0) = ST(0) - [mem64] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2676 | def FpSUBR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 2677 | [(set RFP:$dst, (fsub (extloadf64f32 addr:$src2), |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2678 | RFP:$src1))]>; |
| 2679 | // ST(0) = [mem32] - ST(0) |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2680 | def FpSUBR64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2681 | [(set RFP:$dst, (fsub (loadf64 addr:$src2), RFP:$src1))]>; |
| 2682 | // ST(0) = [mem64] - ST(0) |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2683 | def FpDIV32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2684 | [(set RFP:$dst, (fdiv RFP:$src1, |
| 2685 | (extloadf64f32 addr:$src2)))]>; |
| 2686 | // ST(0) = ST(0) / [mem32] |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2687 | def FpDIV64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2688 | [(set RFP:$dst, (fdiv RFP:$src1, (loadf64 addr:$src2)))]>; |
| 2689 | // ST(0) = ST(0) / [mem64] |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2690 | def FpDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2691 | [(set RFP:$dst, (fdiv (extloadf64f32 addr:$src2), |
| 2692 | RFP:$src1))]>; |
| 2693 | // ST(0) = [mem32] / ST(0) |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2694 | def FpDIVR64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2695 | [(set RFP:$dst, (fdiv (loadf64 addr:$src2), RFP:$src1))]>; |
| 2696 | // ST(0) = [mem64] / ST(0) |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2697 | |
| 2698 | |
| 2699 | def FADD32m : FPI<0xD8, MRM0m, (ops f32mem:$src), "fadd{s} $src">; |
| 2700 | def FADD64m : FPI<0xDC, MRM0m, (ops f64mem:$src), "fadd{l} $src">; |
| 2701 | def FMUL32m : FPI<0xD8, MRM1m, (ops f32mem:$src), "fmul{s} $src">; |
| 2702 | def FMUL64m : FPI<0xDC, MRM1m, (ops f64mem:$src), "fmul{l} $src">; |
| 2703 | def FSUB32m : FPI<0xD8, MRM4m, (ops f32mem:$src), "fsub{s} $src">; |
| 2704 | def FSUB64m : FPI<0xDC, MRM4m, (ops f64mem:$src), "fsub{l} $src">; |
| 2705 | def FSUBR32m : FPI<0xD8, MRM5m, (ops f32mem:$src), "fsubr{s} $src">; |
| 2706 | def FSUBR64m : FPI<0xDC, MRM5m, (ops f64mem:$src), "fsubr{l} $src">; |
| 2707 | def FDIV32m : FPI<0xD8, MRM6m, (ops f32mem:$src), "fdiv{s} $src">; |
| 2708 | def FDIV64m : FPI<0xDC, MRM6m, (ops f64mem:$src), "fdiv{l} $src">; |
| 2709 | def FDIVR32m : FPI<0xD8, MRM7m, (ops f32mem:$src), "fdivr{s} $src">; |
| 2710 | def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">; |
| 2711 | |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2712 | def FpIADD16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, |
| 2713 | [(set RFP:$dst, (fadd RFP:$src1, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2714 | (X86fild addr:$src2, i16)))]>; |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2715 | // ST(0) = ST(0) + [mem16int] |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2716 | def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2717 | [(set RFP:$dst, (fadd RFP:$src1, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2718 | (X86fild addr:$src2, i32)))]>; |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2719 | // ST(0) = ST(0) + [mem32int] |
| 2720 | def FpIMUL16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, |
| 2721 | [(set RFP:$dst, (fmul RFP:$src1, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2722 | (X86fild addr:$src2, i16)))]>; |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2723 | // ST(0) = ST(0) * [mem16int] |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2724 | def FpIMUL32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2725 | [(set RFP:$dst, (fmul RFP:$src1, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2726 | (X86fild addr:$src2, i32)))]>; |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2727 | // ST(0) = ST(0) * [mem32int] |
| 2728 | def FpISUB16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, |
| 2729 | [(set RFP:$dst, (fsub RFP:$src1, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2730 | (X86fild addr:$src2, i16)))]>; |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2731 | // ST(0) = ST(0) - [mem16int] |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2732 | def FpISUB32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2733 | [(set RFP:$dst, (fsub RFP:$src1, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2734 | (X86fild addr:$src2, i32)))]>; |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2735 | // ST(0) = ST(0) - [mem32int] |
| 2736 | def FpISUBR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2737 | [(set RFP:$dst, (fsub (X86fild addr:$src2, i16), |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2738 | RFP:$src1))]>; |
| 2739 | // ST(0) = [mem16int] - ST(0) |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2740 | def FpISUBR32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2741 | [(set RFP:$dst, (fsub (X86fild addr:$src2, i32), |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2742 | RFP:$src1))]>; |
| 2743 | // ST(0) = [mem32int] - ST(0) |
| 2744 | def FpIDIV16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, |
| 2745 | [(set RFP:$dst, (fdiv RFP:$src1, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2746 | (X86fild addr:$src2, i16)))]>; |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2747 | // ST(0) = ST(0) / [mem16int] |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2748 | def FpIDIV32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2749 | [(set RFP:$dst, (fdiv RFP:$src1, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2750 | (X86fild addr:$src2, i32)))]>; |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2751 | // ST(0) = ST(0) / [mem32int] |
| 2752 | def FpIDIVR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2753 | [(set RFP:$dst, (fdiv (X86fild addr:$src2, i16), |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2754 | RFP:$src1))]>; |
| 2755 | // ST(0) = [mem16int] / ST(0) |
Evan Cheng | 8a3f4c7 | 2006-01-16 22:48:46 +0000 | [diff] [blame] | 2756 | def FpIDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2757 | [(set RFP:$dst, (fdiv (X86fild addr:$src2, i32), |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2758 | RFP:$src1))]>; |
| 2759 | // ST(0) = [mem32int] / ST(0) |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2760 | |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2761 | def FIADD16m : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">; |
| 2762 | def FIADD32m : FPI<0xDA, MRM0m, (ops i32mem:$src), "fiadd{l} $src">; |
| 2763 | def FIMUL16m : FPI<0xDE, MRM1m, (ops i16mem:$src), "fimul{s} $src">; |
| 2764 | def FIMUL32m : FPI<0xDA, MRM1m, (ops i32mem:$src), "fimul{l} $src">; |
| 2765 | def FISUB16m : FPI<0xDE, MRM4m, (ops i16mem:$src), "fisub{s} $src">; |
| 2766 | def FISUB32m : FPI<0xDA, MRM4m, (ops i32mem:$src), "fisub{l} $src">; |
| 2767 | def FISUBR16m : FPI<0xDE, MRM5m, (ops i16mem:$src), "fisubr{s} $src">; |
| 2768 | def FISUBR32m : FPI<0xDA, MRM5m, (ops i32mem:$src), "fisubr{l} $src">; |
| 2769 | def FIDIV16m : FPI<0xDE, MRM6m, (ops i16mem:$src), "fidiv{s} $src">; |
Evan Cheng | b5d0b0b | 2006-01-16 23:26:53 +0000 | [diff] [blame] | 2770 | def FIDIV32m : FPI<0xDA, MRM6m, (ops i32mem:$src), "fidiv{l} $src">; |
Evan Cheng | f710062 | 2006-01-10 22:22:02 +0000 | [diff] [blame] | 2771 | def FIDIVR16m : FPI<0xDE, MRM7m, (ops i16mem:$src), "fidivr{s} $src">; |
Evan Cheng | b5d0b0b | 2006-01-16 23:26:53 +0000 | [diff] [blame] | 2772 | def FIDIVR32m : FPI<0xDA, MRM7m, (ops i32mem:$src), "fidivr{l} $src">; |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2773 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2774 | // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion |
| 2775 | // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, |
| 2776 | // we have to put some 'r's in and take them out of weird places. |
| 2777 | def FADDST0r : FPST0rInst <0xC0, "fadd $op">; |
| 2778 | def FADDrST0 : FPrST0Inst <0xC0, "fadd {%ST(0), $op|$op, %ST(0)}">; |
| 2779 | def FADDPrST0 : FPrST0PInst<0xC0, "faddp $op">; |
| 2780 | def FSUBRST0r : FPST0rInst <0xE8, "fsubr $op">; |
| 2781 | def FSUBrST0 : FPrST0Inst <0xE8, "fsub{r} {%ST(0), $op|$op, %ST(0)}">; |
| 2782 | def FSUBPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">; |
| 2783 | def FSUBST0r : FPST0rInst <0xE0, "fsub $op">; |
| 2784 | def FSUBRrST0 : FPrST0Inst <0xE0, "fsub{|r} {%ST(0), $op|$op, %ST(0)}">; |
| 2785 | def FSUBRPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">; |
| 2786 | def FMULST0r : FPST0rInst <0xC8, "fmul $op">; |
| 2787 | def FMULrST0 : FPrST0Inst <0xC8, "fmul {%ST(0), $op|$op, %ST(0)}">; |
| 2788 | def FMULPrST0 : FPrST0PInst<0xC8, "fmulp $op">; |
| 2789 | def FDIVRST0r : FPST0rInst <0xF8, "fdivr $op">; |
| 2790 | def FDIVrST0 : FPrST0Inst <0xF8, "fdiv{r} {%ST(0), $op|$op, %ST(0)}">; |
| 2791 | def FDIVPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">; |
| 2792 | def FDIVST0r : FPST0rInst <0xF0, "fdiv $op">; |
| 2793 | def FDIVRrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">; |
| 2794 | def FDIVRPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">; |
| 2795 | |
| 2796 | |
| 2797 | // Unary operations. |
| 2798 | def FpCHS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, |
| 2799 | [(set RFP:$dst, (fneg RFP:$src))]>; |
| 2800 | def FpABS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, |
| 2801 | [(set RFP:$dst, (fabs RFP:$src))]>; |
| 2802 | def FpSQRT : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, |
| 2803 | [(set RFP:$dst, (fsqrt RFP:$src))]>; |
| 2804 | def FpSIN : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, |
| 2805 | [(set RFP:$dst, (fsin RFP:$src))]>; |
| 2806 | def FpCOS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, |
| 2807 | [(set RFP:$dst, (fcos RFP:$src))]>; |
| 2808 | def FpTST : FpI<(ops RFP:$src), OneArgFP, |
| 2809 | []>; |
| 2810 | |
| 2811 | def FCHS : FPI<0xE0, RawFrm, (ops), "fchs">, D9; |
| 2812 | def FABS : FPI<0xE1, RawFrm, (ops), "fabs">, D9; |
| 2813 | def FSQRT : FPI<0xFA, RawFrm, (ops), "fsqrt">, D9; |
| 2814 | def FSIN : FPI<0xFE, RawFrm, (ops), "fsin">, D9; |
| 2815 | def FCOS : FPI<0xFF, RawFrm, (ops), "fcos">, D9; |
| 2816 | def FTST : FPI<0xE4, RawFrm, (ops), "ftst">, D9; |
| 2817 | |
| 2818 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2819 | // Floating point cmovs. |
| 2820 | let isTwoAddress = 1 in { |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 2821 | def FpCMOVB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, |
| 2822 | [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2823 | X86_COND_B))]>; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 2824 | def FpCMOVBE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, |
| 2825 | [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2826 | X86_COND_BE))]>; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 2827 | def FpCMOVE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, |
| 2828 | [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2829 | X86_COND_E))]>; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 2830 | def FpCMOVP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, |
| 2831 | [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2832 | X86_COND_P))]>; |
Evan Cheng | 86556a5 | 2006-01-21 02:55:41 +0000 | [diff] [blame] | 2833 | def FpCMOVNB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 2834 | [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2835 | X86_COND_AE))]>; |
Evan Cheng | 86556a5 | 2006-01-21 02:55:41 +0000 | [diff] [blame] | 2836 | def FpCMOVNBE: FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 2837 | [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2838 | X86_COND_A))]>; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 2839 | def FpCMOVNE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, |
| 2840 | [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2841 | X86_COND_NE))]>; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 2842 | def FpCMOVNP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, |
| 2843 | [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2844 | X86_COND_NP))]>; |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2845 | } |
| 2846 | |
| 2847 | def FCMOVB : FPI<0xC0, AddRegFrm, (ops RST:$op), |
| 2848 | "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA; |
| 2849 | def FCMOVBE : FPI<0xD0, AddRegFrm, (ops RST:$op), |
| 2850 | "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA; |
| 2851 | def FCMOVE : FPI<0xC8, AddRegFrm, (ops RST:$op), |
| 2852 | "fcmove {$op, %ST(0)|%ST(0), $op}">, DA; |
| 2853 | def FCMOVP : FPI<0xD8, AddRegFrm, (ops RST:$op), |
| 2854 | "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA; |
Evan Cheng | 86556a5 | 2006-01-21 02:55:41 +0000 | [diff] [blame] | 2855 | def FCMOVNB : FPI<0xC0, AddRegFrm, (ops RST:$op), |
| 2856 | "fcmovnb {$op, %ST(0)|%ST(0), $op}">, DB; |
| 2857 | def FCMOVNBE : FPI<0xD0, AddRegFrm, (ops RST:$op), |
| 2858 | "fcmovnbe {$op, %ST(0)|%ST(0), $op}">, DB; |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2859 | def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op), |
| 2860 | "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB; |
| 2861 | def FCMOVNP : FPI<0xD8, AddRegFrm, (ops RST:$op), |
| 2862 | "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB; |
| 2863 | |
| 2864 | // Floating point loads & stores. |
| 2865 | def FpLD32m : FpI<(ops RFP:$dst, f32mem:$src), ZeroArgFP, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2866 | [(set RFP:$dst, (extloadf64f32 addr:$src))]>; |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2867 | def FpLD64m : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP, |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2868 | [(set RFP:$dst, (loadf64 addr:$src))]>; |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2869 | def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2870 | [(set RFP:$dst, (X86fild addr:$src, i16))]>; |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2871 | def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2872 | [(set RFP:$dst, (X86fild addr:$src, i32))]>; |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2873 | def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP, |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 2874 | [(set RFP:$dst, (X86fild addr:$src, i64))]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 2875 | |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2876 | def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, |
| 2877 | [(truncstore RFP:$src, addr:$op, f32)]>; |
| 2878 | def FpST64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, |
| 2879 | [(store RFP:$src, addr:$op)]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 2880 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2881 | def FpSTP32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, []>; |
| 2882 | def FpSTP64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, []>; |
| 2883 | def FpIST16m : FpI<(ops i16mem:$op, RFP:$src), OneArgFP, []>; |
| 2884 | def FpIST32m : FpI<(ops i32mem:$op, RFP:$src), OneArgFP, []>; |
| 2885 | def FpIST64m : FpI<(ops i64mem:$op, RFP:$src), OneArgFP, []>; |
Alkis Evlogimenos | 978f629 | 2004-09-08 16:54:54 +0000 | [diff] [blame] | 2886 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2887 | def FLD32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">; |
| 2888 | def FLD64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">; |
| 2889 | def FILD16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">; |
| 2890 | def FILD32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">; |
| 2891 | def FILD64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">; |
| 2892 | def FST32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">; |
| 2893 | def FST64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">; |
| 2894 | def FSTP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">; |
| 2895 | def FSTP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">; |
| 2896 | def FIST16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">; |
| 2897 | def FIST32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">; |
| 2898 | def FISTP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">; |
| 2899 | def FISTP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">; |
| 2900 | def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2901 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2902 | // FP Stack manipulation instructions. |
| 2903 | def FLDrr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9; |
| 2904 | def FSTrr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD; |
| 2905 | def FSTPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD; |
| 2906 | def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 2907 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2908 | // Floating point constant loads. |
Evan Cheng | 650d688 | 2006-01-05 02:08:37 +0000 | [diff] [blame] | 2909 | def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP, |
| 2910 | [(set RFP:$dst, fp64imm0)]>; |
| 2911 | def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP, |
| 2912 | [(set RFP:$dst, fp64imm1)]>; |
| 2913 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2914 | def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9; |
| 2915 | def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9; |
Chris Lattner | 490e86f | 2004-04-11 20:24:15 +0000 | [diff] [blame] | 2916 | |
Chris Lattner | 1c54a85 | 2004-03-31 22:02:13 +0000 | [diff] [blame] | 2917 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2918 | // Floating point compares. |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2919 | def FpUCOMr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP, |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2920 | []>; // FPSW = cmp ST(0) with ST(i) |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2921 | def FpUCOMIr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 2922 | [(X86cmp RFP:$lhs, RFP:$rhs)]>; // CC = cmp ST(0) with ST(i) |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2923 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2924 | def FUCOMr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) |
| 2925 | (ops RST:$reg), |
| 2926 | "fucom $reg">, DD, Imp<[ST0],[]>; |
| 2927 | def FUCOMPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop |
| 2928 | (ops RST:$reg), |
| 2929 | "fucomp $reg">, DD, Imp<[ST0],[]>; |
| 2930 | def FUCOMPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop |
| 2931 | (ops), |
| 2932 | "fucompp">, DA, Imp<[ST0],[]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2933 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2934 | def FUCOMIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) |
| 2935 | (ops RST:$reg), |
| 2936 | "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; |
| 2937 | def FUCOMIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop |
| 2938 | (ops RST:$reg), |
| 2939 | "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 2940 | |
Chris Lattner | a1b5e16 | 2004-04-12 01:38:55 +0000 | [diff] [blame] | 2941 | |
Chris Lattner | 58fe459 | 2005-12-21 07:47:04 +0000 | [diff] [blame] | 2942 | // Floating point flag ops. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2943 | def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2944 | (ops), "fnstsw", []>, DF, Imp<[],[AX]>; |
Chris Lattner | 96563df | 2004-08-01 06:01:00 +0000 | [diff] [blame] | 2945 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2946 | def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2947 | (ops i16mem:$dst), "fnstcw $dst", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2948 | def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] |
Evan Cheng | f070184 | 2005-11-29 19:38:52 +0000 | [diff] [blame] | 2949 | (ops i16mem:$dst), "fldcw $dst", []>; |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 2950 | |
| 2951 | |
| 2952 | //===----------------------------------------------------------------------===// |
| 2953 | // Miscellaneous Instructions |
| 2954 | //===----------------------------------------------------------------------===// |
| 2955 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2956 | def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>, |
| 2957 | TB, Imp<[],[EAX,EDX]>; |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 2958 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2959 | |
| 2960 | //===----------------------------------------------------------------------===// |
| 2961 | // Non-Instruction Patterns |
| 2962 | //===----------------------------------------------------------------------===// |
| 2963 | |
Evan Cheng | 002fe9b | 2006-01-12 07:56:47 +0000 | [diff] [blame] | 2964 | // GlobalAddress and ExternalSymbol |
Evan Cheng | 77e9043 | 2006-01-12 19:36:31 +0000 | [diff] [blame] | 2965 | def : Pat<(i32 globaladdr:$dst), (MOV32ri tglobaladdr:$dst)>; |
| 2966 | def : Pat<(i32 externalsym:$dst), (MOV32ri texternalsym:$dst)>; |
Evan Cheng | 002fe9b | 2006-01-12 07:56:47 +0000 | [diff] [blame] | 2967 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2968 | // Calls |
| 2969 | def : Pat<(X86call tglobaladdr:$dst), |
| 2970 | (CALLpcrel32 tglobaladdr:$dst)>; |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 2971 | def : Pat<(X86call texternalsym:$dst), |
| 2972 | (CALLpcrel32 texternalsym:$dst)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2973 | |
| 2974 | // X86 specific add which produces a flag. |
| 2975 | def : Pat<(X86addflag R32:$src1, R32:$src2), |
| 2976 | (ADD32rr R32:$src1, R32:$src2)>; |
| 2977 | def : Pat<(X86addflag R32:$src1, (load addr:$src2)), |
| 2978 | (ADD32rm R32:$src1, addr:$src2)>; |
| 2979 | def : Pat<(X86addflag R32:$src1, imm:$src2), |
| 2980 | (ADD32ri R32:$src1, imm:$src2)>; |
| 2981 | def : Pat<(X86addflag R32:$src1, i32immSExt8:$src2), |
| 2982 | (ADD32ri8 R32:$src1, i32immSExt8:$src2)>; |
| 2983 | |
| 2984 | def : Pat<(X86subflag R32:$src1, R32:$src2), |
| 2985 | (SUB32rr R32:$src1, R32:$src2)>; |
| 2986 | def : Pat<(X86subflag R32:$src1, (load addr:$src2)), |
| 2987 | (SUB32rm R32:$src1, addr:$src2)>; |
| 2988 | def : Pat<(X86subflag R32:$src1, imm:$src2), |
| 2989 | (SUB32ri R32:$src1, imm:$src2)>; |
| 2990 | def : Pat<(X86subflag R32:$src1, i32immSExt8:$src2), |
| 2991 | (SUB32ri8 R32:$src1, i32immSExt8:$src2)>; |
| 2992 | |
Evan Cheng | b841433 | 2006-01-13 21:45:19 +0000 | [diff] [blame] | 2993 | def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1), |
| 2994 | (MOV8mi addr:$dst, imm:$src)>; |
| 2995 | def : Pat<(truncstore R8:$src, addr:$dst, i1), |
| 2996 | (MOV8mr addr:$dst, R8:$src)>; |
| 2997 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2998 | // {s|z}extload bool -> {s|z}extload byte |
| 2999 | def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>; |
| 3000 | def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>; |
Evan Cheng | e5d9343 | 2006-01-17 07:02:46 +0000 | [diff] [blame] | 3001 | def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3002 | def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 3003 | def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 3004 | |
| 3005 | // extload bool -> extload byte |
| 3006 | def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
| 3007 | |
| 3008 | // anyext -> zext |
| 3009 | def : Pat<(i16 (anyext R8 :$src)), (MOVZX16rr8 R8 :$src)>; |
| 3010 | def : Pat<(i32 (anyext R8 :$src)), (MOVZX32rr8 R8 :$src)>; |
| 3011 | def : Pat<(i32 (anyext R16:$src)), (MOVZX32rr16 R16:$src)>; |
| 3012 | |
| 3013 | // Required for RET of f32 / f64 values. |
| 3014 | def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>; |
| 3015 | def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>; |
| 3016 | |
| 3017 | // Required for CALL which return f32 / f64 values. |
| 3018 | def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>; |
| 3019 | def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>; |
| 3020 | |
| 3021 | // Floatin point constant -0.0 and -1.0 |
| 3022 | def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>; |
| 3023 | def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>; |
| 3024 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3025 | // RFP undef |
| 3026 | def : Pat<(f64 (undef)), (FpLD0)>, Requires<[FPStack]>; |
| 3027 | |
| 3028 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 3029 | //===----------------------------------------------------------------------===// |
| 3030 | // Some peepholes |
| 3031 | //===----------------------------------------------------------------------===// |
| 3032 | |
| 3033 | // (shl x, 1) ==> (add x, x) |
| 3034 | def : Pat<(shl R8 :$src1, (i8 1)), (ADD8rr R8 :$src1, R8 :$src1)>; |
| 3035 | def : Pat<(shl R16:$src1, (i8 1)), (ADD16rr R16:$src1, R16:$src1)>; |
| 3036 | def : Pat<(shl R32:$src1, (i8 1)), (ADD32rr R32:$src1, R32:$src1)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 3037 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3038 | // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c) |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 3039 | def : Pat<(or (srl R32:$src1, CL:$amt), |
| 3040 | (shl R32:$src2, (sub 32, CL:$amt))), |
| 3041 | (SHRD32rrCL R32:$src1, R32:$src2)>; |
| 3042 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3043 | def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt), |
| 3044 | (shl R32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 3045 | (SHRD32mrCL addr:$dst, R32:$src2)>; |
| 3046 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3047 | // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c) |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 3048 | def : Pat<(or (shl R32:$src1, CL:$amt), |
| 3049 | (srl R32:$src2, (sub 32, CL:$amt))), |
| 3050 | (SHLD32rrCL R32:$src1, R32:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3051 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3052 | def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt), |
| 3053 | (srl R32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 3054 | (SHLD32mrCL addr:$dst, R32:$src2)>; |
| 3055 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3056 | // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c) |
| 3057 | def : Pat<(or (srl R16:$src1, CL:$amt), |
| 3058 | (shl R16:$src2, (sub 16, CL:$amt))), |
| 3059 | (SHRD16rrCL R16:$src1, R16:$src2)>; |
| 3060 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3061 | def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt), |
| 3062 | (shl R16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 3063 | (SHRD16mrCL addr:$dst, R16:$src2)>; |
| 3064 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3065 | // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c) |
| 3066 | def : Pat<(or (shl R16:$src1, CL:$amt), |
| 3067 | (srl R16:$src2, (sub 16, CL:$amt))), |
| 3068 | (SHLD16rrCL R16:$src1, R16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3069 | |
| 3070 | def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt), |
| 3071 | (srl R16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 3072 | (SHLD16mrCL addr:$dst, R16:$src2)>; |