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Scott Michel564427e2007-12-05 01:24:05 +00001//===- SPUSchedule.td - Cell Scheduling Definitions --------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Scott Michel564427e2007-12-05 01:24:05 +00007//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Even pipeline:
12
13def EVEN_UNIT : FuncUnit; // Even execution unit: (PC & 0x7 == 000)
14def ODD_UNIT : FuncUnit; // Odd execution unit: (PC & 0x7 == 100)
15
16//===----------------------------------------------------------------------===//
17// Instruction Itinerary classes used for Cell SPU
18//===----------------------------------------------------------------------===//
19
20def LoadStore : InstrItinClass; // ODD_UNIT
21def BranchHints : InstrItinClass; // ODD_UNIT
22def BranchResolv : InstrItinClass; // ODD_UNIT
23def ChanOpSPR : InstrItinClass; // ODD_UNIT
24def ShuffleOp : InstrItinClass; // ODD_UNIT
25def SelectOp : InstrItinClass; // ODD_UNIT
26def GatherOp : InstrItinClass; // ODD_UNIT
27def LoadNOP : InstrItinClass; // ODD_UNIT
28def ExecNOP : InstrItinClass; // EVEN_UNIT
29def SPrecFP : InstrItinClass; // EVEN_UNIT
30def DPrecFP : InstrItinClass; // EVEN_UNIT
31def FPInt : InstrItinClass; // EVEN_UNIT (FP<->integer)
32def ByteOp : InstrItinClass; // EVEN_UNIT
33def IntegerOp : InstrItinClass; // EVEN_UNIT
34def IntegerMulDiv: InstrItinClass; // EVEN_UNIT
35def RotateShift : InstrItinClass; // EVEN_UNIT
36def ImmLoad : InstrItinClass; // EVEN_UNIT
37
38/* Note: The itinerary for the Cell SPU is somewhat contrived... */
Evan Cheng63d66ee2010-09-28 23:50:49 +000039def SPUItineraries : ProcessorItineraries<[ODD_UNIT, EVEN_UNIT], [], [
Scott Michel564427e2007-12-05 01:24:05 +000040 InstrItinData<LoadStore , [InstrStage<6, [ODD_UNIT]>]>,
41 InstrItinData<BranchHints , [InstrStage<6, [ODD_UNIT]>]>,
42 InstrItinData<BranchResolv, [InstrStage<4, [ODD_UNIT]>]>,
43 InstrItinData<ChanOpSPR , [InstrStage<6, [ODD_UNIT]>]>,
44 InstrItinData<ShuffleOp , [InstrStage<4, [ODD_UNIT]>]>,
45 InstrItinData<SelectOp , [InstrStage<4, [ODD_UNIT]>]>,
46 InstrItinData<GatherOp , [InstrStage<4, [ODD_UNIT]>]>,
47 InstrItinData<LoadNOP , [InstrStage<1, [ODD_UNIT]>]>,
48 InstrItinData<ExecNOP , [InstrStage<1, [EVEN_UNIT]>]>,
49 InstrItinData<SPrecFP , [InstrStage<6, [EVEN_UNIT]>]>,
50 InstrItinData<DPrecFP , [InstrStage<13, [EVEN_UNIT]>]>,
51 InstrItinData<FPInt , [InstrStage<2, [EVEN_UNIT]>]>,
52 InstrItinData<ByteOp , [InstrStage<4, [EVEN_UNIT]>]>,
53 InstrItinData<IntegerOp , [InstrStage<2, [EVEN_UNIT]>]>,
54 InstrItinData<RotateShift , [InstrStage<4, [EVEN_UNIT]>]>,
55 InstrItinData<IntegerMulDiv,[InstrStage<7, [EVEN_UNIT]>]>,
56 InstrItinData<ImmLoad , [InstrStage<2, [EVEN_UNIT]>]>
57 ]>;