Arnold Schwaighofer | 48abc5c | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3, |
| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 22 | SDTCisInt<0>, SDTCisInt<3>]>; |
| 23 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 24 | def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 25 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 26 | def SDTX86Cmov : SDTypeProfile<1, 4, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
| 28 | SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 29 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 30 | // Unary and binary operator instructions that set EFLAGS as a side-effect. |
| 31 | def SDTUnaryArithWithFlags : SDTypeProfile<1, 1, |
| 32 | [SDTCisInt<0>]>; |
| 33 | def SDTBinaryArithWithFlags : SDTypeProfile<1, 2, |
| 34 | [SDTCisSameAs<0, 1>, |
| 35 | SDTCisSameAs<0, 2>, |
| 36 | SDTCisInt<0>]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 37 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 38 | def SDTX86BrCond : SDTypeProfile<0, 3, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 39 | [SDTCisVT<0, OtherVT>, |
| 40 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 41 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 42 | def SDTX86SetCC : SDTypeProfile<1, 2, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 43 | [SDTCisVT<0, i8>, |
| 44 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 45 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 46 | def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, |
| 47 | SDTCisVT<2, i8>]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 48 | def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 49 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 50 | def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, |
| 51 | SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 52 | def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 53 | |
Bill Wendling | c69107c | 2007-11-13 09:19:02 +0000 | [diff] [blame] | 54 | def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; |
| 55 | def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, |
| 56 | SDTCisVT<1, i32> ]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 57 | |
Dan Gohman | d35121a | 2008-05-29 19:57:41 +0000 | [diff] [blame] | 58 | def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 59 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 60 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; |
| 61 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 62 | def SDTX86RdTsc : SDTypeProfile<0, 0, []>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 63 | |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 64 | def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; |
| 65 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 66 | def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>; |
| 67 | |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 68 | def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 69 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 70 | def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 71 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 72 | def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; |
| 73 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 74 | def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>; |
| 75 | def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 76 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; |
| 77 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 78 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 79 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 80 | |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 81 | def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; |
| 82 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 83 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 84 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 85 | [SDNPHasChain]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 86 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 87 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 88 | def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, |
| 89 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 90 | SDNPMayLoad]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 91 | def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8, |
| 92 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 93 | SDNPMayLoad]>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 94 | def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, |
| 95 | [SDNPHasChain, SDNPMayStore, |
| 96 | SDNPMayLoad, SDNPMemOperand]>; |
| 97 | def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, |
| 98 | [SDNPHasChain, SDNPMayStore, |
| 99 | SDNPMayLoad, SDNPMemOperand]>; |
| 100 | def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, |
| 101 | [SDNPHasChain, SDNPMayStore, |
| 102 | SDNPMayLoad, SDNPMemOperand]>; |
| 103 | def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, |
| 104 | [SDNPHasChain, SDNPMayStore, |
| 105 | SDNPMayLoad, SDNPMemOperand]>; |
| 106 | def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, |
| 107 | [SDNPHasChain, SDNPMayStore, |
| 108 | SDNPMayLoad, SDNPMemOperand]>; |
| 109 | def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, |
| 110 | [SDNPHasChain, SDNPMayStore, |
| 111 | SDNPMayLoad, SDNPMemOperand]>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 112 | def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, |
| 113 | [SDNPHasChain, SDNPMayStore, |
| 114 | SDNPMayLoad, SDNPMemOperand]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 115 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, |
| 116 | [SDNPHasChain, SDNPOptInFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 117 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 118 | def X86callseq_start : |
| 119 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, |
Evan Cheng | bb7b844 | 2006-08-11 09:03:33 +0000 | [diff] [blame] | 120 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 121 | def X86callseq_end : |
| 122 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 123 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 124 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 125 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, |
| 126 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 127 | |
Evan Cheng | fb914c4 | 2006-05-20 01:40:16 +0000 | [diff] [blame] | 128 | def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call, |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 129 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; |
| 130 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 131 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 132 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 133 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 134 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 135 | SDNPMayLoad]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 136 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 137 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc, |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 138 | [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 139 | |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 140 | def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; |
| 141 | def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 142 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 143 | def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame] | 144 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 145 | def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress", |
| 146 | SDT_X86SegmentBaseAddress, []>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 147 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 148 | def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, |
| 149 | [SDNPHasChain]>; |
| 150 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 151 | def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, |
| 152 | [SDNPHasChain, SDNPOptInFlag]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 153 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 154 | def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>; |
| 155 | def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; |
| 156 | def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>; |
| 157 | def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; |
| 158 | def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; |
| 159 | def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 160 | |
Evan Cheng | 73f24c9 | 2009-03-30 21:36:47 +0000 | [diff] [blame] | 161 | def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; |
| 162 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 163 | //===----------------------------------------------------------------------===// |
| 164 | // X86 Operand Definitions. |
| 165 | // |
| 166 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 167 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 168 | // |
Evan Cheng | af78ef5 | 2006-05-17 21:21:41 +0000 | [diff] [blame] | 169 | class X86MemOperand<string printMethod> : Operand<iPTR> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 170 | let PrintMethod = printMethod; |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 171 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm); |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 172 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 173 | |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 174 | def i8mem : X86MemOperand<"printi8mem">; |
| 175 | def i16mem : X86MemOperand<"printi16mem">; |
| 176 | def i32mem : X86MemOperand<"printi32mem">; |
| 177 | def i64mem : X86MemOperand<"printi64mem">; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 178 | def i128mem : X86MemOperand<"printi128mem">; |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 179 | def f32mem : X86MemOperand<"printf32mem">; |
| 180 | def f64mem : X86MemOperand<"printf64mem">; |
Dale Johannesen | 59a5873 | 2007-08-05 18:49:15 +0000 | [diff] [blame] | 181 | def f80mem : X86MemOperand<"printf80mem">; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 182 | def f128mem : X86MemOperand<"printf128mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 183 | |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 184 | // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of |
| 185 | // plain GR64, so that it doesn't potentially require a REX prefix. |
| 186 | def i8mem_NOREX : Operand<i64> { |
| 187 | let PrintMethod = "printi8mem"; |
| 188 | let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX, i32imm, i8imm); |
| 189 | } |
| 190 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 191 | def lea32mem : Operand<i32> { |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 192 | let PrintMethod = "printlea32mem"; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 193 | let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm); |
| 194 | } |
| 195 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 196 | def SSECC : Operand<i8> { |
| 197 | let PrintMethod = "printSSECC"; |
| 198 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 199 | |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 200 | def piclabel: Operand<i32> { |
| 201 | let PrintMethod = "printPICLabel"; |
| 202 | } |
| 203 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 204 | // A couple of more descriptive operand definitions. |
| 205 | // 16-bits but only 8 bits are significant. |
| 206 | def i16i8imm : Operand<i16>; |
| 207 | // 32-bits but only 8 bits are significant. |
| 208 | def i32i8imm : Operand<i32>; |
| 209 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 210 | // Branch targets have OtherVT type. |
| 211 | def brtarget : Operand<OtherVT>; |
| 212 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 213 | //===----------------------------------------------------------------------===// |
| 214 | // X86 Complex Pattern Definitions. |
| 215 | // |
| 216 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 217 | // Define X86 specific addressing mode. |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 218 | def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 219 | def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr", |
Evan Cheng | af9db75 | 2006-10-11 21:03:53 +0000 | [diff] [blame] | 220 | [add, mul, shl, or, frameindex], []>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 221 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 222 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 223 | // X86 Instruction Predicate Definitions. |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 224 | def HasMMX : Predicate<"Subtarget->hasMMX()">; |
| 225 | def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; |
| 226 | def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; |
| 227 | def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; |
Bill Wendling | bb1ee05 | 2007-04-10 22:10:25 +0000 | [diff] [blame] | 228 | def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 229 | def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; |
| 230 | def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 231 | def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; |
| 232 | def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 233 | def In32BitMode : Predicate<"!Subtarget->is64Bit()">; |
| 234 | def In64BitMode : Predicate<"Subtarget->is64Bit()">; |
| 235 | def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; |
| 236 | def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">; |
| 237 | def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 238 | def OptForSpeed : Predicate<"!OptForSize">; |
Evan Cheng | ccb6976 | 2009-01-02 05:35:45 +0000 | [diff] [blame] | 239 | def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 240 | |
| 241 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 242 | // X86 Instruction Format Definitions. |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 243 | // |
| 244 | |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 245 | include "X86InstrFormats.td" |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 246 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 247 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 248 | // Pattern fragments... |
| 249 | // |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 250 | |
| 251 | // X86 specific condition code. These correspond to CondCode in |
Nate Begeman | 9a22530 | 2007-05-06 04:00:55 +0000 | [diff] [blame] | 252 | // X86InstrInfo.h. They must be kept in synch. |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 253 | def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE |
| 254 | def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC |
| 255 | def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C |
| 256 | def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA |
| 257 | def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z |
| 258 | def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE |
| 259 | def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL |
| 260 | def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE |
| 261 | def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG |
| 262 | def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 263 | def X86_COND_NO : PatLeaf<(i8 10)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 264 | def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 265 | def X86_COND_NS : PatLeaf<(i8 12)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 266 | def X86_COND_O : PatLeaf<(i8 13)>; |
| 267 | def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE |
| 268 | def X86_COND_S : PatLeaf<(i8 15)>; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 269 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 270 | def i16immSExt8 : PatLeaf<(i16 imm), [{ |
| 271 | // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 272 | // sign extended field. |
Dan Gohman | f5aeb1a | 2008-09-12 16:56:44 +0000 | [diff] [blame] | 273 | return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue(); |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 274 | }]>; |
| 275 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 276 | def i32immSExt8 : PatLeaf<(i32 imm), [{ |
| 277 | // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 278 | // sign extended field. |
Dan Gohman | f5aeb1a | 2008-09-12 16:56:44 +0000 | [diff] [blame] | 279 | return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue(); |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 280 | }]>; |
| 281 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 282 | // Helper fragments for loads. |
Evan Cheng | b656443 | 2008-05-13 18:59:59 +0000 | [diff] [blame] | 283 | // It's always safe to treat a anyext i16 load as a i32 load if the i16 is |
| 284 | // known to be 32-bit aligned or better. Ditto for i8 to i16. |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 285 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 286 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 287 | if (const Value *Src = LD->getSrcValue()) |
| 288 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 289 | if (PT->getAddressSpace() != 0) |
| 290 | return false; |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 291 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 292 | if (ExtType == ISD::NON_EXTLOAD) |
| 293 | return true; |
| 294 | if (ExtType == ISD::EXTLOAD) |
| 295 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 296 | return false; |
| 297 | }]>; |
| 298 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 299 | def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 300 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 301 | if (const Value *Src = LD->getSrcValue()) |
| 302 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 303 | if (PT->getAddressSpace() != 0) |
| 304 | return false; |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 305 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 306 | if (ExtType == ISD::EXTLOAD) |
| 307 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
| 308 | return false; |
| 309 | }]>; |
| 310 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 311 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 312 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 313 | if (const Value *Src = LD->getSrcValue()) |
| 314 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 315 | if (PT->getAddressSpace() != 0) |
| 316 | return false; |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 317 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 318 | if (ExtType == ISD::NON_EXTLOAD) |
| 319 | return true; |
| 320 | if (ExtType == ISD::EXTLOAD) |
| 321 | return LD->getAlignment() >= 4 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 322 | return false; |
| 323 | }]>; |
| 324 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 325 | def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 326 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 327 | if (const Value *Src = LD->getSrcValue()) |
| 328 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 329 | if (PT->getAddressSpace() != 0) |
| 330 | return false; |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 331 | if (LD->isVolatile()) |
| 332 | return false; |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 333 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 334 | if (ExtType == ISD::NON_EXTLOAD) |
| 335 | return true; |
| 336 | if (ExtType == ISD::EXTLOAD) |
| 337 | return LD->getAlignment() >= 4; |
| 338 | return false; |
| 339 | }]>; |
| 340 | |
Nate Begeman | 51a0437 | 2009-01-26 01:24:32 +0000 | [diff] [blame] | 341 | def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 342 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 343 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 344 | return PT->getAddressSpace() == 256; |
Nate Begeman | 51a0437 | 2009-01-26 01:24:32 +0000 | [diff] [blame] | 345 | return false; |
| 346 | }]>; |
| 347 | |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 348 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{ |
| 349 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 350 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 351 | if (PT->getAddressSpace() != 0) |
| 352 | return false; |
| 353 | return true; |
| 354 | }]>; |
| 355 | def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{ |
| 356 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 357 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 358 | if (PT->getAddressSpace() != 0) |
| 359 | return false; |
| 360 | return true; |
| 361 | }]>; |
Evan Cheng | 06a8aa1 | 2006-03-17 19:55:52 +0000 | [diff] [blame] | 362 | |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 363 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{ |
| 364 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 365 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 366 | if (PT->getAddressSpace() != 0) |
| 367 | return false; |
| 368 | return true; |
| 369 | }]>; |
| 370 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{ |
| 371 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 372 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 373 | if (PT->getAddressSpace() != 0) |
| 374 | return false; |
| 375 | return true; |
| 376 | }]>; |
| 377 | def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{ |
| 378 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 379 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 380 | if (PT->getAddressSpace() != 0) |
| 381 | return false; |
| 382 | return true; |
| 383 | }]>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 384 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 385 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; |
| 386 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; |
| 387 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 388 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 389 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; |
| 390 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; |
| 391 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; |
| 392 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; |
| 393 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; |
| 394 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 395 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 396 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; |
| 397 | def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; |
| 398 | def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; |
| 399 | def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; |
| 400 | def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; |
| 401 | def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 402 | |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 403 | |
| 404 | // An 'and' node with a single use. |
| 405 | def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ |
Evan Cheng | 07b7ea1 | 2008-03-04 00:40:35 +0000 | [diff] [blame] | 406 | return N->hasOneUse(); |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 407 | }]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 408 | // An 'srl' node with a single use. |
| 409 | def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ |
| 410 | return N->hasOneUse(); |
| 411 | }]>; |
| 412 | // An 'trunc' node with a single use. |
| 413 | def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ |
| 414 | return N->hasOneUse(); |
| 415 | }]>; |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 416 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 417 | // 'shld' and 'shrd' instruction patterns. Note that even though these have |
| 418 | // the srl and shl in their patterns, the C++ code must still check for them, |
| 419 | // because predicates are tested before children nodes are explored. |
| 420 | |
| 421 | def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2), |
| 422 | (or (srl node:$src1, node:$amt1), |
| 423 | (shl node:$src2, node:$amt2)), [{ |
| 424 | assert(N->getOpcode() == ISD::OR); |
| 425 | return N->getOperand(0).getOpcode() == ISD::SRL && |
| 426 | N->getOperand(1).getOpcode() == ISD::SHL && |
| 427 | isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) && |
| 428 | isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) && |
| 429 | N->getOperand(0).getConstantOperandVal(1) == |
| 430 | N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1); |
| 431 | }]>; |
| 432 | |
| 433 | def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2), |
| 434 | (or (shl node:$src1, node:$amt1), |
| 435 | (srl node:$src2, node:$amt2)), [{ |
| 436 | assert(N->getOpcode() == ISD::OR); |
| 437 | return N->getOperand(0).getOpcode() == ISD::SHL && |
| 438 | N->getOperand(1).getOpcode() == ISD::SRL && |
| 439 | isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) && |
| 440 | isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) && |
| 441 | N->getOperand(0).getConstantOperandVal(1) == |
| 442 | N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1); |
| 443 | }]>; |
| 444 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 445 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 446 | // Instruction list... |
| 447 | // |
| 448 | |
Chris Lattner | f18c074 | 2006-10-12 17:42:56 +0000 | [diff] [blame] | 449 | // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into |
| 450 | // a stack adjustment and the codegen must know that they may modify the stack |
| 451 | // pointer before prolog-epilog rewriting occurs. |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 452 | // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become |
| 453 | // sub / add which can clobber EFLAGS. |
Evan Cheng | 8decf6b | 2007-09-28 01:19:48 +0000 | [diff] [blame] | 454 | let Defs = [ESP, EFLAGS], Uses = [ESP] in { |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 455 | def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt), |
| 456 | "#ADJCALLSTACKDOWN", |
Chris Lattner | e563bbc | 2008-10-11 22:08:30 +0000 | [diff] [blame] | 457 | [(X86callseq_start timm:$amt)]>, |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 458 | Requires<[In32BitMode]>; |
| 459 | def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), |
| 460 | "#ADJCALLSTACKUP", |
Chris Lattner | e563bbc | 2008-10-11 22:08:30 +0000 | [diff] [blame] | 461 | [(X86callseq_end timm:$amt1, timm:$amt2)]>, |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 462 | Requires<[In32BitMode]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 463 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 464 | |
| 465 | // Nop |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 466 | let neverHasSideEffects = 1 in |
| 467 | def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 468 | |
Evan Cheng | 0475ab5 | 2008-01-05 00:41:47 +0000 | [diff] [blame] | 469 | // PIC base |
Dan Gohman | 2662d55 | 2008-10-01 04:14:30 +0000 | [diff] [blame] | 470 | let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 471 | def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label), |
| 472 | "call\t$label\n\tpop{l}\t$reg", []>; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 473 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 474 | //===----------------------------------------------------------------------===// |
| 475 | // Control Flow Instructions... |
| 476 | // |
| 477 | |
Chris Lattner | 1be4811 | 2005-05-13 17:56:48 +0000 | [diff] [blame] | 478 | // Return instructions. |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 479 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 480 | hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in { |
Dan Gohman | e4c67cd | 2008-05-31 02:11:25 +0000 | [diff] [blame] | 481 | def RET : I <0xC3, RawFrm, (outs), (ins variable_ops), |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 482 | "ret", |
Dan Gohman | e4c67cd | 2008-05-31 02:11:25 +0000 | [diff] [blame] | 483 | [(X86retflag 0)]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 484 | def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), |
| 485 | "ret\t$amt", |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 486 | [(X86retflag imm:$amt)]>; |
Evan Cheng | 171049d | 2005-12-23 22:14:32 +0000 | [diff] [blame] | 487 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 488 | |
| 489 | // All branches are RawFrm, Void, Branch, and Terminators |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 490 | let isBranch = 1, isTerminator = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 491 | class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> : |
| 492 | I<opcode, RawFrm, (outs), ins, asm, pattern>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 493 | |
Evan Cheng | ec3bc39 | 2006-09-07 19:03:48 +0000 | [diff] [blame] | 494 | let isBranch = 1, isBarrier = 1 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 495 | def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 496 | |
Owen Anderson | 20ab290 | 2007-11-12 07:39:39 +0000 | [diff] [blame] | 497 | // Indirect branches |
| 498 | let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 499 | def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 500 | [(brind GR32:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 501 | def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 502 | [(brind (loadi32 addr:$dst))]>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | // Conditional branches |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 506 | let Uses = [EFLAGS] in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 507 | def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 508 | [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 509 | def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 510 | [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 511 | def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 512 | [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 513 | def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 514 | [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 515 | def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 516 | [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 517 | def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 518 | [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 519 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 520 | def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 521 | [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 522 | def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 523 | [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 524 | def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 525 | [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 526 | def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 527 | [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 528 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 529 | def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 530 | [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 531 | def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 532 | [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 533 | def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 534 | [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 535 | def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 536 | [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 537 | def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 538 | [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 539 | def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 540 | [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 541 | } // Uses = [EFLAGS] |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 542 | |
| 543 | //===----------------------------------------------------------------------===// |
| 544 | // Call Instructions... |
| 545 | // |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 546 | let isCall = 1 in |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 547 | // All calls clobber the non-callee saved registers. ESP is marked as |
| 548 | // a use to prevent stack-pointer assignments that appear immediately |
| 549 | // before calls from potentially appearing dead. Uses for argument |
| 550 | // registers are added manually. |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 551 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
Bill Wendling | 3f3a17d | 2007-04-25 21:31:48 +0000 | [diff] [blame] | 552 | MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, |
Evan Cheng | 109a562 | 2008-10-17 21:02:22 +0000 | [diff] [blame] | 553 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 554 | XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], |
Dan Gohman | 2662d55 | 2008-10-01 04:14:30 +0000 | [diff] [blame] | 555 | Uses = [ESP] in { |
Evan Cheng | f02ca69 | 2007-12-22 02:26:46 +0000 | [diff] [blame] | 556 | def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops), |
Evan Cheng | a065200 | 2009-03-12 18:15:39 +0000 | [diff] [blame] | 557 | "call\t${dst:call}", [(X86call imm:$dst)]>, |
| 558 | Requires<[In32BitMode]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 559 | def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 560 | "call\t{*}$dst", [(X86call GR32:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 561 | def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops), |
Dan Gohman | b410617 | 2008-05-29 21:50:34 +0000 | [diff] [blame] | 562 | "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 563 | } |
| 564 | |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 565 | // Tail call stuff. |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 566 | |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 567 | def TAILCALL : I<0, Pseudo, (outs), (ins), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 568 | "#TAILCALL", |
| 569 | []>; |
| 570 | |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 571 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | 4fe3073 | 2008-03-19 16:39:45 +0000 | [diff] [blame] | 572 | def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 573 | "#TC_RETURN $dst $offset", |
| 574 | []>; |
| 575 | |
| 576 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | 4fe3073 | 2008-03-19 16:39:45 +0000 | [diff] [blame] | 577 | def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 578 | "#TC_RETURN $dst $offset", |
| 579 | []>; |
| 580 | |
| 581 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 582 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 583 | def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL", |
Evan Cheng | f10c17f | 2006-09-22 21:43:59 +0000 | [diff] [blame] | 584 | []>; |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 585 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 586 | def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL", |
| 587 | []>; |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 588 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 589 | def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 590 | "jmp\t{*}$dst # TAILCALL", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 591 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 592 | //===----------------------------------------------------------------------===// |
| 593 | // Miscellaneous Instructions... |
| 594 | // |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 595 | let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 596 | def LEAVE : I<0xC9, RawFrm, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 597 | (outs), (ins), "leave", []>; |
| 598 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 599 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { |
| 600 | let mayLoad = 1 in |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 601 | def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 602 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 603 | let mayStore = 1 in |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 604 | def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 605 | } |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 606 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 607 | let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in |
Evan Cheng | bf4f89d | 2007-09-26 21:28:00 +0000 | [diff] [blame] | 608 | def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 609 | let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in |
Evan Cheng | bf4f89d | 2007-09-26 21:28:00 +0000 | [diff] [blame] | 610 | def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>; |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 611 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 612 | let isTwoAddress = 1 in // GR32 = bswap GR32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 613 | def BSWAP32r : I<0xC8, AddRegFrm, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 614 | (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 615 | "bswap{l}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 616 | [(set GR32:$dst, (bswap GR32:$src))]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 617 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 618 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 619 | // Bit scan instructions. |
| 620 | let Defs = [EFLAGS] in { |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 621 | def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 622 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 623 | [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 624 | def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 625 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 626 | [(set GR16:$dst, (X86bsf (loadi16 addr:$src))), |
| 627 | (implicit EFLAGS)]>, TB; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 628 | def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 629 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 630 | [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 631 | def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 632 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 633 | [(set GR32:$dst, (X86bsf (loadi32 addr:$src))), |
| 634 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 635 | |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 636 | def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 637 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 638 | [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 639 | def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 640 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 641 | [(set GR16:$dst, (X86bsr (loadi16 addr:$src))), |
| 642 | (implicit EFLAGS)]>, TB; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 643 | def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 644 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 645 | [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 646 | def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 647 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 648 | [(set GR32:$dst, (X86bsr (loadi32 addr:$src))), |
| 649 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 650 | } // Defs = [EFLAGS] |
| 651 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 652 | let neverHasSideEffects = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 653 | def LEA16r : I<0x8D, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 654 | (outs GR16:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 655 | "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize; |
Evan Cheng | e771ebd | 2008-03-27 01:41:09 +0000 | [diff] [blame] | 656 | let isReMaterializable = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 657 | def LEA32r : I<0x8D, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 658 | (outs GR32:$dst), (ins lea32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 659 | "lea{l}\t{$src|$dst}, {$dst|$src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 660 | [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 661 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 662 | let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 663 | def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 664 | [(X86rep_movs i8)]>, REP; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 665 | def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 666 | [(X86rep_movs i16)]>, REP, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 667 | def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 668 | [(X86rep_movs i32)]>, REP; |
| 669 | } |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 670 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 671 | let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 672 | def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 673 | [(X86rep_stos i8)]>, REP; |
| 674 | let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 675 | def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 676 | [(X86rep_stos i16)]>, REP, OpSize; |
| 677 | let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 678 | def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 679 | [(X86rep_stos i32)]>, REP; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 680 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 681 | let Defs = [RAX, RDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 682 | def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 683 | TB; |
Chris Lattner | b89abef | 2004-02-14 04:45:37 +0000 | [diff] [blame] | 684 | |
Anton Korobeynikov | 66fac79 | 2008-01-15 07:02:33 +0000 | [diff] [blame] | 685 | let isBarrier = 1, hasCtrlDep = 1 in { |
Chris Lattner | da68d30 | 2008-01-15 21:58:22 +0000 | [diff] [blame] | 686 | def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; |
Anton Korobeynikov | 66fac79 | 2008-01-15 07:02:33 +0000 | [diff] [blame] | 687 | } |
| 688 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 689 | //===----------------------------------------------------------------------===// |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 690 | // Input/Output Instructions... |
| 691 | // |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 692 | let Defs = [AL], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 693 | def IN8rr : I<0xEC, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 694 | "in{b}\t{%dx, %al|%AL, %DX}", []>; |
| 695 | let Defs = [AX], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 696 | def IN16rr : I<0xED, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 697 | "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize; |
| 698 | let Defs = [EAX], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 699 | def IN32rr : I<0xED, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 700 | "in{l}\t{%dx, %eax|%EAX, %DX}", []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 701 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 702 | let Defs = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 703 | def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 704 | "in{b}\t{$port, %al|%AL, $port}", []>; |
| 705 | let Defs = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 706 | def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 707 | "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize; |
| 708 | let Defs = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 709 | def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 710 | "in{l}\t{$port, %eax|%EAX, $port}", []>; |
Chris Lattner | 440bbc2 | 2004-04-13 17:19:31 +0000 | [diff] [blame] | 711 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 712 | let Uses = [DX, AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 713 | def OUT8rr : I<0xEE, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 714 | "out{b}\t{%al, %dx|%DX, %AL}", []>; |
| 715 | let Uses = [DX, AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 716 | def OUT16rr : I<0xEF, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 717 | "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize; |
| 718 | let Uses = [DX, EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 719 | def OUT32rr : I<0xEF, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 720 | "out{l}\t{%eax, %dx|%DX, %EAX}", []>; |
Chris Lattner | ffff708 | 2004-08-01 07:44:35 +0000 | [diff] [blame] | 721 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 722 | let Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 723 | def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 724 | "out{b}\t{%al, $port|$port, %AL}", []>; |
| 725 | let Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 726 | def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 727 | "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize; |
| 728 | let Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 729 | def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 730 | "out{l}\t{%eax, $port|$port, %EAX}", []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 731 | |
| 732 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 733 | // Move Instructions... |
| 734 | // |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 735 | let neverHasSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 736 | def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 737 | "mov{b}\t{$src, $dst|$dst, $src}", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 738 | def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 739 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 740 | def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 741 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 742 | } |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 743 | let isReMaterializable = 1, isAsCheapAsAMove = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 744 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 745 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 746 | [(set GR8:$dst, imm:$src)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 747 | def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 748 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 749 | [(set GR16:$dst, imm:$src)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 750 | def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 751 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 752 | [(set GR32:$dst, imm:$src)]>; |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 753 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 754 | def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 755 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 756 | [(store (i8 imm:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 757 | def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 758 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 759 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 760 | def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 761 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 762 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 763 | |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 764 | let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 765 | def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 766 | "mov{b}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 767 | [(set GR8:$dst, (loadi8 addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 768 | def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 769 | "mov{w}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 770 | [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 771 | def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 772 | "mov{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 773 | [(set GR32:$dst, (loadi32 addr:$src))]>; |
Evan Cheng | 2f39426 | 2007-08-30 05:49:43 +0000 | [diff] [blame] | 774 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 775 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 776 | def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 777 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 778 | [(store GR8:$src, addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 779 | def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 780 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 781 | [(store GR16:$src, addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 782 | def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 783 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 784 | [(store GR32:$src, addr:$dst)]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 785 | |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame^] | 786 | // Versions of MOV8rr and MOV8mr that use i8mem_NOREX and GR8_NOREX so that they |
| 787 | // can be used for copying and storing h registers, which can't be encoded when |
| 788 | // a REX prefix is present. |
| 789 | let neverHasSideEffects = 1 in |
| 790 | def MOV8rr_NOREX : I<0x88, MRMDestReg, (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), |
| 791 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
| 792 | def MOV8mr_NOREX : I<0x88, MRMDestMem, |
| 793 | (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), |
| 794 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 795 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 796 | //===----------------------------------------------------------------------===// |
| 797 | // Fixed-Register Multiplication and Division Instructions... |
| 798 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 799 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 800 | // Extra precision multiplication |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 801 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 802 | def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 803 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 804 | // This probably ought to be moved to a def : Pat<> if the |
| 805 | // syntax can be accepted. |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 806 | [(set AL, (mul AL, GR8:$src)), |
| 807 | (implicit EFLAGS)]>; // AL,AH = AL*GR8 |
| 808 | |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 809 | let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 810 | def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), |
| 811 | "mul{w}\t$src", |
| 812 | []>, OpSize; // AX,DX = AX*GR16 |
| 813 | |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 814 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 815 | def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), |
| 816 | "mul{l}\t$src", |
| 817 | []>; // EAX,EDX = EAX*GR32 |
| 818 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 819 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 820 | def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 821 | "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 822 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 823 | // This probably ought to be moved to a def : Pat<> if the |
| 824 | // syntax can be accepted. |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 825 | [(set AL, (mul AL, (loadi8 addr:$src))), |
| 826 | (implicit EFLAGS)]>; // AL,AH = AL*[mem8] |
| 827 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 828 | let mayLoad = 1, neverHasSideEffects = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 829 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 830 | def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 831 | "mul{w}\t$src", |
| 832 | []>, OpSize; // AX,DX = AX*[mem16] |
| 833 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 834 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 835 | def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 836 | "mul{l}\t$src", |
| 837 | []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 838 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 839 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 840 | let neverHasSideEffects = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 841 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 842 | def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>; |
| 843 | // AL,AH = AL*GR8 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 844 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 845 | def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 846 | OpSize; // AX,DX = AX*GR16 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 847 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 848 | def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>; |
| 849 | // EAX,EDX = EAX*GR32 |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 850 | let mayLoad = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 851 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 852 | def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 853 | "imul{b}\t$src", []>; // AL,AH = AL*[mem8] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 854 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 855 | def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 856 | "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16] |
| 857 | let Defs = [EAX,EDX], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 858 | def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 859 | "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 860 | } |
Dan Gohman | c99da13 | 2008-11-18 21:29:14 +0000 | [diff] [blame] | 861 | } // neverHasSideEffects |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 862 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 863 | // unsigned division/remainder |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 864 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 865 | def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 866 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 867 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 868 | def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 869 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 870 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 871 | def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 872 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 873 | let mayLoad = 1 in { |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 874 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 875 | def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 876 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 877 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 878 | def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 879 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 880 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 881 | def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 882 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 883 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 884 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 885 | // Signed division/remainder. |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 886 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 887 | def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 888 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 889 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 890 | def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 891 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 892 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 893 | def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 894 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 895 | let mayLoad = 1, mayLoad = 1 in { |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 896 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 897 | def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 898 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 899 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 900 | def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 901 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 902 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 903 | def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 904 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 905 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 906 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 907 | //===----------------------------------------------------------------------===// |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 908 | // Two address Instructions. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 909 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 910 | let isTwoAddress = 1 in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 911 | |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 912 | // Conditional moves |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 913 | let Uses = [EFLAGS] in { |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 914 | let isCommutable = 1 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 915 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 916 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 917 | "cmovb\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 918 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 919 | X86_COND_B, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 920 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 921 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 922 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 923 | "cmovb\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 924 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 925 | X86_COND_B, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 926 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 927 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 928 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 929 | "cmovae\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 930 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 931 | X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 932 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 933 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 934 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 935 | "cmovae\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 936 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 937 | X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 938 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 939 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 940 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 941 | "cmove\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 942 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 943 | X86_COND_E, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 944 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 945 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 946 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 947 | "cmove\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 948 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 949 | X86_COND_E, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 950 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 951 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 952 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 953 | "cmovne\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 954 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 955 | X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 956 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 957 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 958 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 959 | "cmovne\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 960 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 961 | X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 962 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 963 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 964 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 965 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 966 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 967 | X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 968 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 969 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 970 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 971 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 972 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 973 | X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 974 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 975 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 976 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 977 | "cmova\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 978 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 979 | X86_COND_A, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 980 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 981 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 982 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 983 | "cmova\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 984 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 985 | X86_COND_A, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 986 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 987 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 988 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 989 | "cmovl\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 990 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 991 | X86_COND_L, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 992 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 993 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 994 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 995 | "cmovl\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 996 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 997 | X86_COND_L, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 998 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 999 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1000 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1001 | "cmovge\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1002 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1003 | X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1004 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1005 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1006 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1007 | "cmovge\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1008 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1009 | X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1010 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1011 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1012 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1013 | "cmovle\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1014 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1015 | X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1016 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1017 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1018 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1019 | "cmovle\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1020 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1021 | X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1022 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1023 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1024 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1025 | "cmovg\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1026 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1027 | X86_COND_G, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1028 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1029 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1030 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1031 | "cmovg\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1032 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1033 | X86_COND_G, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1034 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1035 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1036 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1037 | "cmovs\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1038 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1039 | X86_COND_S, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1040 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1041 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1042 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1043 | "cmovs\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1044 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1045 | X86_COND_S, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1046 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1047 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1048 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1049 | "cmovns\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1050 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1051 | X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1052 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1053 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1054 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1055 | "cmovns\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1056 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1057 | X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1058 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1059 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1060 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1061 | "cmovp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1062 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1063 | X86_COND_P, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1064 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1065 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1066 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1067 | "cmovp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1068 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1069 | X86_COND_P, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1070 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1071 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1072 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1073 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1074 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1075 | X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1076 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1077 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1078 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1079 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1080 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1081 | X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1082 | TB; |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1083 | def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16 |
| 1084 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1085 | "cmovo\t{$src2, $dst|$dst, $src2}", |
| 1086 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
| 1087 | X86_COND_O, EFLAGS))]>, |
| 1088 | TB, OpSize; |
| 1089 | def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32 |
| 1090 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1091 | "cmovo\t{$src2, $dst|$dst, $src2}", |
| 1092 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
| 1093 | X86_COND_O, EFLAGS))]>, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1094 | TB; |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1095 | def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16 |
| 1096 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1097 | "cmovno\t{$src2, $dst|$dst, $src2}", |
| 1098 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
| 1099 | X86_COND_NO, EFLAGS))]>, |
| 1100 | TB, OpSize; |
| 1101 | def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32 |
| 1102 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1103 | "cmovno\t{$src2, $dst|$dst, $src2}", |
| 1104 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
| 1105 | X86_COND_NO, EFLAGS))]>, |
| 1106 | TB; |
| 1107 | } // isCommutable = 1 |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1108 | |
| 1109 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16] |
| 1110 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1111 | "cmovb\t{$src2, $dst|$dst, $src2}", |
| 1112 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1113 | X86_COND_B, EFLAGS))]>, |
| 1114 | TB, OpSize; |
| 1115 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32] |
| 1116 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1117 | "cmovb\t{$src2, $dst|$dst, $src2}", |
| 1118 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1119 | X86_COND_B, EFLAGS))]>, |
| 1120 | TB; |
| 1121 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16] |
| 1122 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1123 | "cmovae\t{$src2, $dst|$dst, $src2}", |
| 1124 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1125 | X86_COND_AE, EFLAGS))]>, |
| 1126 | TB, OpSize; |
| 1127 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32] |
| 1128 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1129 | "cmovae\t{$src2, $dst|$dst, $src2}", |
| 1130 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1131 | X86_COND_AE, EFLAGS))]>, |
| 1132 | TB; |
| 1133 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16] |
| 1134 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1135 | "cmove\t{$src2, $dst|$dst, $src2}", |
| 1136 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1137 | X86_COND_E, EFLAGS))]>, |
| 1138 | TB, OpSize; |
| 1139 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32] |
| 1140 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1141 | "cmove\t{$src2, $dst|$dst, $src2}", |
| 1142 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1143 | X86_COND_E, EFLAGS))]>, |
| 1144 | TB; |
| 1145 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16] |
| 1146 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1147 | "cmovne\t{$src2, $dst|$dst, $src2}", |
| 1148 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1149 | X86_COND_NE, EFLAGS))]>, |
| 1150 | TB, OpSize; |
| 1151 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32] |
| 1152 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1153 | "cmovne\t{$src2, $dst|$dst, $src2}", |
| 1154 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1155 | X86_COND_NE, EFLAGS))]>, |
| 1156 | TB; |
| 1157 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16] |
| 1158 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1159 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
| 1160 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1161 | X86_COND_BE, EFLAGS))]>, |
| 1162 | TB, OpSize; |
| 1163 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32] |
| 1164 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1165 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
| 1166 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1167 | X86_COND_BE, EFLAGS))]>, |
| 1168 | TB; |
| 1169 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16] |
| 1170 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1171 | "cmova\t{$src2, $dst|$dst, $src2}", |
| 1172 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1173 | X86_COND_A, EFLAGS))]>, |
| 1174 | TB, OpSize; |
| 1175 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32] |
| 1176 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1177 | "cmova\t{$src2, $dst|$dst, $src2}", |
| 1178 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1179 | X86_COND_A, EFLAGS))]>, |
| 1180 | TB; |
| 1181 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16] |
| 1182 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1183 | "cmovl\t{$src2, $dst|$dst, $src2}", |
| 1184 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1185 | X86_COND_L, EFLAGS))]>, |
| 1186 | TB, OpSize; |
| 1187 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32] |
| 1188 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1189 | "cmovl\t{$src2, $dst|$dst, $src2}", |
| 1190 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1191 | X86_COND_L, EFLAGS))]>, |
| 1192 | TB; |
| 1193 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16] |
| 1194 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1195 | "cmovge\t{$src2, $dst|$dst, $src2}", |
| 1196 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1197 | X86_COND_GE, EFLAGS))]>, |
| 1198 | TB, OpSize; |
| 1199 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32] |
| 1200 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1201 | "cmovge\t{$src2, $dst|$dst, $src2}", |
| 1202 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1203 | X86_COND_GE, EFLAGS))]>, |
| 1204 | TB; |
| 1205 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16] |
| 1206 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1207 | "cmovle\t{$src2, $dst|$dst, $src2}", |
| 1208 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1209 | X86_COND_LE, EFLAGS))]>, |
| 1210 | TB, OpSize; |
| 1211 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32] |
| 1212 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1213 | "cmovle\t{$src2, $dst|$dst, $src2}", |
| 1214 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1215 | X86_COND_LE, EFLAGS))]>, |
| 1216 | TB; |
| 1217 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16] |
| 1218 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1219 | "cmovg\t{$src2, $dst|$dst, $src2}", |
| 1220 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1221 | X86_COND_G, EFLAGS))]>, |
| 1222 | TB, OpSize; |
| 1223 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32] |
| 1224 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1225 | "cmovg\t{$src2, $dst|$dst, $src2}", |
| 1226 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1227 | X86_COND_G, EFLAGS))]>, |
| 1228 | TB; |
| 1229 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16] |
| 1230 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1231 | "cmovs\t{$src2, $dst|$dst, $src2}", |
| 1232 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1233 | X86_COND_S, EFLAGS))]>, |
| 1234 | TB, OpSize; |
| 1235 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32] |
| 1236 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1237 | "cmovs\t{$src2, $dst|$dst, $src2}", |
| 1238 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1239 | X86_COND_S, EFLAGS))]>, |
| 1240 | TB; |
| 1241 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16] |
| 1242 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1243 | "cmovns\t{$src2, $dst|$dst, $src2}", |
| 1244 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1245 | X86_COND_NS, EFLAGS))]>, |
| 1246 | TB, OpSize; |
| 1247 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32] |
| 1248 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1249 | "cmovns\t{$src2, $dst|$dst, $src2}", |
| 1250 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1251 | X86_COND_NS, EFLAGS))]>, |
| 1252 | TB; |
| 1253 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16] |
| 1254 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1255 | "cmovp\t{$src2, $dst|$dst, $src2}", |
| 1256 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1257 | X86_COND_P, EFLAGS))]>, |
| 1258 | TB, OpSize; |
| 1259 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32] |
| 1260 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1261 | "cmovp\t{$src2, $dst|$dst, $src2}", |
| 1262 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1263 | X86_COND_P, EFLAGS))]>, |
| 1264 | TB; |
| 1265 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16] |
| 1266 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1267 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
| 1268 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1269 | X86_COND_NP, EFLAGS))]>, |
| 1270 | TB, OpSize; |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1271 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32] |
| 1272 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1273 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
| 1274 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1275 | X86_COND_NP, EFLAGS))]>, |
| 1276 | TB; |
| 1277 | def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16] |
| 1278 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1279 | "cmovo\t{$src2, $dst|$dst, $src2}", |
| 1280 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1281 | X86_COND_O, EFLAGS))]>, |
| 1282 | TB, OpSize; |
| 1283 | def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32] |
| 1284 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1285 | "cmovo\t{$src2, $dst|$dst, $src2}", |
| 1286 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1287 | X86_COND_O, EFLAGS))]>, |
| 1288 | TB; |
| 1289 | def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16] |
| 1290 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1291 | "cmovno\t{$src2, $dst|$dst, $src2}", |
| 1292 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1293 | X86_COND_NO, EFLAGS))]>, |
| 1294 | TB, OpSize; |
| 1295 | def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32] |
| 1296 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1297 | "cmovno\t{$src2, $dst|$dst, $src2}", |
| 1298 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1299 | X86_COND_NO, EFLAGS))]>, |
| 1300 | TB; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1301 | } // Uses = [EFLAGS] |
| 1302 | |
| 1303 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1304 | // unary instructions |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1305 | let CodeSize = 2 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1306 | let Defs = [EFLAGS] in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1307 | def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1308 | [(set GR8:$dst, (ineg GR8:$src)), |
| 1309 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1310 | def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1311 | [(set GR16:$dst, (ineg GR16:$src)), |
| 1312 | (implicit EFLAGS)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1313 | def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1314 | [(set GR32:$dst, (ineg GR32:$src)), |
| 1315 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1316 | let isTwoAddress = 0 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1317 | def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1318 | [(store (ineg (loadi8 addr:$dst)), addr:$dst), |
| 1319 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1320 | def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1321 | [(store (ineg (loadi16 addr:$dst)), addr:$dst), |
| 1322 | (implicit EFLAGS)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1323 | def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1324 | [(store (ineg (loadi32 addr:$dst)), addr:$dst), |
| 1325 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1326 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1327 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1328 | |
Evan Cheng | aaf414c | 2009-01-21 02:09:05 +0000 | [diff] [blame] | 1329 | // Match xor -1 to not. Favors these over a move imm + xor to save code size. |
| 1330 | let AddedComplexity = 15 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1331 | def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1332 | [(set GR8:$dst, (not GR8:$src))]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1333 | def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1334 | [(set GR16:$dst, (not GR16:$src))]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1335 | def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1336 | [(set GR32:$dst, (not GR32:$src))]>; |
Evan Cheng | aaf414c | 2009-01-21 02:09:05 +0000 | [diff] [blame] | 1337 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1338 | let isTwoAddress = 0 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1339 | def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1340 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1341 | def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1342 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1343 | def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1344 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1345 | } |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1346 | } // CodeSize |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1347 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1348 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1349 | let Defs = [EFLAGS] in { |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1350 | let CodeSize = 2 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1351 | def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1352 | [(set GR8:$dst, (add GR8:$src, 1)), |
| 1353 | (implicit EFLAGS)]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1354 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1355 | def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1356 | [(set GR16:$dst, (add GR16:$src, 1)), |
| 1357 | (implicit EFLAGS)]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1358 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1359 | def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1360 | [(set GR32:$dst, (add GR32:$src, 1)), |
| 1361 | (implicit EFLAGS)]>, Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1362 | } |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1363 | let isTwoAddress = 0, CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1364 | def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1365 | [(store (add (loadi8 addr:$dst), 1), addr:$dst), |
| 1366 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1367 | def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1368 | [(store (add (loadi16 addr:$dst), 1), addr:$dst), |
| 1369 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1370 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1371 | def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1372 | [(store (add (loadi32 addr:$dst), 1), addr:$dst), |
| 1373 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1374 | Requires<[In32BitMode]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1375 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1376 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1377 | let CodeSize = 2 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1378 | def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1379 | [(set GR8:$dst, (add GR8:$src, -1)), |
| 1380 | (implicit EFLAGS)]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1381 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1382 | def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1383 | [(set GR16:$dst, (add GR16:$src, -1)), |
| 1384 | (implicit EFLAGS)]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1385 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1386 | def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1387 | [(set GR32:$dst, (add GR32:$src, -1)), |
| 1388 | (implicit EFLAGS)]>, Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1389 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1390 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1391 | let isTwoAddress = 0, CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1392 | def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1393 | [(store (add (loadi8 addr:$dst), -1), addr:$dst), |
| 1394 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1395 | def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1396 | [(store (add (loadi16 addr:$dst), -1), addr:$dst), |
| 1397 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1398 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1399 | def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1400 | [(store (add (loadi32 addr:$dst), -1), addr:$dst), |
| 1401 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1402 | Requires<[In32BitMode]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1403 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1404 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1405 | |
| 1406 | // Logical operators... |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1407 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1408 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1409 | def AND8rr : I<0x20, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1410 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1411 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1412 | [(set GR8:$dst, (and GR8:$src1, GR8:$src2)), |
| 1413 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1414 | def AND16rr : I<0x21, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1415 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1416 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1417 | [(set GR16:$dst, (and GR16:$src1, GR16:$src2)), |
| 1418 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1419 | def AND32rr : I<0x21, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1420 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1421 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1422 | [(set GR32:$dst, (and GR32:$src1, GR32:$src2)), |
| 1423 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1424 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1425 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1426 | def AND8rm : I<0x22, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1427 | (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1428 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1429 | [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1430 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1431 | def AND16rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1432 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1433 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1434 | [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1435 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1436 | def AND32rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1437 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1438 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1439 | [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1440 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1441 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1442 | def AND8ri : Ii8<0x80, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1443 | (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1444 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1445 | [(set GR8:$dst, (and GR8:$src1, imm:$src2)), |
| 1446 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1447 | def AND16ri : Ii16<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1448 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1449 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1450 | [(set GR16:$dst, (and GR16:$src1, imm:$src2)), |
| 1451 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1452 | def AND32ri : Ii32<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1453 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1454 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1455 | [(set GR32:$dst, (and GR32:$src1, imm:$src2)), |
| 1456 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1457 | def AND16ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1458 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1459 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1460 | [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)), |
| 1461 | (implicit EFLAGS)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1462 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1463 | def AND32ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1464 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1465 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1466 | [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)), |
| 1467 | (implicit EFLAGS)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1468 | |
| 1469 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1470 | def AND8mr : I<0x20, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1471 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1472 | "and{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1473 | [(store (and (load addr:$dst), GR8:$src), addr:$dst), |
| 1474 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1475 | def AND16mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1476 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1477 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1478 | [(store (and (load addr:$dst), GR16:$src), addr:$dst), |
| 1479 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1480 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1481 | def AND32mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1482 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1483 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1484 | [(store (and (load addr:$dst), GR32:$src), addr:$dst), |
| 1485 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1486 | def AND8mi : Ii8<0x80, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1487 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1488 | "and{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1489 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1490 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1491 | def AND16mi : Ii16<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1492 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1493 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1494 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1495 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1496 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1497 | def AND32mi : Ii32<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1498 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1499 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1500 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1501 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1502 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1503 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1504 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1505 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1506 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1507 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1508 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1509 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1510 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1511 | [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1512 | (implicit EFLAGS)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1513 | } |
| 1514 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1515 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1516 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1517 | def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1518 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1519 | [(set GR8:$dst, (or GR8:$src1, GR8:$src2)), |
| 1520 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1521 | def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1522 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1523 | [(set GR16:$dst, (or GR16:$src1, GR16:$src2)), |
| 1524 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1525 | def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1526 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1527 | [(set GR32:$dst, (or GR32:$src1, GR32:$src2)), |
| 1528 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1529 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1530 | def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1531 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1532 | [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))), |
| 1533 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1534 | def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1535 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1536 | [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))), |
| 1537 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1538 | def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1539 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1540 | [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))), |
| 1541 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1542 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1543 | def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1544 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1545 | [(set GR8:$dst, (or GR8:$src1, imm:$src2)), |
| 1546 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1547 | def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1548 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1549 | [(set GR16:$dst, (or GR16:$src1, imm:$src2)), |
| 1550 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1551 | def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1552 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1553 | [(set GR32:$dst, (or GR32:$src1, imm:$src2)), |
| 1554 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1555 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1556 | def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1557 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1558 | [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)), |
| 1559 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1560 | def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1561 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1562 | [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)), |
| 1563 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1564 | let isTwoAddress = 0 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1565 | def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1566 | "or{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1567 | [(store (or (load addr:$dst), GR8:$src), addr:$dst), |
| 1568 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1569 | def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1570 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1571 | [(store (or (load addr:$dst), GR16:$src), addr:$dst), |
| 1572 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1573 | def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1574 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1575 | [(store (or (load addr:$dst), GR32:$src), addr:$dst), |
| 1576 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1577 | def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1578 | "or{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1579 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1580 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1581 | def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1582 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1583 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1584 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1585 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1586 | def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1587 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1588 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1589 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1590 | def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1591 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1592 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1593 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1594 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1595 | def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1596 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1597 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1598 | (implicit EFLAGS)]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1599 | } // isTwoAddress = 0 |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1600 | |
| 1601 | |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1602 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1603 | def XOR8rr : I<0x30, MRMDestReg, |
| 1604 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
| 1605 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1606 | [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)), |
| 1607 | (implicit EFLAGS)]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1608 | def XOR16rr : I<0x31, MRMDestReg, |
| 1609 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1610 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1611 | [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)), |
| 1612 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1613 | def XOR32rr : I<0x31, MRMDestReg, |
| 1614 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1615 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1616 | [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)), |
| 1617 | (implicit EFLAGS)]>; |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1618 | } // isCommutable = 1 |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1619 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1620 | def XOR8rm : I<0x32, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1621 | (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1622 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1623 | [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))), |
| 1624 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1625 | def XOR16rm : I<0x33, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1626 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1627 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1628 | [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))), |
| 1629 | (implicit EFLAGS)]>, |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1630 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1631 | def XOR32rm : I<0x33, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1632 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1633 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1634 | [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))), |
| 1635 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1636 | |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1637 | def XOR8ri : Ii8<0x80, MRM6r, |
| 1638 | (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 1639 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1640 | [(set GR8:$dst, (xor GR8:$src1, imm:$src2)), |
| 1641 | (implicit EFLAGS)]>; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1642 | def XOR16ri : Ii16<0x81, MRM6r, |
| 1643 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
| 1644 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1645 | [(set GR16:$dst, (xor GR16:$src1, imm:$src2)), |
| 1646 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1647 | def XOR32ri : Ii32<0x81, MRM6r, |
| 1648 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
| 1649 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1650 | [(set GR32:$dst, (xor GR32:$src1, imm:$src2)), |
| 1651 | (implicit EFLAGS)]>; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1652 | def XOR16ri8 : Ii8<0x83, MRM6r, |
| 1653 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
| 1654 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1655 | [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)), |
| 1656 | (implicit EFLAGS)]>, |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1657 | OpSize; |
| 1658 | def XOR32ri8 : Ii8<0x83, MRM6r, |
| 1659 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
| 1660 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1661 | [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)), |
| 1662 | (implicit EFLAGS)]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1663 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1664 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1665 | def XOR8mr : I<0x30, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1666 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1667 | "xor{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1668 | [(store (xor (load addr:$dst), GR8:$src), addr:$dst), |
| 1669 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1670 | def XOR16mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1671 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1672 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1673 | [(store (xor (load addr:$dst), GR16:$src), addr:$dst), |
| 1674 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1675 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1676 | def XOR32mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1677 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1678 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1679 | [(store (xor (load addr:$dst), GR32:$src), addr:$dst), |
| 1680 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1681 | def XOR8mi : Ii8<0x80, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1682 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1683 | "xor{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1684 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1685 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1686 | def XOR16mi : Ii16<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1687 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1688 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1689 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1690 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1691 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1692 | def XOR32mi : Ii32<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1693 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1694 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1695 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1696 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1697 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1698 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1699 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1700 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1701 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1702 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1703 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1704 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1705 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1706 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1707 | (implicit EFLAGS)]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1708 | } // isTwoAddress = 0 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1709 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1710 | |
| 1711 | // Shift instructions |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1712 | let Defs = [EFLAGS] in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1713 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1714 | def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1715 | "shl{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1716 | [(set GR8:$dst, (shl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1717 | def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1718 | "shl{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1719 | [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1720 | def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1721 | "shl{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1722 | [(set GR32:$dst, (shl GR32:$src, CL))]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1723 | } // Uses = [CL] |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1724 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1725 | def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1726 | "shl{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1727 | [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1728 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1729 | def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1730 | "shl{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1731 | [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1732 | def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1733 | "shl{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1734 | [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f9b3f37 | 2008-01-11 18:00:50 +0000 | [diff] [blame] | 1735 | // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is |
| 1736 | // cheaper. |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1737 | } // isConvertibleToThreeAddress = 1 |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1738 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1739 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1740 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1741 | def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1742 | "shl{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1743 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1744 | def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1745 | "shl{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1746 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1747 | def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1748 | "shl{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1749 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1750 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1751 | def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1752 | "shl{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1753 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1754 | def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1755 | "shl{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1756 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1757 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1758 | def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1759 | "shl{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1760 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1761 | |
| 1762 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1763 | def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1764 | "shl{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1765 | [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1766 | def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1767 | "shl{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1768 | [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1769 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1770 | def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1771 | "shl{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1772 | [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1773 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1774 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1775 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1776 | def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1777 | "shr{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1778 | [(set GR8:$dst, (srl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1779 | def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1780 | "shr{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1781 | [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1782 | def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1783 | "shr{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1784 | [(set GR32:$dst, (srl GR32:$src, CL))]>; |
| 1785 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1786 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1787 | def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1788 | "shr{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1789 | [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1790 | def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1791 | "shr{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1792 | [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1793 | def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1794 | "shr{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1795 | [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1796 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1797 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1798 | def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1799 | "shr{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1800 | [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1801 | def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1802 | "shr{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1803 | [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1804 | def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1805 | "shr{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1806 | [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>; |
| 1807 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1808 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1809 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1810 | def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1811 | "shr{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1812 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1813 | def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1814 | "shr{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1815 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1816 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1817 | def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1818 | "shr{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1819 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1820 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1821 | def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1822 | "shr{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1823 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1824 | def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1825 | "shr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1826 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1827 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1828 | def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1829 | "shr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1830 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1831 | |
| 1832 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1833 | def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1834 | "shr{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1835 | [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1836 | def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1837 | "shr{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1838 | [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1839 | def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1840 | "shr{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1841 | [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1842 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1843 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1844 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1845 | def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1846 | "sar{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1847 | [(set GR8:$dst, (sra GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1848 | def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1849 | "sar{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1850 | [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1851 | def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1852 | "sar{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1853 | [(set GR32:$dst, (sra GR32:$src, CL))]>; |
| 1854 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1855 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1856 | def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1857 | "sar{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1858 | [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1859 | def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1860 | "sar{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1861 | [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1862 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1863 | def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1864 | "sar{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1865 | [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1866 | |
| 1867 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1868 | def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1869 | "sar{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1870 | [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1871 | def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1872 | "sar{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1873 | [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1874 | def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1875 | "sar{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1876 | [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>; |
| 1877 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1878 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1879 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1880 | def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1881 | "sar{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1882 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1883 | def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1884 | "sar{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1885 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1886 | def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1887 | "sar{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1888 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1889 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1890 | def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1891 | "sar{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1892 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1893 | def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1894 | "sar{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1895 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1896 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1897 | def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1898 | "sar{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1899 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1900 | |
| 1901 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1902 | def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1903 | "sar{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1904 | [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1905 | def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1906 | "sar{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1907 | [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1908 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1909 | def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1910 | "sar{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1911 | [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1912 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1913 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1914 | // Rotate instructions |
| 1915 | // FIXME: provide shorter instructions when imm8 == 1 |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1916 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1917 | def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1918 | "rol{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1919 | [(set GR8:$dst, (rotl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1920 | def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1921 | "rol{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1922 | [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1923 | def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1924 | "rol{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1925 | [(set GR32:$dst, (rotl GR32:$src, CL))]>; |
| 1926 | } |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1927 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1928 | def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1929 | "rol{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1930 | [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1931 | def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1932 | "rol{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1933 | [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1934 | def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1935 | "rol{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1936 | [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1937 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1938 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1939 | def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1940 | "rol{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1941 | [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1942 | def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1943 | "rol{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1944 | [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1945 | def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1946 | "rol{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1947 | [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>; |
| 1948 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1949 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1950 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1951 | def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1952 | "rol{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1953 | [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1954 | def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1955 | "rol{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1956 | [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1957 | def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1958 | "rol{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1959 | [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1960 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1961 | def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1962 | "rol{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1963 | [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1964 | def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1965 | "rol{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1966 | [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1967 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1968 | def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1969 | "rol{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1970 | [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1971 | |
| 1972 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1973 | def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1974 | "rol{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1975 | [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1976 | def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1977 | "rol{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1978 | [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1979 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1980 | def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1981 | "rol{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1982 | [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1983 | } |
| 1984 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1985 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1986 | def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1987 | "ror{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1988 | [(set GR8:$dst, (rotr GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1989 | def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1990 | "ror{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1991 | [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1992 | def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1993 | "ror{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1994 | [(set GR32:$dst, (rotr GR32:$src, CL))]>; |
| 1995 | } |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1996 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1997 | def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1998 | "ror{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1999 | [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2000 | def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2001 | "ror{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2002 | [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2003 | def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2004 | "ror{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2005 | [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2006 | |
| 2007 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2008 | def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2009 | "ror{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2010 | [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2011 | def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2012 | "ror{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2013 | [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2014 | def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2015 | "ror{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2016 | [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>; |
| 2017 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2018 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2019 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2020 | def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2021 | "ror{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2022 | [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2023 | def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2024 | "ror{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2025 | [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2026 | def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2027 | "ror{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2028 | [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2029 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2030 | def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2031 | "ror{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2032 | [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2033 | def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2034 | "ror{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2035 | [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2036 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2037 | def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2038 | "ror{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2039 | [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2040 | |
| 2041 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2042 | def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2043 | "ror{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2044 | [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2045 | def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2046 | "ror{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2047 | [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 2048 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2049 | def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2050 | "ror{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2051 | [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2052 | } |
| 2053 | |
| 2054 | |
| 2055 | |
| 2056 | // Double shift instructions (generalizations of rotate) |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2057 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2058 | def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2059 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2060 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2061 | def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2062 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2063 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2064 | def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2065 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2066 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2067 | TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2068 | def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2069 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2070 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2071 | TB, OpSize; |
| 2072 | } |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 2073 | |
| 2074 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2075 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2076 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2077 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2078 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2079 | (i8 imm:$src3)))]>, |
| 2080 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2081 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2082 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2083 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2084 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2085 | (i8 imm:$src3)))]>, |
| 2086 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2087 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2088 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2089 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2090 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2091 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2092 | TB, OpSize; |
| 2093 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2094 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2095 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2096 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2097 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2098 | TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 2099 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 2100 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2101 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2102 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2103 | def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2104 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2105 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2106 | addr:$dst)]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2107 | def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2108 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2109 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2110 | addr:$dst)]>, TB; |
| 2111 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2112 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2113 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2114 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2115 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2116 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 2117 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2118 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2119 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2120 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2121 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2122 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 2123 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2124 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2125 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2126 | def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2127 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2128 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2129 | addr:$dst)]>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2130 | def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2131 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2132 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2133 | addr:$dst)]>, TB, OpSize; |
| 2134 | } |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2135 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2136 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2137 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2138 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2139 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2140 | TB, OpSize; |
| 2141 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2142 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2143 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2144 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2145 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2146 | TB, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2147 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2148 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2149 | |
| 2150 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2151 | // Arithmetic. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2152 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2153 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2154 | // Register-Register Addition |
| 2155 | def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst), |
| 2156 | (ins GR8 :$src1, GR8 :$src2), |
| 2157 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2158 | [(set GR8:$dst, (add GR8:$src1, GR8:$src2)), |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2159 | (implicit EFLAGS)]>; |
| 2160 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2161 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2162 | // Register-Register Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2163 | def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst), |
| 2164 | (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2165 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2166 | [(set GR16:$dst, (add GR16:$src1, GR16:$src2)), |
| 2167 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2168 | def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), |
| 2169 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2170 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2171 | [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), |
| 2172 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2173 | } // end isConvertibleToThreeAddress |
| 2174 | } // end isCommutable |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2175 | |
| 2176 | // Register-Memory Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2177 | def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), |
| 2178 | (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2179 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2180 | [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))), |
| 2181 | (implicit EFLAGS)]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2182 | def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), |
| 2183 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2184 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2185 | [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))), |
| 2186 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2187 | def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), |
| 2188 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2189 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2190 | [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))), |
| 2191 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2192 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2193 | // Register-Integer Addition |
| 2194 | def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 2195 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2196 | [(set GR8:$dst, (add GR8:$src1, imm:$src2)), |
| 2197 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2198 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2199 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2200 | // Register-Integer Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2201 | def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst), |
| 2202 | (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2203 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2204 | [(set GR16:$dst, (add GR16:$src1, imm:$src2)), |
| 2205 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2206 | def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), |
| 2207 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2208 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2209 | [(set GR32:$dst, (add GR32:$src1, imm:$src2)), |
| 2210 | (implicit EFLAGS)]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2211 | def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst), |
| 2212 | (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2213 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2214 | [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)), |
| 2215 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2216 | def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst), |
| 2217 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2218 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2219 | [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)), |
| 2220 | (implicit EFLAGS)]>; |
Evan Cheng | 09e3c80 | 2006-05-19 18:40:54 +0000 | [diff] [blame] | 2221 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2222 | |
| 2223 | let isTwoAddress = 0 in { |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2224 | // Memory-Register Addition |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2225 | def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2226 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2227 | [(store (add (load addr:$dst), GR8:$src2), addr:$dst), |
| 2228 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2229 | def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2230 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2231 | [(store (add (load addr:$dst), GR16:$src2), addr:$dst), |
| 2232 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2233 | def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2234 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2235 | [(store (add (load addr:$dst), GR32:$src2), addr:$dst), |
| 2236 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2237 | def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2238 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2239 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 2240 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2241 | def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2242 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2243 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst), |
| 2244 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2245 | def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2246 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2247 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst), |
| 2248 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2249 | def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2250 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2251 | [(store (add (load addr:$dst), i16immSExt8:$src2), |
| 2252 | addr:$dst), |
| 2253 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2254 | def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2255 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2256 | [(store (add (load addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2257 | addr:$dst), |
| 2258 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2259 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2260 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2261 | let Uses = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2262 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2263 | def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2264 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2265 | [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2266 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2267 | def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2268 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2269 | [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2270 | def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2271 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2272 | [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2273 | def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2274 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2275 | [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2276 | |
| 2277 | let isTwoAddress = 0 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2278 | def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2279 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2280 | [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2281 | def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2282 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2283 | [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2284 | def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2285 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2286 | [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2287 | } |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2288 | } // Uses = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2289 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2290 | // Register-Register Subtraction |
| 2291 | def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2292 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2293 | [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)), |
| 2294 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2295 | def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
| 2296 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2297 | [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)), |
| 2298 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2299 | def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
| 2300 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2301 | [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)), |
| 2302 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2303 | |
| 2304 | // Register-Memory Subtraction |
| 2305 | def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), |
| 2306 | (ins GR8 :$src1, i8mem :$src2), |
| 2307 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2308 | [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))), |
| 2309 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2310 | def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), |
| 2311 | (ins GR16:$src1, i16mem:$src2), |
| 2312 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2313 | [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))), |
| 2314 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2315 | def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), |
| 2316 | (ins GR32:$src1, i32mem:$src2), |
| 2317 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2318 | [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))), |
| 2319 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2320 | |
| 2321 | // Register-Integer Subtraction |
| 2322 | def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), |
| 2323 | (ins GR8:$src1, i8imm:$src2), |
| 2324 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2325 | [(set GR8:$dst, (sub GR8:$src1, imm:$src2)), |
| 2326 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2327 | def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), |
| 2328 | (ins GR16:$src1, i16imm:$src2), |
| 2329 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2330 | [(set GR16:$dst, (sub GR16:$src1, imm:$src2)), |
| 2331 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2332 | def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), |
| 2333 | (ins GR32:$src1, i32imm:$src2), |
| 2334 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2335 | [(set GR32:$dst, (sub GR32:$src1, imm:$src2)), |
| 2336 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2337 | def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), |
| 2338 | (ins GR16:$src1, i16i8imm:$src2), |
| 2339 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2340 | [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)), |
| 2341 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2342 | def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), |
| 2343 | (ins GR32:$src1, i32i8imm:$src2), |
| 2344 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2345 | [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)), |
| 2346 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2347 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2348 | let isTwoAddress = 0 in { |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2349 | // Memory-Register Subtraction |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2350 | def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2351 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2352 | [(store (sub (load addr:$dst), GR8:$src2), addr:$dst), |
| 2353 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2354 | def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2355 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2356 | [(store (sub (load addr:$dst), GR16:$src2), addr:$dst), |
| 2357 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2358 | def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2359 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2360 | [(store (sub (load addr:$dst), GR32:$src2), addr:$dst), |
| 2361 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2362 | |
| 2363 | // Memory-Integer Subtraction |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2364 | def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2365 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2366 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 2367 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2368 | def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2369 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2370 | [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst), |
| 2371 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2372 | def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2373 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2374 | [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst), |
| 2375 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2376 | def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2377 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2378 | [(store (sub (load addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2379 | addr:$dst), |
| 2380 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2381 | def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2382 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2383 | [(store (sub (load addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2384 | addr:$dst), |
| 2385 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2386 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2387 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2388 | let Uses = [EFLAGS] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2389 | def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2390 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2391 | [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 2392 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2393 | let isTwoAddress = 0 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2394 | def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2395 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2396 | [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2397 | def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2398 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2399 | [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2400 | def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2401 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2402 | [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2403 | def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2404 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2405 | [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2406 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2407 | def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2408 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2409 | [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2410 | def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2411 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2412 | [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2413 | def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2414 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2415 | [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2416 | } // Uses = [EFLAGS] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2417 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2418 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2419 | let Defs = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2420 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2421 | // Register-Register Signed Integer Multiply |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2422 | def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2423 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2424 | [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)), |
| 2425 | (implicit EFLAGS)]>, TB, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2426 | def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2427 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2428 | [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)), |
| 2429 | (implicit EFLAGS)]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2430 | } |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2431 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2432 | // Register-Memory Signed Integer Multiply |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2433 | def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), |
| 2434 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2435 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2436 | [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))), |
| 2437 | (implicit EFLAGS)]>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2438 | def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2439 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2440 | [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))), |
| 2441 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2442 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2443 | } // end Two Address instructions |
| 2444 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2445 | // Suprisingly enough, these are not two address instructions! |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2446 | let Defs = [EFLAGS] in { |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2447 | // Register-Integer Signed Integer Multiply |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2448 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2449 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2450 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2451 | [(set GR16:$dst, (mul GR16:$src1, imm:$src2)), |
| 2452 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2453 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2454 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2455 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2456 | [(set GR32:$dst, (mul GR32:$src1, imm:$src2)), |
| 2457 | (implicit EFLAGS)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2458 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2459 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2460 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2461 | [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)), |
| 2462 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2463 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2464 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2465 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2466 | [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)), |
| 2467 | (implicit EFLAGS)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2468 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2469 | // Memory-Integer Signed Integer Multiply |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2470 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2471 | (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2472 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2473 | [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)), |
| 2474 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2475 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2476 | (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2477 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2478 | [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)), |
| 2479 | (implicit EFLAGS)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2480 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2481 | (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2482 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2483 | [(set GR16:$dst, (mul (load addr:$src1), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2484 | i16immSExt8:$src2)), |
| 2485 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2486 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2487 | (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2488 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2489 | [(set GR32:$dst, (mul (load addr:$src1), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2490 | i32immSExt8:$src2)), |
| 2491 | (implicit EFLAGS)]>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2492 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2493 | |
| 2494 | //===----------------------------------------------------------------------===// |
| 2495 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2496 | // |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2497 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2498 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2499 | def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2500 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2501 | [(X86cmp (and_su GR8:$src1, GR8:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2502 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2503 | def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2504 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2505 | [(X86cmp (and_su GR16:$src1, GR16:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2506 | (implicit EFLAGS)]>, |
| 2507 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2508 | def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2509 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2510 | [(X86cmp (and_su GR32:$src1, GR32:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2511 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2512 | } |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2513 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2514 | def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2515 | "test{b}\t{$src2, $src1|$src1, $src2}", |
| 2516 | [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0), |
| 2517 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2518 | def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2519 | "test{w}\t{$src2, $src1|$src1, $src2}", |
| 2520 | [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0), |
| 2521 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2522 | def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2523 | "test{l}\t{$src2, $src1|$src1, $src2}", |
| 2524 | [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0), |
| 2525 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2526 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2527 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2528 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2529 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2530 | [(X86cmp (and_su GR8:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2531 | (implicit EFLAGS)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2532 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2533 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2534 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2535 | [(X86cmp (and_su GR16:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2536 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2537 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2538 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2539 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2540 | [(X86cmp (and_su GR32:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2541 | (implicit EFLAGS)]>; |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2542 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2543 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2544 | (outs), (ins i8mem:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2545 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2546 | [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0), |
| 2547 | (implicit EFLAGS)]>; |
| 2548 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2549 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2550 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2551 | [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0), |
| 2552 | (implicit EFLAGS)]>, OpSize; |
| 2553 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2554 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2555 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2556 | [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2557 | (implicit EFLAGS)]>; |
| 2558 | } // Defs = [EFLAGS] |
| 2559 | |
| 2560 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2561 | // Condition code ops, incl. set if equal/not equal/... |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2562 | let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2563 | def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2564 | let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2565 | def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2566 | |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2567 | let Uses = [EFLAGS] in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2568 | def SETEr : I<0x94, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2569 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2570 | "sete\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2571 | [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2572 | TB; // GR8 = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2573 | def SETEm : I<0x94, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2574 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2575 | "sete\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2576 | [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2577 | TB; // [mem8] = == |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2578 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2579 | def SETNEr : I<0x95, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2580 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2581 | "setne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2582 | [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2583 | TB; // GR8 = != |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2584 | def SETNEm : I<0x95, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2585 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2586 | "setne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2587 | [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2588 | TB; // [mem8] = != |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2589 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2590 | def SETLr : I<0x9C, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2591 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2592 | "setl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2593 | [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2594 | TB; // GR8 = < signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2595 | def SETLm : I<0x9C, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2596 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2597 | "setl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2598 | [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2599 | TB; // [mem8] = < signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2600 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2601 | def SETGEr : I<0x9D, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2602 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2603 | "setge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2604 | [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2605 | TB; // GR8 = >= signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2606 | def SETGEm : I<0x9D, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2607 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2608 | "setge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2609 | [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2610 | TB; // [mem8] = >= signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2611 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2612 | def SETLEr : I<0x9E, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2613 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2614 | "setle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2615 | [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2616 | TB; // GR8 = <= signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2617 | def SETLEm : I<0x9E, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2618 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2619 | "setle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2620 | [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2621 | TB; // [mem8] = <= signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2622 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2623 | def SETGr : I<0x9F, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2624 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2625 | "setg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2626 | [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2627 | TB; // GR8 = > signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2628 | def SETGm : I<0x9F, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2629 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2630 | "setg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2631 | [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2632 | TB; // [mem8] = > signed |
| 2633 | |
| 2634 | def SETBr : I<0x92, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2635 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2636 | "setb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2637 | [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2638 | TB; // GR8 = < unsign |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2639 | def SETBm : I<0x92, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2640 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2641 | "setb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2642 | [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2643 | TB; // [mem8] = < unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2644 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2645 | def SETAEr : I<0x93, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2646 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2647 | "setae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2648 | [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2649 | TB; // GR8 = >= unsign |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2650 | def SETAEm : I<0x93, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2651 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2652 | "setae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2653 | [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2654 | TB; // [mem8] = >= unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2655 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2656 | def SETBEr : I<0x96, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2657 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2658 | "setbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2659 | [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2660 | TB; // GR8 = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2661 | def SETBEm : I<0x96, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2662 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2663 | "setbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2664 | [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2665 | TB; // [mem8] = <= unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2666 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2667 | def SETAr : I<0x97, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2668 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2669 | "seta\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2670 | [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2671 | TB; // GR8 = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2672 | def SETAm : I<0x97, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2673 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2674 | "seta\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2675 | [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2676 | TB; // [mem8] = > signed |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2677 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2678 | def SETSr : I<0x98, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2679 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2680 | "sets\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2681 | [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2682 | TB; // GR8 = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2683 | def SETSm : I<0x98, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2684 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2685 | "sets\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2686 | [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2687 | TB; // [mem8] = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2688 | def SETNSr : I<0x99, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2689 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2690 | "setns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2691 | [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2692 | TB; // GR8 = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2693 | def SETNSm : I<0x99, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2694 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2695 | "setns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2696 | [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2697 | TB; // [mem8] = !<sign bit> |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2698 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2699 | def SETPr : I<0x9A, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2700 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2701 | "setp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2702 | [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2703 | TB; // GR8 = parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2704 | def SETPm : I<0x9A, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2705 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2706 | "setp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2707 | [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2708 | TB; // [mem8] = parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2709 | def SETNPr : I<0x9B, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2710 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2711 | "setnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2712 | [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2713 | TB; // GR8 = not parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2714 | def SETNPm : I<0x9B, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2715 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2716 | "setnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2717 | [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2718 | TB; // [mem8] = not parity |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2719 | |
| 2720 | def SETOr : I<0x90, MRM0r, |
| 2721 | (outs GR8 :$dst), (ins), |
| 2722 | "seto\t$dst", |
| 2723 | [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>, |
| 2724 | TB; // GR8 = overflow |
| 2725 | def SETOm : I<0x90, MRM0m, |
| 2726 | (outs), (ins i8mem:$dst), |
| 2727 | "seto\t$dst", |
| 2728 | [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>, |
| 2729 | TB; // [mem8] = overflow |
| 2730 | def SETNOr : I<0x91, MRM0r, |
| 2731 | (outs GR8 :$dst), (ins), |
| 2732 | "setno\t$dst", |
| 2733 | [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>, |
| 2734 | TB; // GR8 = not overflow |
| 2735 | def SETNOm : I<0x91, MRM0m, |
| 2736 | (outs), (ins i8mem:$dst), |
| 2737 | "setno\t$dst", |
| 2738 | [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>, |
| 2739 | TB; // [mem8] = not overflow |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2740 | } // Uses = [EFLAGS] |
| 2741 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2742 | |
| 2743 | // Integer comparisons |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2744 | let Defs = [EFLAGS] in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2745 | def CMP8rr : I<0x38, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2746 | (outs), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2747 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2748 | [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2749 | def CMP16rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2750 | (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2751 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2752 | [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2753 | def CMP32rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2754 | (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2755 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2756 | [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2757 | def CMP8mr : I<0x38, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2758 | (outs), (ins i8mem :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2759 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2760 | [(X86cmp (loadi8 addr:$src1), GR8:$src2), |
| 2761 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2762 | def CMP16mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2763 | (outs), (ins i16mem:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2764 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2765 | [(X86cmp (loadi16 addr:$src1), GR16:$src2), |
| 2766 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2767 | def CMP32mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2768 | (outs), (ins i32mem:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2769 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2770 | [(X86cmp (loadi32 addr:$src1), GR32:$src2), |
| 2771 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2772 | def CMP8rm : I<0x3A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2773 | (outs), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2774 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2775 | [(X86cmp GR8:$src1, (loadi8 addr:$src2)), |
| 2776 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2777 | def CMP16rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2778 | (outs), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2779 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2780 | [(X86cmp GR16:$src1, (loadi16 addr:$src2)), |
| 2781 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2782 | def CMP32rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2783 | (outs), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2784 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2785 | [(X86cmp GR32:$src1, (loadi32 addr:$src2)), |
| 2786 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2787 | def CMP8ri : Ii8<0x80, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2788 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2789 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2790 | [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2791 | def CMP16ri : Ii16<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2792 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2793 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2794 | [(X86cmp GR16:$src1, imm:$src2), |
| 2795 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2796 | def CMP32ri : Ii32<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2797 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2798 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2799 | [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2800 | def CMP8mi : Ii8 <0x80, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2801 | (outs), (ins i8mem :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2802 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2803 | [(X86cmp (loadi8 addr:$src1), imm:$src2), |
| 2804 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2805 | def CMP16mi : Ii16<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2806 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2807 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2808 | [(X86cmp (loadi16 addr:$src1), imm:$src2), |
| 2809 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2810 | def CMP32mi : Ii32<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2811 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2812 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2813 | [(X86cmp (loadi32 addr:$src1), imm:$src2), |
| 2814 | (implicit EFLAGS)]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2815 | def CMP16ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2816 | (outs), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2817 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2818 | [(X86cmp GR16:$src1, i16immSExt8:$src2), |
| 2819 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2820 | def CMP16mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2821 | (outs), (ins i16mem:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2822 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2823 | [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2), |
| 2824 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2825 | def CMP32mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2826 | (outs), (ins i32mem:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2827 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2828 | [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2), |
| 2829 | (implicit EFLAGS)]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2830 | def CMP32ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2831 | (outs), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2832 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2833 | [(X86cmp GR32:$src1, i32immSExt8:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2834 | (implicit EFLAGS)]>; |
| 2835 | } // Defs = [EFLAGS] |
| 2836 | |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2837 | // Bit tests. |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2838 | // TODO: BTC, BTR, and BTS |
| 2839 | let Defs = [EFLAGS] in { |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 2840 | def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2841 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 2842 | [(X86bt GR16:$src1, GR16:$src2), |
Chris Lattner | f1e9fd5 | 2008-12-25 01:32:49 +0000 | [diff] [blame] | 2843 | (implicit EFLAGS)]>, OpSize, TB; |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 2844 | def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2845 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 2846 | [(X86bt GR32:$src1, GR32:$src2), |
Chris Lattner | f1e9fd5 | 2008-12-25 01:32:49 +0000 | [diff] [blame] | 2847 | (implicit EFLAGS)]>, TB; |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 2848 | |
| 2849 | // Unlike with the register+register form, the memory+register form of the |
| 2850 | // bt instruction does not ignore the high bits of the index. From ISel's |
| 2851 | // perspective, this is pretty bizarre. Disable these instructions for now. |
| 2852 | //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 2853 | // "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 2854 | // [(X86bt (loadi16 addr:$src1), GR16:$src2), |
| 2855 | // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>; |
| 2856 | //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 2857 | // "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 2858 | // [(X86bt (loadi32 addr:$src1), GR32:$src2), |
| 2859 | // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 2860 | |
| 2861 | def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 2862 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 2863 | [(X86bt GR16:$src1, i16immSExt8:$src2), |
| 2864 | (implicit EFLAGS)]>, OpSize, TB; |
| 2865 | def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 2866 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 2867 | [(X86bt GR32:$src1, i32immSExt8:$src2), |
| 2868 | (implicit EFLAGS)]>, TB; |
| 2869 | // Note that these instructions don't need FastBTMem because that |
| 2870 | // only applies when the other operand is in a register. When it's |
| 2871 | // an immediate, bt is still fast. |
| 2872 | def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 2873 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 2874 | [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2), |
| 2875 | (implicit EFLAGS)]>, OpSize, TB; |
| 2876 | def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 2877 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 2878 | [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2), |
| 2879 | (implicit EFLAGS)]>, TB; |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2880 | } // Defs = [EFLAGS] |
| 2881 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2882 | // Sign/Zero extenders |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2883 | // Use movsbl intead of movsbw; we don't care about the high 16 bits |
| 2884 | // of the register here. This has a smaller encoding and avoids a |
| 2885 | // partial-register update. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2886 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2887 | "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 2888 | [(set GR16:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2889 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2890 | "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 2891 | [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2892 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2893 | "movs{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2894 | [(set GR32:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2895 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2896 | "movs{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2897 | [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2898 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2899 | "movs{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2900 | [(set GR32:$dst, (sext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2901 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2902 | "movs{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2903 | [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 2904 | |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2905 | // Use movzbl intead of movzbw; we don't care about the high 16 bits |
| 2906 | // of the register here. This has a smaller encoding and avoids a |
| 2907 | // partial-register update. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2908 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2909 | "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 2910 | [(set GR16:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2911 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2912 | "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 2913 | [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2914 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2915 | "movz{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2916 | [(set GR32:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2917 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2918 | "movz{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2919 | [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2920 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2921 | "movz{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2922 | [(set GR32:$dst, (zext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2923 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2924 | "movz{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2925 | [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2926 | |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 2927 | // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8 |
| 2928 | // except that they use GR32_NOREX for the output operand register class |
| 2929 | // instead of GR32. This allows them to operate on h registers on x86-64. |
| 2930 | def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg, |
| 2931 | (outs GR32_NOREX:$dst), (ins GR8:$src), |
| 2932 | "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX", |
| 2933 | []>, TB; |
| 2934 | def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem, |
| 2935 | (outs GR32_NOREX:$dst), (ins i8mem:$src), |
| 2936 | "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX", |
| 2937 | []>, TB; |
| 2938 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2939 | let neverHasSideEffects = 1 in { |
| 2940 | let Defs = [AX], Uses = [AL] in |
| 2941 | def CBW : I<0x98, RawFrm, (outs), (ins), |
| 2942 | "{cbtw|cbw}", []>, OpSize; // AX = signext(AL) |
| 2943 | let Defs = [EAX], Uses = [AX] in |
| 2944 | def CWDE : I<0x98, RawFrm, (outs), (ins), |
| 2945 | "{cwtl|cwde}", []>; // EAX = signext(AX) |
Evan Cheng | f91c101 | 2006-05-31 22:05:11 +0000 | [diff] [blame] | 2946 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2947 | let Defs = [AX,DX], Uses = [AX] in |
| 2948 | def CWD : I<0x99, RawFrm, (outs), (ins), |
| 2949 | "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX) |
| 2950 | let Defs = [EAX,EDX], Uses = [EAX] in |
| 2951 | def CDQ : I<0x99, RawFrm, (outs), (ins), |
| 2952 | "{cltd|cdq}", []>; // EDX:EAX = signext(EAX) |
| 2953 | } |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2954 | |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2955 | //===----------------------------------------------------------------------===// |
| 2956 | // Alias Instructions |
| 2957 | //===----------------------------------------------------------------------===// |
| 2958 | |
| 2959 | // Alias instructions that map movr0 to xor. |
| 2960 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok. |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 2961 | let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2962 | def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2963 | "xor{b}\t$dst, $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2964 | [(set GR8:$dst, 0)]>; |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2965 | // Use xorl instead of xorw since we don't care about the high 16 bits, |
| 2966 | // it's smaller, and it avoids a partial-register update. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2967 | def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2968 | "xor{l}\t${dst:subreg32}, ${dst:subreg32}", |
| 2969 | [(set GR16:$dst, 0)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2970 | def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2971 | "xor{l}\t$dst, $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2972 | [(set GR32:$dst, 0)]>; |
Dan Gohman | 1ab7989 | 2007-09-07 21:32:51 +0000 | [diff] [blame] | 2973 | } |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2974 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2975 | //===----------------------------------------------------------------------===// |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 2976 | // Thread Local Storage Instructions |
| 2977 | // |
| 2978 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2979 | let Uses = [EBX] in |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame] | 2980 | def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym), |
| 2981 | "leal\t${sym:mem}(,%ebx,1), $dst", |
| 2982 | [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 2983 | |
Nate Begeman | 51a0437 | 2009-01-26 01:24:32 +0000 | [diff] [blame] | 2984 | let AddedComplexity = 5 in |
| 2985 | def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 2986 | "movl\t%gs:$src, $dst", |
| 2987 | [(set GR32:$dst, (gsload addr:$src))]>, SegGS; |
| 2988 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 2989 | //===----------------------------------------------------------------------===// |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 2990 | // DWARF Pseudo Instructions |
| 2991 | // |
| 2992 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2993 | def DWARF_LOC : I<0, Pseudo, (outs), |
| 2994 | (ins i32imm:$line, i32imm:$col, i32imm:$file), |
Dan Gohman | 6b5766e | 2007-09-24 19:25:06 +0000 | [diff] [blame] | 2995 | ".loc\t${file:debug} ${line:debug} ${col:debug}", |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 2996 | [(dwarf_loc (i32 imm:$line), (i32 imm:$col), |
| 2997 | (i32 imm:$file))]>; |
| 2998 | |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 2999 | //===----------------------------------------------------------------------===// |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 3000 | // EH Pseudo Instructions |
| 3001 | // |
| 3002 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 3003 | hasCtrlDep = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3004 | def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3005 | "ret\t#eh_return, addr: $addr", |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 3006 | [(X86ehret GR32:$addr)]>; |
| 3007 | |
| 3008 | } |
| 3009 | |
| 3010 | //===----------------------------------------------------------------------===// |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 3011 | // Atomic support |
| 3012 | // |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3013 | |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 3014 | // Atomic swap. These are just normal xchg instructions. But since a memory |
| 3015 | // operand is referenced, the atomicity is ensured. |
Dan Gohman | 165660e | 2008-08-06 15:52:50 +0000 | [diff] [blame] | 3016 | let Constraints = "$val = $dst" in { |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 3017 | def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), |
| 3018 | "xchg{l}\t{$val, $ptr|$ptr, $val}", |
| 3019 | [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>; |
| 3020 | def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), |
| 3021 | "xchg{w}\t{$val, $ptr|$ptr, $val}", |
| 3022 | [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, |
| 3023 | OpSize; |
| 3024 | def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), |
| 3025 | "xchg{b}\t{$val, $ptr|$ptr, $val}", |
| 3026 | [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>; |
| 3027 | } |
| 3028 | |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3029 | // Atomic compare and swap. |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 3030 | let Defs = [EAX, EFLAGS], Uses = [EAX] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3031 | def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3032 | "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 3033 | [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3034 | } |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3035 | let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in { |
Anton Korobeynikov | f88a6fa | 2008-07-22 16:22:48 +0000 | [diff] [blame] | 3036 | def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3037 | "lock\n\tcmpxchg8b\t$ptr", |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 3038 | [(X86cas8 addr:$ptr)]>, TB, LOCK; |
| 3039 | } |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 3040 | |
| 3041 | let Defs = [AX, EFLAGS], Uses = [AX] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3042 | def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3043 | "lock\n\tcmpxchg{w}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 3044 | [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3045 | } |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 3046 | let Defs = [AL, EFLAGS], Uses = [AL] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3047 | def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3048 | "lock\n\tcmpxchg{b}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 3049 | [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3050 | } |
| 3051 | |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3052 | // Atomic exchange and add |
| 3053 | let Constraints = "$val = $dst", Defs = [EFLAGS] in { |
| 3054 | def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3055 | "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3056 | [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3057 | TB, LOCK; |
| 3058 | def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3059 | "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3060 | [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3061 | TB, OpSize, LOCK; |
| 3062 | def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3063 | "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3064 | [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3065 | TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3066 | } |
| 3067 | |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3068 | // Atomic exchange, and, or, xor |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 3069 | let Constraints = "$val = $dst", Defs = [EFLAGS], |
| 3070 | usesCustomDAGSchedInserter = 1 in { |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3071 | def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3072 | "#ATOMAND32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3073 | [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3074 | def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3075 | "#ATOMOR32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3076 | [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3077 | def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3078 | "#ATOMXOR32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3079 | [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>; |
Andrew Lenharth | 507a58a | 2008-06-14 05:48:15 +0000 | [diff] [blame] | 3080 | def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3081 | "#ATOMNAND32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3082 | [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3083 | def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3084 | "#ATOMMIN32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3085 | [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3086 | def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3087 | "#ATOMMAX32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3088 | [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3089 | def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3090 | "#ATOMUMIN32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3091 | [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3092 | def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3093 | "#ATOMUMAX32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3094 | [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3095 | |
| 3096 | def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3097 | "#ATOMAND16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3098 | [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3099 | def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3100 | "#ATOMOR16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3101 | [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3102 | def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3103 | "#ATOMXOR16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3104 | [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3105 | def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3106 | "#ATOMNAND16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3107 | [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3108 | def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3109 | "#ATOMMIN16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3110 | [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3111 | def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3112 | "#ATOMMAX16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3113 | [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3114 | def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3115 | "#ATOMUMIN16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3116 | [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3117 | def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3118 | "#ATOMUMAX16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3119 | [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3120 | |
| 3121 | def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3122 | "#ATOMAND8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3123 | [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3124 | def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3125 | "#ATOMOR8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3126 | [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3127 | def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3128 | "#ATOMXOR8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3129 | [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3130 | def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3131 | "#ATOMNAND8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3132 | [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>; |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 3133 | } |
| 3134 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3135 | let Constraints = "$val1 = $dst1, $val2 = $dst2", |
| 3136 | Defs = [EFLAGS, EAX, EBX, ECX, EDX], |
| 3137 | Uses = [EAX, EBX, ECX, EDX], |
Dale Johannesen | 1b54c7f | 2008-10-03 19:41:08 +0000 | [diff] [blame] | 3138 | mayLoad = 1, mayStore = 1, |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3139 | usesCustomDAGSchedInserter = 1 in { |
| 3140 | def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3141 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3142 | "#ATOMAND6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3143 | def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3144 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3145 | "#ATOMOR6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3146 | def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3147 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3148 | "#ATOMXOR6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3149 | def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3150 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3151 | "#ATOMNAND6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3152 | def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3153 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3154 | "#ATOMADD6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3155 | def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3156 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3157 | "#ATOMSUB6432 PSEUDO!", []>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 3158 | def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3159 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3160 | "#ATOMSWAP6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3161 | } |
| 3162 | |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 3163 | //===----------------------------------------------------------------------===// |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3164 | // Non-Instruction Patterns |
| 3165 | //===----------------------------------------------------------------------===// |
| 3166 | |
Bill Wendling | 056292f | 2008-09-16 21:48:12 +0000 | [diff] [blame] | 3167 | // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 3168 | def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 3169 | def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; |
Nate Begeman | 6795ebb | 2008-04-12 00:47:57 +0000 | [diff] [blame] | 3170 | def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 3171 | def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; |
| 3172 | def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; |
| 3173 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3174 | def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), |
| 3175 | (ADD32ri GR32:$src1, tconstpool:$src2)>; |
| 3176 | def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), |
| 3177 | (ADD32ri GR32:$src1, tjumptable:$src2)>; |
| 3178 | def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), |
| 3179 | (ADD32ri GR32:$src1, tglobaladdr:$src2)>; |
| 3180 | def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), |
| 3181 | (ADD32ri GR32:$src1, texternalsym:$src2)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 3182 | |
Evan Cheng | fc8feb1 | 2006-05-19 07:30:36 +0000 | [diff] [blame] | 3183 | def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 3184 | (MOV32mi addr:$dst, tglobaladdr:$src)>; |
Evan Cheng | fc8feb1 | 2006-05-19 07:30:36 +0000 | [diff] [blame] | 3185 | def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 3186 | (MOV32mi addr:$dst, texternalsym:$src)>; |
| 3187 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3188 | // Calls |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 3189 | // tailcall stuff |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3190 | def : Pat<(X86tailcall GR32:$dst), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 3191 | (TAILCALL)>; |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 3192 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 3193 | def : Pat<(X86tailcall (i32 tglobaladdr:$dst)), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 3194 | (TAILCALL)>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 3195 | def : Pat<(X86tailcall (i32 texternalsym:$dst)), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 3196 | (TAILCALL)>; |
| 3197 | |
| 3198 | def : Pat<(X86tcret GR32:$dst, imm:$off), |
| 3199 | (TCRETURNri GR32:$dst, imm:$off)>; |
| 3200 | |
| 3201 | def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), |
| 3202 | (TCRETURNdi texternalsym:$dst, imm:$off)>; |
| 3203 | |
| 3204 | def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), |
| 3205 | (TCRETURNdi texternalsym:$dst, imm:$off)>; |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 3206 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 3207 | def : Pat<(X86call (i32 tglobaladdr:$dst)), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3208 | (CALLpcrel32 tglobaladdr:$dst)>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 3209 | def : Pat<(X86call (i32 texternalsym:$dst)), |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 3210 | (CALLpcrel32 texternalsym:$dst)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3211 | |
| 3212 | // X86 specific add which produces a flag. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3213 | def : Pat<(addc GR32:$src1, GR32:$src2), |
| 3214 | (ADD32rr GR32:$src1, GR32:$src2)>; |
| 3215 | def : Pat<(addc GR32:$src1, (load addr:$src2)), |
| 3216 | (ADD32rm GR32:$src1, addr:$src2)>; |
| 3217 | def : Pat<(addc GR32:$src1, imm:$src2), |
| 3218 | (ADD32ri GR32:$src1, imm:$src2)>; |
| 3219 | def : Pat<(addc GR32:$src1, i32immSExt8:$src2), |
| 3220 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3221 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3222 | def : Pat<(subc GR32:$src1, GR32:$src2), |
| 3223 | (SUB32rr GR32:$src1, GR32:$src2)>; |
| 3224 | def : Pat<(subc GR32:$src1, (load addr:$src2)), |
| 3225 | (SUB32rm GR32:$src1, addr:$src2)>; |
| 3226 | def : Pat<(subc GR32:$src1, imm:$src2), |
| 3227 | (SUB32ri GR32:$src1, imm:$src2)>; |
| 3228 | def : Pat<(subc GR32:$src1, i32immSExt8:$src2), |
| 3229 | (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3230 | |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 3231 | // Comparisons. |
| 3232 | |
| 3233 | // TEST R,R is smaller than CMP R,0 |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3234 | def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 3235 | (TEST8rr GR8:$src1, GR8:$src1)>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3236 | def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 3237 | (TEST16rr GR16:$src1, GR16:$src1)>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3238 | def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 3239 | (TEST32rr GR32:$src1, GR32:$src1)>; |
| 3240 | |
Dan Gohman | fbb7486 | 2009-01-07 01:00:24 +0000 | [diff] [blame] | 3241 | // Conditional moves with folded loads with operands swapped and conditions |
| 3242 | // inverted. |
| 3243 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS), |
| 3244 | (CMOVAE16rm GR16:$src2, addr:$src1)>; |
| 3245 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS), |
| 3246 | (CMOVAE32rm GR32:$src2, addr:$src1)>; |
| 3247 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS), |
| 3248 | (CMOVB16rm GR16:$src2, addr:$src1)>; |
| 3249 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS), |
| 3250 | (CMOVB32rm GR32:$src2, addr:$src1)>; |
| 3251 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS), |
| 3252 | (CMOVNE16rm GR16:$src2, addr:$src1)>; |
| 3253 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS), |
| 3254 | (CMOVNE32rm GR32:$src2, addr:$src1)>; |
| 3255 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS), |
| 3256 | (CMOVE16rm GR16:$src2, addr:$src1)>; |
| 3257 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS), |
| 3258 | (CMOVE32rm GR32:$src2, addr:$src1)>; |
| 3259 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS), |
| 3260 | (CMOVA16rm GR16:$src2, addr:$src1)>; |
| 3261 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS), |
| 3262 | (CMOVA32rm GR32:$src2, addr:$src1)>; |
| 3263 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS), |
| 3264 | (CMOVBE16rm GR16:$src2, addr:$src1)>; |
| 3265 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS), |
| 3266 | (CMOVBE32rm GR32:$src2, addr:$src1)>; |
| 3267 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS), |
| 3268 | (CMOVGE16rm GR16:$src2, addr:$src1)>; |
| 3269 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS), |
| 3270 | (CMOVGE32rm GR32:$src2, addr:$src1)>; |
| 3271 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS), |
| 3272 | (CMOVL16rm GR16:$src2, addr:$src1)>; |
| 3273 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS), |
| 3274 | (CMOVL32rm GR32:$src2, addr:$src1)>; |
| 3275 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS), |
| 3276 | (CMOVG16rm GR16:$src2, addr:$src1)>; |
| 3277 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS), |
| 3278 | (CMOVG32rm GR32:$src2, addr:$src1)>; |
| 3279 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS), |
| 3280 | (CMOVLE16rm GR16:$src2, addr:$src1)>; |
| 3281 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS), |
| 3282 | (CMOVLE32rm GR32:$src2, addr:$src1)>; |
| 3283 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS), |
| 3284 | (CMOVNP16rm GR16:$src2, addr:$src1)>; |
| 3285 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS), |
| 3286 | (CMOVNP32rm GR32:$src2, addr:$src1)>; |
| 3287 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS), |
| 3288 | (CMOVP16rm GR16:$src2, addr:$src1)>; |
| 3289 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS), |
| 3290 | (CMOVP32rm GR32:$src2, addr:$src1)>; |
| 3291 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS), |
| 3292 | (CMOVNS16rm GR16:$src2, addr:$src1)>; |
| 3293 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS), |
| 3294 | (CMOVNS32rm GR32:$src2, addr:$src1)>; |
| 3295 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS), |
| 3296 | (CMOVS16rm GR16:$src2, addr:$src1)>; |
| 3297 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS), |
| 3298 | (CMOVS32rm GR32:$src2, addr:$src1)>; |
| 3299 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS), |
| 3300 | (CMOVNO16rm GR16:$src2, addr:$src1)>; |
| 3301 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS), |
| 3302 | (CMOVNO32rm GR32:$src2, addr:$src1)>; |
| 3303 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS), |
| 3304 | (CMOVO16rm GR16:$src2, addr:$src1)>; |
| 3305 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS), |
| 3306 | (CMOVO32rm GR32:$src2, addr:$src1)>; |
| 3307 | |
Duncan Sands | f9c98e6 | 2008-01-23 20:39:46 +0000 | [diff] [blame] | 3308 | // zextload bool -> zextload byte |
Evan Cheng | e5d9343 | 2006-01-17 07:02:46 +0000 | [diff] [blame] | 3309 | def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3310 | def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 3311 | def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 3312 | |
| 3313 | // extload bool -> extload byte |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 3314 | def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Bill Wendling | 449416d | 2008-08-22 20:51:05 +0000 | [diff] [blame] | 3315 | def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>, |
| 3316 | Requires<[In32BitMode]>; |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 3317 | def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
Bill Wendling | 449416d | 2008-08-22 20:51:05 +0000 | [diff] [blame] | 3318 | def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>, |
| 3319 | Requires<[In32BitMode]>; |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 3320 | def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 3321 | def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3322 | |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3323 | // anyext |
Bill Wendling | 449416d | 2008-08-22 20:51:05 +0000 | [diff] [blame] | 3324 | def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>, |
| 3325 | Requires<[In32BitMode]>; |
| 3326 | def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>, |
| 3327 | Requires<[In32BitMode]>; |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3328 | def : Pat<(i32 (anyext GR16:$src)), |
| 3329 | (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3330 | |
Evan Cheng | 1314b00 | 2007-12-13 00:43:27 +0000 | [diff] [blame] | 3331 | // (and (i32 load), 255) -> (zextload i8) |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 3332 | def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))), |
| 3333 | (MOVZX32rm8 addr:$src)>; |
| 3334 | def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))), |
| 3335 | (MOVZX32rm16 addr:$src)>; |
Evan Cheng | 1314b00 | 2007-12-13 00:43:27 +0000 | [diff] [blame] | 3336 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 3337 | //===----------------------------------------------------------------------===// |
| 3338 | // Some peepholes |
| 3339 | //===----------------------------------------------------------------------===// |
| 3340 | |
Dan Gohman | 63f9720 | 2008-10-17 01:33:43 +0000 | [diff] [blame] | 3341 | // Odd encoding trick: -128 fits into an 8-bit immediate field while |
| 3342 | // +128 doesn't, so in this special case use a sub instead of an add. |
| 3343 | def : Pat<(add GR16:$src1, 128), |
| 3344 | (SUB16ri8 GR16:$src1, -128)>; |
| 3345 | def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), |
| 3346 | (SUB16mi8 addr:$dst, -128)>; |
| 3347 | def : Pat<(add GR32:$src1, 128), |
| 3348 | (SUB32ri8 GR32:$src1, -128)>; |
| 3349 | def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), |
| 3350 | (SUB32mi8 addr:$dst, -128)>; |
| 3351 | |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3352 | // r & (2^16-1) ==> movz |
| 3353 | def : Pat<(and GR32:$src1, 0xffff), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3354 | (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>; |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 3355 | // r & (2^8-1) ==> movz |
| 3356 | def : Pat<(and GR32:$src1, 0xff), |
Dan Gohman | 88c7af0 | 2009-04-13 21:06:25 +0000 | [diff] [blame] | 3357 | (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3358 | x86_subreg_8bit))>, |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 3359 | Requires<[In32BitMode]>; |
| 3360 | // r & (2^8-1) ==> movz |
| 3361 | def : Pat<(and GR16:$src1, 0xff), |
Dan Gohman | 88c7af0 | 2009-04-13 21:06:25 +0000 | [diff] [blame] | 3362 | (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3363 | x86_subreg_8bit))>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3364 | Requires<[In32BitMode]>; |
| 3365 | |
| 3366 | // sext_inreg patterns |
| 3367 | def : Pat<(sext_inreg GR32:$src, i16), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3368 | (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>; |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3369 | def : Pat<(sext_inreg GR32:$src, i8), |
Dan Gohman | 88c7af0 | 2009-04-13 21:06:25 +0000 | [diff] [blame] | 3370 | (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3371 | x86_subreg_8bit))>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3372 | Requires<[In32BitMode]>; |
| 3373 | def : Pat<(sext_inreg GR16:$src, i8), |
Dan Gohman | 88c7af0 | 2009-04-13 21:06:25 +0000 | [diff] [blame] | 3374 | (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3375 | x86_subreg_8bit))>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3376 | Requires<[In32BitMode]>; |
| 3377 | |
| 3378 | // trunc patterns |
| 3379 | def : Pat<(i16 (trunc GR32:$src)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3380 | (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>; |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3381 | def : Pat<(i8 (trunc GR32:$src)), |
Dan Gohman | 88c7af0 | 2009-04-13 21:06:25 +0000 | [diff] [blame] | 3382 | (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3383 | x86_subreg_8bit)>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3384 | Requires<[In32BitMode]>; |
| 3385 | def : Pat<(i8 (trunc GR16:$src)), |
Dan Gohman | 88c7af0 | 2009-04-13 21:06:25 +0000 | [diff] [blame] | 3386 | (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3387 | x86_subreg_8bit)>, |
| 3388 | Requires<[In32BitMode]>; |
| 3389 | |
| 3390 | // h-register tricks |
| 3391 | def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), |
Dan Gohman | 88c7af0 | 2009-04-13 21:06:25 +0000 | [diff] [blame] | 3392 | (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3393 | x86_subreg_8bit_hi)>, |
| 3394 | Requires<[In32BitMode]>; |
| 3395 | def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), |
Dan Gohman | 88c7af0 | 2009-04-13 21:06:25 +0000 | [diff] [blame] | 3396 | (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3397 | x86_subreg_8bit_hi)>, |
| 3398 | Requires<[In32BitMode]>; |
| 3399 | def : Pat<(srl_su GR16:$src, (i8 8)), |
| 3400 | (EXTRACT_SUBREG |
| 3401 | (MOVZX32rr8 |
Dan Gohman | 88c7af0 | 2009-04-13 21:06:25 +0000 | [diff] [blame] | 3402 | (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3403 | x86_subreg_8bit_hi)), |
| 3404 | x86_subreg_16bit)>, |
| 3405 | Requires<[In32BitMode]>; |
| 3406 | def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), |
Dan Gohman | 88c7af0 | 2009-04-13 21:06:25 +0000 | [diff] [blame] | 3407 | (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3408 | x86_subreg_8bit_hi))>, |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 3409 | Requires<[In32BitMode]>; |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3410 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 3411 | // (shl x, 1) ==> (add x, x) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3412 | def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; |
| 3413 | def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; |
| 3414 | def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 3415 | |
Evan Cheng | eb9f892 | 2008-08-30 02:03:58 +0000 | [diff] [blame] | 3416 | // (shl x (and y, 31)) ==> (shl x, y) |
| 3417 | def : Pat<(shl GR8:$src1, (and CL:$amt, 31)), |
| 3418 | (SHL8rCL GR8:$src1)>; |
| 3419 | def : Pat<(shl GR16:$src1, (and CL:$amt, 31)), |
| 3420 | (SHL16rCL GR16:$src1)>; |
| 3421 | def : Pat<(shl GR32:$src1, (and CL:$amt, 31)), |
| 3422 | (SHL32rCL GR32:$src1)>; |
| 3423 | def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3424 | (SHL8mCL addr:$dst)>; |
| 3425 | def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3426 | (SHL16mCL addr:$dst)>; |
| 3427 | def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3428 | (SHL32mCL addr:$dst)>; |
| 3429 | |
| 3430 | def : Pat<(srl GR8:$src1, (and CL:$amt, 31)), |
| 3431 | (SHR8rCL GR8:$src1)>; |
| 3432 | def : Pat<(srl GR16:$src1, (and CL:$amt, 31)), |
| 3433 | (SHR16rCL GR16:$src1)>; |
| 3434 | def : Pat<(srl GR32:$src1, (and CL:$amt, 31)), |
| 3435 | (SHR32rCL GR32:$src1)>; |
| 3436 | def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3437 | (SHR8mCL addr:$dst)>; |
| 3438 | def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3439 | (SHR16mCL addr:$dst)>; |
| 3440 | def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3441 | (SHR32mCL addr:$dst)>; |
| 3442 | |
| 3443 | def : Pat<(sra GR8:$src1, (and CL:$amt, 31)), |
| 3444 | (SAR8rCL GR8:$src1)>; |
| 3445 | def : Pat<(sra GR16:$src1, (and CL:$amt, 31)), |
| 3446 | (SAR16rCL GR16:$src1)>; |
| 3447 | def : Pat<(sra GR32:$src1, (and CL:$amt, 31)), |
| 3448 | (SAR32rCL GR32:$src1)>; |
| 3449 | def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3450 | (SAR8mCL addr:$dst)>; |
| 3451 | def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3452 | (SAR16mCL addr:$dst)>; |
| 3453 | def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3454 | (SAR32mCL addr:$dst)>; |
| 3455 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3456 | // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3457 | def : Pat<(or (srl GR32:$src1, CL:$amt), |
| 3458 | (shl GR32:$src2, (sub 32, CL:$amt))), |
| 3459 | (SHRD32rrCL GR32:$src1, GR32:$src2)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 3460 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3461 | def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3462 | (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 3463 | (SHRD32mrCL addr:$dst, GR32:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3464 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 3465 | def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))), |
| 3466 | (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 3467 | (SHRD32rrCL GR32:$src1, GR32:$src2)>; |
| 3468 | |
| 3469 | def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))), |
| 3470 | (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 3471 | addr:$dst), |
| 3472 | (SHRD32mrCL addr:$dst, GR32:$src2)>; |
| 3473 | |
| 3474 | def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)), |
| 3475 | (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>; |
| 3476 | |
| 3477 | def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1), |
| 3478 | GR32:$src2, (i8 imm:$amt2)), addr:$dst), |
| 3479 | (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>; |
| 3480 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3481 | // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3482 | def : Pat<(or (shl GR32:$src1, CL:$amt), |
| 3483 | (srl GR32:$src2, (sub 32, CL:$amt))), |
| 3484 | (SHLD32rrCL GR32:$src1, GR32:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3485 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3486 | def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3487 | (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 3488 | (SHLD32mrCL addr:$dst, GR32:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3489 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 3490 | def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))), |
| 3491 | (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 3492 | (SHLD32rrCL GR32:$src1, GR32:$src2)>; |
| 3493 | |
| 3494 | def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))), |
| 3495 | (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 3496 | addr:$dst), |
| 3497 | (SHLD32mrCL addr:$dst, GR32:$src2)>; |
| 3498 | |
| 3499 | def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)), |
| 3500 | (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>; |
| 3501 | |
| 3502 | def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1), |
| 3503 | GR32:$src2, (i8 imm:$amt2)), addr:$dst), |
| 3504 | (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>; |
| 3505 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3506 | // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3507 | def : Pat<(or (srl GR16:$src1, CL:$amt), |
| 3508 | (shl GR16:$src2, (sub 16, CL:$amt))), |
| 3509 | (SHRD16rrCL GR16:$src1, GR16:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3510 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3511 | def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3512 | (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 3513 | (SHRD16mrCL addr:$dst, GR16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3514 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 3515 | def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))), |
| 3516 | (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 3517 | (SHRD16rrCL GR16:$src1, GR16:$src2)>; |
| 3518 | |
| 3519 | def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))), |
| 3520 | (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 3521 | addr:$dst), |
| 3522 | (SHRD16mrCL addr:$dst, GR16:$src2)>; |
| 3523 | |
| 3524 | def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)), |
| 3525 | (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>; |
| 3526 | |
| 3527 | def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1), |
| 3528 | GR16:$src2, (i8 imm:$amt2)), addr:$dst), |
| 3529 | (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>; |
| 3530 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3531 | // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3532 | def : Pat<(or (shl GR16:$src1, CL:$amt), |
| 3533 | (srl GR16:$src2, (sub 16, CL:$amt))), |
| 3534 | (SHLD16rrCL GR16:$src1, GR16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3535 | |
| 3536 | def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3537 | (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 3538 | (SHLD16mrCL addr:$dst, GR16:$src2)>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 3539 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 3540 | def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))), |
| 3541 | (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 3542 | (SHLD16rrCL GR16:$src1, GR16:$src2)>; |
| 3543 | |
| 3544 | def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))), |
| 3545 | (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 3546 | addr:$dst), |
| 3547 | (SHLD16mrCL addr:$dst, GR16:$src2)>; |
| 3548 | |
| 3549 | def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)), |
| 3550 | (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>; |
| 3551 | |
| 3552 | def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1), |
| 3553 | GR16:$src2, (i8 imm:$amt2)), addr:$dst), |
| 3554 | (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>; |
| 3555 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 3556 | //===----------------------------------------------------------------------===// |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3557 | // EFLAGS-defining Patterns |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3558 | //===----------------------------------------------------------------------===// |
| 3559 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3560 | // Register-Register Addition with EFLAGS result |
| 3561 | def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3562 | (implicit EFLAGS)), |
| 3563 | (ADD8rr GR8:$src1, GR8:$src2)>; |
| 3564 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3565 | // Register-Register Addition with EFLAGS result |
| 3566 | def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3567 | (implicit EFLAGS)), |
| 3568 | (ADD16rr GR16:$src1, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3569 | def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3570 | (implicit EFLAGS)), |
| 3571 | (ADD32rr GR32:$src1, GR32:$src2)>; |
| 3572 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3573 | // Register-Memory Addition with EFLAGS result |
| 3574 | def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3575 | (implicit EFLAGS)), |
| 3576 | (ADD8rm GR8:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3577 | def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3578 | (implicit EFLAGS)), |
| 3579 | (ADD16rm GR16:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3580 | def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3581 | (implicit EFLAGS)), |
| 3582 | (ADD32rm GR32:$src1, addr:$src2)>; |
| 3583 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3584 | // Register-Integer Addition with EFLAGS result |
| 3585 | def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3586 | (implicit EFLAGS)), |
| 3587 | (ADD8ri GR8:$src1, imm:$src2)>; |
| 3588 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3589 | // Register-Integer Addition with EFLAGS result |
| 3590 | def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3591 | (implicit EFLAGS)), |
| 3592 | (ADD16ri GR16:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3593 | def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3594 | (implicit EFLAGS)), |
| 3595 | (ADD32ri GR32:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3596 | def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3597 | (implicit EFLAGS)), |
| 3598 | (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3599 | def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3600 | (implicit EFLAGS)), |
| 3601 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 3602 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3603 | // Memory-Register Addition with EFLAGS result |
| 3604 | def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3605 | addr:$dst), |
| 3606 | (implicit EFLAGS)), |
| 3607 | (ADD8mr addr:$dst, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3608 | def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3609 | addr:$dst), |
| 3610 | (implicit EFLAGS)), |
| 3611 | (ADD16mr addr:$dst, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3612 | def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3613 | addr:$dst), |
| 3614 | (implicit EFLAGS)), |
| 3615 | (ADD32mr addr:$dst, GR32:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3616 | def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3617 | addr:$dst), |
| 3618 | (implicit EFLAGS)), |
| 3619 | (ADD8mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3620 | def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3621 | addr:$dst), |
| 3622 | (implicit EFLAGS)), |
| 3623 | (ADD16mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3624 | def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3625 | addr:$dst), |
| 3626 | (implicit EFLAGS)), |
| 3627 | (ADD32mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3628 | def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3629 | addr:$dst), |
| 3630 | (implicit EFLAGS)), |
| 3631 | (ADD16mi8 addr:$dst, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3632 | def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3633 | addr:$dst), |
| 3634 | (implicit EFLAGS)), |
| 3635 | (ADD32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 3636 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3637 | // Register-Register Subtraction with EFLAGS result |
| 3638 | def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3639 | (implicit EFLAGS)), |
| 3640 | (SUB8rr GR8:$src1, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3641 | def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3642 | (implicit EFLAGS)), |
| 3643 | (SUB16rr GR16:$src1, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3644 | def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3645 | (implicit EFLAGS)), |
| 3646 | (SUB32rr GR32:$src1, GR32:$src2)>; |
| 3647 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3648 | // Register-Memory Subtraction with EFLAGS result |
| 3649 | def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3650 | (implicit EFLAGS)), |
| 3651 | (SUB8rm GR8:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3652 | def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3653 | (implicit EFLAGS)), |
| 3654 | (SUB16rm GR16:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3655 | def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3656 | (implicit EFLAGS)), |
| 3657 | (SUB32rm GR32:$src1, addr:$src2)>; |
| 3658 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3659 | // Register-Integer Subtraction with EFLAGS result |
| 3660 | def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3661 | (implicit EFLAGS)), |
| 3662 | (SUB8ri GR8:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3663 | def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3664 | (implicit EFLAGS)), |
| 3665 | (SUB16ri GR16:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3666 | def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3667 | (implicit EFLAGS)), |
| 3668 | (SUB32ri GR32:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3669 | def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3670 | (implicit EFLAGS)), |
| 3671 | (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3672 | def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3673 | (implicit EFLAGS)), |
| 3674 | (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 3675 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3676 | // Memory-Register Subtraction with EFLAGS result |
| 3677 | def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3678 | addr:$dst), |
| 3679 | (implicit EFLAGS)), |
| 3680 | (SUB8mr addr:$dst, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3681 | def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3682 | addr:$dst), |
| 3683 | (implicit EFLAGS)), |
| 3684 | (SUB16mr addr:$dst, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3685 | def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3686 | addr:$dst), |
| 3687 | (implicit EFLAGS)), |
| 3688 | (SUB32mr addr:$dst, GR32:$src2)>; |
| 3689 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3690 | // Memory-Integer Subtraction with EFLAGS result |
| 3691 | def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3692 | addr:$dst), |
| 3693 | (implicit EFLAGS)), |
| 3694 | (SUB8mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3695 | def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3696 | addr:$dst), |
| 3697 | (implicit EFLAGS)), |
| 3698 | (SUB16mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3699 | def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3700 | addr:$dst), |
| 3701 | (implicit EFLAGS)), |
| 3702 | (SUB32mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3703 | def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3704 | addr:$dst), |
| 3705 | (implicit EFLAGS)), |
| 3706 | (SUB16mi8 addr:$dst, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3707 | def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3708 | addr:$dst), |
| 3709 | (implicit EFLAGS)), |
| 3710 | (SUB32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 3711 | |
| 3712 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3713 | // Register-Register Signed Integer Multiply with EFLAGS result |
| 3714 | def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3715 | (implicit EFLAGS)), |
| 3716 | (IMUL16rr GR16:$src1, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3717 | def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3718 | (implicit EFLAGS)), |
| 3719 | (IMUL32rr GR32:$src1, GR32:$src2)>; |
| 3720 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3721 | // Register-Memory Signed Integer Multiply with EFLAGS result |
| 3722 | def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3723 | (implicit EFLAGS)), |
| 3724 | (IMUL16rm GR16:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3725 | def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3726 | (implicit EFLAGS)), |
| 3727 | (IMUL32rm GR32:$src1, addr:$src2)>; |
| 3728 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3729 | // Register-Integer Signed Integer Multiply with EFLAGS result |
| 3730 | def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3731 | (implicit EFLAGS)), |
| 3732 | (IMUL16rri GR16:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3733 | def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3734 | (implicit EFLAGS)), |
| 3735 | (IMUL32rri GR32:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3736 | def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3737 | (implicit EFLAGS)), |
| 3738 | (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3739 | def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3740 | (implicit EFLAGS)), |
| 3741 | (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; |
| 3742 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3743 | // Memory-Integer Signed Integer Multiply with EFLAGS result |
| 3744 | def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3745 | (implicit EFLAGS)), |
| 3746 | (IMUL16rmi addr:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3747 | def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3748 | (implicit EFLAGS)), |
| 3749 | (IMUL32rmi addr:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3750 | def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3751 | (implicit EFLAGS)), |
| 3752 | (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3753 | def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3754 | (implicit EFLAGS)), |
| 3755 | (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; |
| 3756 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3757 | // Optimize multiply by 2 with EFLAGS result. |
Evan Cheng | 6a86bd7 | 2009-01-27 03:30:42 +0000 | [diff] [blame] | 3758 | let AddedComplexity = 2 in { |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3759 | def : Pat<(parallel (X86smul_flag GR16:$src1, 2), |
Evan Cheng | 6a86bd7 | 2009-01-27 03:30:42 +0000 | [diff] [blame] | 3760 | (implicit EFLAGS)), |
| 3761 | (ADD16rr GR16:$src1, GR16:$src1)>; |
| 3762 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3763 | def : Pat<(parallel (X86smul_flag GR32:$src1, 2), |
Evan Cheng | 6a86bd7 | 2009-01-27 03:30:42 +0000 | [diff] [blame] | 3764 | (implicit EFLAGS)), |
| 3765 | (ADD32rr GR32:$src1, GR32:$src1)>; |
| 3766 | } |
| 3767 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3768 | // INC and DEC with EFLAGS result. Note that these do not set CF. |
| 3769 | def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)), |
| 3770 | (INC8r GR8:$src)>; |
| 3771 | def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst), |
| 3772 | (implicit EFLAGS)), |
| 3773 | (INC8m addr:$dst)>; |
| 3774 | def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)), |
| 3775 | (DEC8r GR8:$src)>; |
| 3776 | def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst), |
| 3777 | (implicit EFLAGS)), |
| 3778 | (DEC8m addr:$dst)>; |
| 3779 | |
| 3780 | def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 3781 | (INC16r GR16:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3782 | def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst), |
| 3783 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 3784 | (INC16m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3785 | def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 3786 | (DEC16r GR16:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3787 | def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst), |
| 3788 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 3789 | (DEC16m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3790 | |
| 3791 | def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 3792 | (INC32r GR32:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3793 | def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst), |
| 3794 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 3795 | (INC32m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3796 | def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 3797 | (DEC32r GR32:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3798 | def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst), |
| 3799 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 3800 | (DEC32m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 3801 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 3802 | //===----------------------------------------------------------------------===// |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 3803 | // Floating Point Stack Support |
| 3804 | //===----------------------------------------------------------------------===// |
| 3805 | |
| 3806 | include "X86InstrFPStack.td" |
| 3807 | |
| 3808 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 3809 | // X86-64 Support |
| 3810 | //===----------------------------------------------------------------------===// |
| 3811 | |
Chris Lattner | 36fe6d2 | 2008-01-10 05:50:42 +0000 | [diff] [blame] | 3812 | include "X86Instr64bit.td" |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 3813 | |
| 3814 | //===----------------------------------------------------------------------===// |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 3815 | // XMM Floating point support (requires SSE / SSE2) |
| 3816 | //===----------------------------------------------------------------------===// |
| 3817 | |
| 3818 | include "X86InstrSSE.td" |
Evan Cheng | 80f5404 | 2008-04-25 18:19:54 +0000 | [diff] [blame] | 3819 | |
| 3820 | //===----------------------------------------------------------------------===// |
| 3821 | // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2) |
| 3822 | //===----------------------------------------------------------------------===// |
| 3823 | |
| 3824 | include "X86InstrMMX.td" |