Blame - lib/Target/CellSPU/SPUInstrInfo.td - fp2-dev/platform/external/llvm

blob: a0e2fe1a685a7bec542e454e6888774aa35cf26c [file] [log] [blame]

Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1	//==- SPUInstrInfo.td - Describe the Cell SPU Instructions -- tablegen --==//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
Scott Michel	43e7c5e	2007-12-05 01:40:25 +0000	[diff] [blame]	5	// This file was developed by a team from the Computer Systems Research
				6	// Department at The Aerospace Corporation and is distributed under the
				7	// University of Illinois Open Source License. See LICENSE.TXT for details.
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	8	//
				9	//===----------------------------------------------------------------------===//
				10	// Cell SPU Instructions:
				11	//===----------------------------------------------------------------------===//
				12
				13	//===----------------------------------------------------------------------===//
				14	// TODO Items (not urgent today, but would be nice, low priority)
				15	//
				16	// ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
				17	// concatenating the byte argument b as "bbbb". Could recognize this bit pattern
				18	// in 16-bit and 32-bit constants and reduce instruction count.
				19	//===----------------------------------------------------------------------===//
				20
				21	//===----------------------------------------------------------------------===//
				22	// Pseudo instructions:
				23	//===----------------------------------------------------------------------===//
				24
				25	let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
				26	def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
				27	"${:comment} ADJCALLSTACKDOWN",
				28	[(callseq_start imm:$amt)]>;
				29	def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt),
				30	"${:comment} ADJCALLSTACKUP",
				31	[(callseq_end imm:$amt)]>;
				32	}
				33
				34	//===----------------------------------------------------------------------===//
				35	// DWARF debugging Pseudo Instructions
				36	//===----------------------------------------------------------------------===//
				37
				38	def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
				39	"${:comment} .loc $file, $line, $col",
				40	[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
				41	(i32 imm:$file))]>;
				42
				43	//===----------------------------------------------------------------------===//
				44	// Loads:
				45	// NB: The ordering is actually important, since the instruction selection
				46	// will try each of the instructions in sequence, i.e., the D-form first with
				47	// the 10-bit displacement, then the A-form with the 16 bit displacement, and
				48	// finally the X-form with the register-register.
				49	//===----------------------------------------------------------------------===//
				50
				51	let isLoad = 1 in {
				52	def LQDv16i8:
				53	RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
				54	"lqd\t$rT, $src", LoadStore,
				55	[(set (v16i8 VECREG:$rT), (load dform_addr:$src))]>;
				56
				57	def LQDv8i16:
				58	RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
				59	"lqd\t$rT, $src", LoadStore,
				60	[(set (v8i16 VECREG:$rT), (load dform_addr:$src))]>;
				61
				62	def LQDv4i32:
				63	RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
				64	"lqd\t$rT, $src", LoadStore,
				65	[(set (v4i32 VECREG:$rT), (load dform_addr:$src))]>;
				66
				67	def LQDv2i64:
				68	RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
				69	"lqd\t$rT, $src", LoadStore,
				70	[(set (v2i64 VECREG:$rT), (load dform_addr:$src))]>;
				71
				72	def LQDv4f32:
				73	RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
				74	"lqd\t$rT, $src", LoadStore,
				75	[(set (v4f32 VECREG:$rT), (load dform_addr:$src))]>;
				76
				77	def LQDv2f64:
				78	RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
				79	"lqd\t$rT, $src", LoadStore,
				80	[(set (v2f64 VECREG:$rT), (load dform_addr:$src))]>;
				81
				82	def LQDr128:
				83	RI10Form<0b00101100, (outs GPRC:$rT), (ins memri10:$src),
				84	"lqd\t$rT, $src", LoadStore,
				85	[(set GPRC:$rT, (load dform_addr:$src))]>;
				86
				87	def LQDr64:
				88	RI10Form<0b00101100, (outs R64C:$rT), (ins memri10:$src),
				89	"lqd\t$rT, $src", LoadStore,
				90	[(set R64C:$rT, (load dform_addr:$src))]>;
				91
				92	def LQDr32:
				93	RI10Form<0b00101100, (outs R32C:$rT), (ins memri10:$src),
				94	"lqd\t$rT, $src", LoadStore,
				95	[(set R32C:$rT, (load dform_addr:$src))]>;
				96
				97	// Floating Point
				98	def LQDf32:
				99	RI10Form<0b00101100, (outs R32FP:$rT), (ins memri10:$src),
				100	"lqd\t$rT, $src", LoadStore,
				101	[(set R32FP:$rT, (load dform_addr:$src))]>;
				102
				103	def LQDf64:
				104	RI10Form<0b00101100, (outs R64FP:$rT), (ins memri10:$src),
				105	"lqd\t$rT, $src", LoadStore,
				106	[(set R64FP:$rT, (load dform_addr:$src))]>;
				107	// END Floating Point
				108
				109	def LQDr16:
				110	RI10Form<0b00101100, (outs R16C:$rT), (ins memri10:$src),
				111	"lqd\t$rT, $src", LoadStore,
				112	[(set R16C:$rT, (load dform_addr:$src))]>;
				113
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	114	def LQDr8:
				115	RI10Form<0b00101100, (outs R8C:$rT), (ins memri10:$src),
				116	"lqd\t$rT, $src", LoadStore,
				117	[(set R8C:$rT, (load dform_addr:$src))]>;
				118
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	119	def LQAv16i8:
				120	RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
				121	"lqa\t$rT, $src", LoadStore,
				122	[(set (v16i8 VECREG:$rT), (load aform_addr:$src))]>;
				123
				124	def LQAv8i16:
				125	RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
				126	"lqa\t$rT, $src", LoadStore,
				127	[(set (v8i16 VECREG:$rT), (load aform_addr:$src))]>;
				128
				129	def LQAv4i32:
				130	RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
				131	"lqa\t$rT, $src", LoadStore,
				132	[(set (v4i32 VECREG:$rT), (load aform_addr:$src))]>;
				133
				134	def LQAv2i64:
				135	RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
				136	"lqa\t$rT, $src", LoadStore,
				137	[(set (v2i64 VECREG:$rT), (load aform_addr:$src))]>;
				138
				139	def LQAv4f32:
				140	RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
				141	"lqa\t$rT, $src", LoadStore,
				142	[(set (v4f32 VECREG:$rT), (load aform_addr:$src))]>;
				143
				144	def LQAv2f64:
				145	RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
				146	"lqa\t$rT, $src", LoadStore,
				147	[(set (v2f64 VECREG:$rT), (load aform_addr:$src))]>;
				148
				149	def LQAr128:
				150	RI16Form<0b100001100, (outs GPRC:$rT), (ins addr256k:$src),
				151	"lqa\t$rT, $src", LoadStore,
				152	[(set GPRC:$rT, (load aform_addr:$src))]>;
				153
				154	def LQAr64:
				155	RI16Form<0b100001100, (outs R64C:$rT), (ins addr256k:$src),
				156	"lqa\t$rT, $src", LoadStore,
				157	[(set R64C:$rT, (load aform_addr:$src))]>;
				158
				159	def LQAr32:
				160	RI16Form<0b100001100, (outs R32C:$rT), (ins addr256k:$src),
				161	"lqa\t$rT, $src", LoadStore,
				162	[(set R32C:$rT, (load aform_addr:$src))]>;
				163
				164	def LQAf32:
				165	RI16Form<0b100001100, (outs R32FP:$rT), (ins addr256k:$src),
				166	"lqa\t$rT, $src", LoadStore,
				167	[(set R32FP:$rT, (load aform_addr:$src))]>;
				168
				169	def LQAf64:
				170	RI16Form<0b100001100, (outs R64FP:$rT), (ins addr256k:$src),
				171	"lqa\t$rT, $src", LoadStore,
				172	[(set R64FP:$rT, (load aform_addr:$src))]>;
				173
				174	def LQAr16:
				175	RI16Form<0b100001100, (outs R16C:$rT), (ins addr256k:$src),
				176	"lqa\t$rT, $src", LoadStore,
				177	[(set R16C:$rT, (load aform_addr:$src))]>;
				178
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	179	def LQAr8:
				180	RI16Form<0b100001100, (outs R8C:$rT), (ins addr256k:$src),
				181	"lqa\t$rT, $src", LoadStore,
				182	[(set R8C:$rT, (load aform_addr:$src))]>;
				183
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	184	def LQXv16i8:
				185	RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
				186	"lqx\t$rT, $src", LoadStore,
				187	[(set (v16i8 VECREG:$rT), (load xform_addr:$src))]>;
				188
				189	def LQXv8i16:
				190	RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
				191	"lqx\t$rT, $src", LoadStore,
				192	[(set (v8i16 VECREG:$rT), (load xform_addr:$src))]>;
				193
				194	def LQXv4i32:
				195	RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
				196	"lqx\t$rT, $src", LoadStore,
				197	[(set (v4i32 VECREG:$rT), (load xform_addr:$src))]>;
				198
				199	def LQXv2i64:
				200	RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
				201	"lqx\t$rT, $src", LoadStore,
				202	[(set (v2i64 VECREG:$rT), (load xform_addr:$src))]>;
				203
				204	def LQXv4f32:
				205	RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
				206	"lqx\t$rT, $src", LoadStore,
				207	[(set (v4f32 VECREG:$rT), (load xform_addr:$src))]>;
				208
				209	def LQXv2f64:
				210	RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
				211	"lqx\t$rT, $src", LoadStore,
				212	[(set (v2f64 VECREG:$rT), (load xform_addr:$src))]>;
				213
				214	def LQXr128:
				215	RRForm<0b00100011100, (outs GPRC:$rT), (ins memrr:$src),
				216	"lqx\t$rT, $src", LoadStore,
				217	[(set GPRC:$rT, (load xform_addr:$src))]>;
				218
				219	def LQXr64:
				220	RRForm<0b00100011100, (outs R64C:$rT), (ins memrr:$src),
				221	"lqx\t$rT, $src", LoadStore,
				222	[(set R64C:$rT, (load xform_addr:$src))]>;
				223
				224	def LQXr32:
				225	RRForm<0b00100011100, (outs R32C:$rT), (ins memrr:$src),
				226	"lqx\t$rT, $src", LoadStore,
				227	[(set R32C:$rT, (load xform_addr:$src))]>;
				228
				229	def LQXf32:
				230	RRForm<0b00100011100, (outs R32FP:$rT), (ins memrr:$src),
				231	"lqx\t$rT, $src", LoadStore,
				232	[(set R32FP:$rT, (load xform_addr:$src))]>;
				233
				234	def LQXf64:
				235	RRForm<0b00100011100, (outs R64FP:$rT), (ins memrr:$src),
				236	"lqx\t$rT, $src", LoadStore,
				237	[(set R64FP:$rT, (load xform_addr:$src))]>;
				238
				239	def LQXr16:
				240	RRForm<0b00100011100, (outs R16C:$rT), (ins memrr:$src),
				241	"lqx\t$rT, $src", LoadStore,
				242	[(set R16C:$rT, (load xform_addr:$src))]>;
				243
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	244	def LQXr8:
				245	RRForm<0b00100011100, (outs R8C:$rT), (ins memrr:$src),
				246	"lqx\t$rT, $src", LoadStore,
				247	[(set R8C:$rT, (load xform_addr:$src))]>;
				248
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	249	/* Load quadword, PC relative: Not much use at this point in time.
				250	Might be of use later for relocatable code.
				251	def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
				252	"lqr\t$rT, $disp", LoadStore,
				253	[(set VECREG:$rT, (load iaddr:$disp))]>;
				254	*/
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	255	}
				256
				257	//===----------------------------------------------------------------------===//
				258	// Stores:
				259	//===----------------------------------------------------------------------===//
				260
				261	let isStore = 1 in {
				262	def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
				263	"stqd\t$rT, $src", LoadStore,
				264	[(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
				265
				266	def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
				267	"stqd\t$rT, $src", LoadStore,
				268	[(store (v8i16 VECREG:$rT), dform_addr:$src)]>;
				269
				270	def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
				271	"stqd\t$rT, $src", LoadStore,
				272	[(store (v4i32 VECREG:$rT), dform_addr:$src)]>;
				273
				274	def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
				275	"stqd\t$rT, $src", LoadStore,
				276	[(store (v2i64 VECREG:$rT), dform_addr:$src)]>;
				277
				278	def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
				279	"stqd\t$rT, $src", LoadStore,
				280	[(store (v4f32 VECREG:$rT), dform_addr:$src)]>;
				281
				282	def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
				283	"stqd\t$rT, $src", LoadStore,
				284	[(store (v2f64 VECREG:$rT), dform_addr:$src)]>;
				285
				286	def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src),
				287	"stqd\t$rT, $src", LoadStore,
				288	[(store GPRC:$rT, dform_addr:$src)]>;
				289
				290	def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src),
				291	"stqd\t$rT, $src", LoadStore,
				292	[(store R64C:$rT, dform_addr:$src)]>;
				293
				294	def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src),
				295	"stqd\t$rT, $src", LoadStore,
				296	[(store R32C:$rT, dform_addr:$src)]>;
				297
				298	// Floating Point
				299	def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src),
				300	"stqd\t$rT, $src", LoadStore,
				301	[(store R32FP:$rT, dform_addr:$src)]>;
				302
				303	def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src),
				304	"stqd\t$rT, $src", LoadStore,
				305	[(store R64FP:$rT, dform_addr:$src)]>;
				306
				307	def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src),
				308	"stqd\t$rT, $src", LoadStore,
				309	[(store R16C:$rT, dform_addr:$src)]>;
				310
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	311	def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src),
				312	"stqd\t$rT, $src", LoadStore,
				313	[(store R8C:$rT, dform_addr:$src)]>;
				314
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	315	def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
				316	"stqa\t$rT, $src", LoadStore,
				317	[(store (v16i8 VECREG:$rT), aform_addr:$src)]>;
				318
				319	def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
				320	"stqa\t$rT, $src", LoadStore,
				321	[(store (v8i16 VECREG:$rT), aform_addr:$src)]>;
				322
				323	def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
				324	"stqa\t$rT, $src", LoadStore,
				325	[(store (v4i32 VECREG:$rT), aform_addr:$src)]>;
				326
				327	def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
				328	"stqa\t$rT, $src", LoadStore,
				329	[(store (v2i64 VECREG:$rT), aform_addr:$src)]>;
				330
				331	def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
				332	"stqa\t$rT, $src", LoadStore,
				333	[(store (v4f32 VECREG:$rT), aform_addr:$src)]>;
				334
				335	def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
				336	"stqa\t$rT, $src", LoadStore,
				337	[(store (v2f64 VECREG:$rT), aform_addr:$src)]>;
				338
				339	def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src),
				340	"stqa\t$rT, $src", LoadStore,
				341	[(store GPRC:$rT, aform_addr:$src)]>;
				342
				343	def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src),
				344	"stqa\t$rT, $src", LoadStore,
				345	[(store R64C:$rT, aform_addr:$src)]>;
				346
				347	def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src),
				348	"stqa\t$rT, $src", LoadStore,
				349	[(store R32C:$rT, aform_addr:$src)]>;
				350
				351	// Floating Point
				352	def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src),
				353	"stqa\t$rT, $src", LoadStore,
				354	[(store R32FP:$rT, aform_addr:$src)]>;
				355
				356	def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src),
				357	"stqa\t$rT, $src", LoadStore,
				358	[(store R64FP:$rT, aform_addr:$src)]>;
				359
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	360	def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src),
				361	"stqa\t$rT, $src", LoadStore,
				362	[(store R16C:$rT, aform_addr:$src)]>;
				363
				364	def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src),
				365	"stqa\t$rT, $src", LoadStore,
				366	[(store R8C:$rT, aform_addr:$src)]>;
				367
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	368	def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
				369	"stqx\t$rT, $src", LoadStore,
				370	[(store (v16i8 VECREG:$rT), xform_addr:$src)]>;
				371
				372	def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
				373	"stqx\t$rT, $src", LoadStore,
				374	[(store (v8i16 VECREG:$rT), xform_addr:$src)]>;
				375
				376	def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
				377	"stqx\t$rT, $src", LoadStore,
				378	[(store (v4i32 VECREG:$rT), xform_addr:$src)]>;
				379
				380	def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
				381	"stqx\t$rT, $src", LoadStore,
				382	[(store (v2i64 VECREG:$rT), xform_addr:$src)]>;
				383
				384	def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
				385	"stqx\t$rT, $src", LoadStore,
				386	[(store (v4f32 VECREG:$rT), xform_addr:$src)]>;
				387
				388	def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
				389	"stqx\t$rT, $src", LoadStore,
				390	[(store (v2f64 VECREG:$rT), xform_addr:$src)]>;
				391
				392	def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src),
				393	"stqx\t$rT, $src", LoadStore,
				394	[(store GPRC:$rT, xform_addr:$src)]>;
				395
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	396	def STQXr64:
				397	RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	398	"stqx\t$rT, $src", LoadStore,
				399	[(store R64C:$rT, xform_addr:$src)]>;
				400
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	401	def STQXr32:
				402	RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	403	"stqx\t$rT, $src", LoadStore,
				404	[(store R32C:$rT, xform_addr:$src)]>;
				405
				406	// Floating Point
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	407	def STQXf32:
				408	RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	409	"stqx\t$rT, $src", LoadStore,
				410	[(store R32FP:$rT, xform_addr:$src)]>;
				411
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	412	def STQXf64:
				413	RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	414	"stqx\t$rT, $src", LoadStore,
				415	[(store R64FP:$rT, xform_addr:$src)]>;
				416
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	417	def STQXr16:
				418	RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	419	"stqx\t$rT, $src", LoadStore,
				420	[(store R16C:$rT, xform_addr:$src)]>;
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	421
				422	def STQXr8:
				423	RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src),
				424	"stqx\t$rT, $src", LoadStore,
				425	[(store R8C:$rT, xform_addr:$src)]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	426
				427	/* Store quadword, PC relative: Not much use at this point in time. Might
				428	be useful for relocatable code.
				429	def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
				430	"stqr\t$rT, $disp", LoadStore,
				431	[(store VECREG:$rT, iaddr:$disp)]>;
				432	*/
				433	}
				434
				435	//===----------------------------------------------------------------------===//
				436	// Generate Controls for Insertion:
				437	//===----------------------------------------------------------------------===//
				438
				439	def CBD :
				440	RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
				441	"cbd\t$rT, $src", ShuffleOp,
				442	[(set (v16i8 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
				443
				444	def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
				445	"cbx\t$rT, $src", ShuffleOp,
				446	[(set (v16i8 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
				447
				448	def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
				449	"chd\t$rT, $src", ShuffleOp,
				450	[(set (v8i16 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
				451
				452	def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
				453	"chx\t$rT, $src", ShuffleOp,
				454	[(set (v8i16 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
				455
				456	def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
				457	"cwd\t$rT, $src", ShuffleOp,
				458	[(set (v4i32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
				459
				460	def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
				461	"cwx\t$rT, $src", ShuffleOp,
				462	[(set (v4i32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
				463
				464	def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
				465	"cdd\t$rT, $src", ShuffleOp,
				466	[(set (v2i64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
				467
				468	def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
				469	"cdx\t$rT, $src", ShuffleOp,
				470	[(set (v2i64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
				471
				472	//===----------------------------------------------------------------------===//
				473	// Constant formation:
				474	//===----------------------------------------------------------------------===//
				475
				476	def ILHv8i16:
				477	RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
				478	"ilh\t$rT, $val", ImmLoad,
				479	[(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
				480
				481	def ILHr16:
				482	RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
				483	"ilh\t$rT, $val", ImmLoad,
				484	[(set R16C:$rT, immSExt16:$val)]>;
				485
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	486	// Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
				487	// the right constant")
				488	def ILHr8:
				489	RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
				490	"ilh\t$rT, $val", ImmLoad,
				491	[(set R8C:$rT, immSExt8:$val)]>;
				492
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	493	// IL does sign extension!
				494	def ILr64:
				495	RI16Form<0b100000010, (outs R64C:$rT), (ins s16imm_i64:$val),
				496	"il\t$rT, $val", ImmLoad,
				497	[(set R64C:$rT, immSExt16:$val)]>;
				498
				499	def ILv2i64:
				500	RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm_i64:$val),
				501	"il\t$rT, $val", ImmLoad,
				502	[(set VECREG:$rT, (v2i64 v2i64SExt16Imm:$val))]>;
				503
				504	def ILv4i32:
				505	RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm:$val),
				506	"il\t$rT, $val", ImmLoad,
				507	[(set VECREG:$rT, (v4i32 v4i32SExt16Imm:$val))]>;
				508
				509	def ILr32:
				510	RI16Form<0b100000010, (outs R32C:$rT), (ins s16imm_i32:$val),
				511	"il\t$rT, $val", ImmLoad,
				512	[(set R32C:$rT, immSExt16:$val)]>;
				513
				514	def ILf32:
				515	RI16Form<0b100000010, (outs R32FP:$rT), (ins s16imm_f32:$val),
				516	"il\t$rT, $val", ImmLoad,
				517	[(set R32FP:$rT, (SPUFPconstant fpimmSExt16:$val))]>;
				518
				519	def ILf64:
				520	RI16Form<0b100000010, (outs R64FP:$rT), (ins s16imm_f64:$val),
				521	"il\t$rT, $val", ImmLoad,
				522	[(set R64FP:$rT, (SPUFPconstant fpimmSExt16:$val))]>;
				523
				524	def ILHUv4i32:
				525	RI16Form<0b010000010, (outs VECREG:$rT), (ins u16imm:$val),
				526	"ilhu\t$rT, $val", ImmLoad,
				527	[(set VECREG:$rT, (v4i32 immILHUvec:$val))]>;
				528
				529	def ILHUr32:
				530	RI16Form<0b010000010, (outs R32C:$rT), (ins u16imm:$val),
				531	"ilhu\t$rT, $val", ImmLoad,
				532	[(set R32C:$rT, hi16:$val)]>;
				533
				534	// ILHUf32: Used to custom lower float constant loads
				535	def ILHUf32:
				536	RI16Form<0b010000010, (outs R32FP:$rT), (ins f16imm:$val),
				537	"ilhu\t$rT, $val", ImmLoad,
				538	[(set R32FP:$rT, (SPUFPconstant hi16_f32:$val))]>;
				539
				540	// ILHUhi: Used for loading high portion of an address. Note the symbolHi
				541	// printer used for the operand.
				542	def ILHUhi : RI16Form<0b010000010, (outs R32C:$rT), (ins symbolHi:$val),
				543	"ilhu\t$rT, $val", ImmLoad,
				544	[(set R32C:$rT, hi16:$val)]>;
				545
				546	// Immediate load address (can also be used to load 18-bit unsigned constants,
				547	// see the zext 16->32 pattern)
				548	def ILAr64:
				549	RI18Form<0b1000010, (outs R64C:$rT), (ins u18imm_i64:$val),
				550	"ila\t$rT, $val", LoadNOP,
				551	[(set R64C:$rT, imm18:$val)]>;
				552
				553	// TODO: ILAv2i64
				554
				555	def ILAv2i64:
				556	RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val),
				557	"ila\t$rT, $val", LoadNOP,
				558	[(set (v2i64 VECREG:$rT), v2i64Uns18Imm:$val)]>;
				559
				560	def ILAv4i32:
				561	RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val),
				562	"ila\t$rT, $val", LoadNOP,
				563	[(set (v4i32 VECREG:$rT), v4i32Uns18Imm:$val)]>;
				564
				565	def ILAr32:
				566	RI18Form<0b1000010, (outs R32C:$rT), (ins u18imm:$val),
				567	"ila\t$rT, $val", LoadNOP,
				568	[(set R32C:$rT, imm18:$val)]>;
				569
				570	def ILAf32:
				571	RI18Form<0b1000010, (outs R32FP:$rT), (ins f18imm:$val),
				572	"ila\t$rT, $val", LoadNOP,
				573	[(set R32FP:$rT, (SPUFPconstant fpimm18:$val))]>;
				574
				575	def ILAf64:
				576	RI18Form<0b1000010, (outs R64FP:$rT), (ins f18imm_f64:$val),
				577	"ila\t$rT, $val", LoadNOP,
				578	[(set R64FP:$rT, (SPUFPconstant fpimm18:$val))]>;
				579
				580	def ILAlo:
				581	RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLo:$val),
				582	"ila\t$rT, $val", ImmLoad,
				583	[(set R32C:$rT, imm18:$val)]>;
				584
				585	def ILAlsa:
				586	RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLSA:$val),
				587	"ila\t$rT, $val", ImmLoad,
				588	[/* no pattern */]>;
				589
				590	// Immediate OR, Halfword Lower: The "other" part of loading large constants
				591	// into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
				592	// Note that these are really two operand instructions, but they're encoded
				593	// as three operands with the first two arguments tied-to each other.
				594
				595	def IOHLvec:
				596	RI16Form<0b100000110, (outs VECREG:$rT), (ins VECREG:$rS, u16imm:$val),
				597	"iohl\t$rT, $val", ImmLoad,
				598	[/* insert intrinsic here */]>,
				599	RegConstraint<"$rS = $rT">,
				600	NoEncode<"$rS">;
				601
				602	def IOHLr32:
				603	RI16Form<0b100000110, (outs R32C:$rT), (ins R32C:$rS, i32imm:$val),
				604	"iohl\t$rT, $val", ImmLoad,
				605	[/* insert intrinsic here */]>,
				606	RegConstraint<"$rS = $rT">,
				607	NoEncode<"$rS">;
				608
				609	def IOHLf32:
				610	RI16Form<0b100000110, (outs R32FP:$rT), (ins R32FP:$rS, f32imm:$val),
				611	"iohl\t$rT, $val", ImmLoad,
				612	[/* insert intrinsic here */]>,
				613	RegConstraint<"$rS = $rT">,
				614	NoEncode<"$rS">;
				615
				616	// Form select mask for bytes using immediate, used in conjunction with the
				617	// SELB instruction:
				618
				619	def FSMBIv16i8 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
				620	"fsmbi\t$rT, $val", SelectOp,
				621	[(set (v16i8 VECREG:$rT), (SPUfsmbi_v16i8 immU16:$val))]>;
				622
				623	def FSMBIv8i16 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
				624	"fsmbi\t$rT, $val", SelectOp,
				625	[(set (v8i16 VECREG:$rT), (SPUfsmbi_v8i16 immU16:$val))]>;
				626
				627	def FSMBIvecv4i32 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
				628	"fsmbi\t$rT, $val", SelectOp,
				629	[(set (v4i32 VECREG:$rT), (SPUfsmbi_v4i32 immU16:$val))]>;
				630
				631	//===----------------------------------------------------------------------===//
				632	// Integer and Logical Operations:
				633	//===----------------------------------------------------------------------===//
				634
				635	def AHv8i16:
				636	RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				637	"ah\t$rT, $rA, $rB", IntegerOp,
				638	[(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
				639
				640	def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
				641	(AHv8i16 VECREG:$rA, VECREG:$rB)>;
				642
				643	// [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
				644
				645	def AHr16:
				646	RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				647	"ah\t$rT, $rA, $rB", IntegerOp,
				648	[(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
				649
				650	def AHIvec:
				651	RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				652	"ahi\t$rT, $rA, $val", IntegerOp,
				653	[(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
				654	v8i16SExt10Imm:$val))]>;
				655
				656	def AHIr16 : RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
				657	"ahi\t$rT, $rA, $val", IntegerOp,
				658	[(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
				659
				660	def Avec : RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				661	"a\t$rT, $rA, $rB", IntegerOp,
				662	[(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
				663
				664	def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
				665	(Avec VECREG:$rA, VECREG:$rB)>;
				666
				667	def Ar32 : RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				668	"a\t$rT, $rA, $rB", IntegerOp,
				669	[(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
				670
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	671	def Ar8:
				672	RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
				673	"a\t$rT, $rA, $rB", IntegerOp,
				674	[(set R8C:$rT, (add R8C:$rA, R8C:$rB))]>;
				675
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	676	def AIvec:
				677	RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				678	"ai\t$rT, $rA, $val", IntegerOp,
				679	[(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA),
				680	v4i32SExt10Imm:$val))]>;
				681
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	682	def AIr32:
				683	RI10Form<0b00111000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
				684	"ai\t$rT, $rA, $val", IntegerOp,
				685	[(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	686
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	687	def SFHvec:
				688	RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				689	"sfh\t$rT, $rA, $rB", IntegerOp,
				690	[(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
				691	(v8i16 VECREG:$rB)))]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	692
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	693	def SFHr16:
				694	RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				695	"sfh\t$rT, $rA, $rB", IntegerOp,
				696	[(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	697
				698	def SFHIvec:
				699	RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				700	"sfhi\t$rT, $rA, $val", IntegerOp,
				701	[(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
				702	(v8i16 VECREG:$rA)))]>;
				703
				704	def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
				705	"sfhi\t$rT, $rA, $val", IntegerOp,
				706	[(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
				707
				708	def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
				709	(ins VECREG:$rA, VECREG:$rB),
				710	"sf\t$rT, $rA, $rB", IntegerOp,
				711	[(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
				712
				713	def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				714	"sf\t$rT, $rA, $rB", IntegerOp,
				715	[(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
				716
				717	def SFIvec:
				718	RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				719	"sfi\t$rT, $rA, $val", IntegerOp,
				720	[(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
				721	(v4i32 VECREG:$rA)))]>;
				722
				723	def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
				724	(ins R32C:$rA, s10imm_i32:$val),
				725	"sfi\t$rT, $rA, $val", IntegerOp,
				726	[(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
				727
				728	// ADDX: only available in vector form, doesn't match a pattern.
				729	def ADDXvec:
				730	RRForm<0b00000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
				731	VECREG:$rCarry),
				732	"addx\t$rT, $rA, $rB", IntegerOp,
				733	[]>,
				734	RegConstraint<"$rCarry = $rT">,
				735	NoEncode<"$rCarry">;
				736
				737	// CG: only available in vector form, doesn't match a pattern.
				738	def CGvec:
				739	RRForm<0b01000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
				740	VECREG:$rCarry),
				741	"cg\t$rT, $rA, $rB", IntegerOp,
				742	[]>,
				743	RegConstraint<"$rCarry = $rT">,
				744	NoEncode<"$rCarry">;
				745
				746	// SFX: only available in vector form, doesn't match a pattern
				747	def SFXvec:
				748	RRForm<0b10000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
				749	VECREG:$rCarry),
				750	"sfx\t$rT, $rA, $rB", IntegerOp,
				751	[]>,
				752	RegConstraint<"$rCarry = $rT">,
				753	NoEncode<"$rCarry">;
				754
				755	// BG: only available in vector form, doesn't match a pattern.
				756	def BGvec:
				757	RRForm<0b01000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
				758	VECREG:$rCarry),
				759	"bg\t$rT, $rA, $rB", IntegerOp,
				760	[]>,
				761	RegConstraint<"$rCarry = $rT">,
				762	NoEncode<"$rCarry">;
				763
				764	// BGX: only available in vector form, doesn't match a pattern.
				765	def BGXvec:
				766	RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
				767	VECREG:$rCarry),
				768	"bgx\t$rT, $rA, $rB", IntegerOp,
				769	[]>,
				770	RegConstraint<"$rCarry = $rT">,
				771	NoEncode<"$rCarry">;
				772
				773	// Halfword multiply variants:
				774	// N.B: These can be used to build up larger quantities (16x16 -> 32)
				775
				776	def MPYv8i16:
				777	RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				778	"mpy\t$rT, $rA, $rB", IntegerMulDiv,
				779	[(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
				780	(v8i16 VECREG:$rB)))]>;
				781
				782	def MPYr16:
				783	RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				784	"mpy\t$rT, $rA, $rB", IntegerMulDiv,
				785	[(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
				786
				787	def MPYUv4i32:
				788	RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				789	"mpyu\t$rT, $rA, $rB", IntegerMulDiv,
				790	[(set (v4i32 VECREG:$rT),
				791	(SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
				792
				793	def MPYUr16:
				794	RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
				795	"mpyu\t$rT, $rA, $rB", IntegerMulDiv,
				796	[(set R32C:$rT, (mul (zext R16C:$rA),
				797	(zext R16C:$rB)))]>;
				798
				799	def MPYUr32:
				800	RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				801	"mpyu\t$rT, $rA, $rB", IntegerMulDiv,
				802	[(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
				803
				804	// mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
				805	// this only produces the lower 16 bits)
				806	def MPYIvec:
				807	RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				808	"mpyi\t$rT, $rA, $val", IntegerMulDiv,
				809	[(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
				810
				811	def MPYIr16:
				812	RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
				813	"mpyi\t$rT, $rA, $val", IntegerMulDiv,
				814	[(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
				815
				816	// mpyui: same issues as other multiplies, plus, this doesn't match a
				817	// pattern... but may be used during target DAG selection or lowering
				818	def MPYUIvec:
				819	RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				820	"mpyui\t$rT, $rA, $val", IntegerMulDiv,
				821	[]>;
				822
				823	def MPYUIr16:
				824	RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
				825	"mpyui\t$rT, $rA, $val", IntegerMulDiv,
				826	[]>;
				827
				828	// mpya: 16 x 16 + 16 -> 32 bit result
				829	def MPYAvec:
				830	RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				831	"mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
				832	[(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
				833	(v8i16 VECREG:$rB)))),
				834	(v4i32 VECREG:$rC)))]>;
				835
				836	def MPYAr32:
				837	RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
				838	"mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
				839	[(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
				840	R32C:$rC))]>;
				841
				842	def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
				843	(MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
				844
				845	def MPYAr32_sextinreg:
				846	RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
				847	"mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
				848	[(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
				849	(sext_inreg R32C:$rB, i16)),
				850	R32C:$rC))]>;
				851
				852	//def MPYAr32:
				853	// RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
				854	// "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
				855	// [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
				856	// R32C:$rC))]>;
				857
				858	// mpyh: multiply high, used to synthesize 32-bit multiplies
				859	def MPYHv4i32:
				860	RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				861	"mpyh\t$rT, $rA, $rB", IntegerMulDiv,
				862	[(set (v4i32 VECREG:$rT),
				863	(SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
				864
				865	def MPYHr32:
				866	RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				867	"mpyh\t$rT, $rA, $rB", IntegerMulDiv,
				868	[(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
				869
				870	// mpys: multiply high and shift right (returns the top half of
				871	// a 16-bit multiply, sign extended to 32 bits.)
				872	def MPYSvec:
				873	RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				874	"mpys\t$rT, $rA, $rB", IntegerMulDiv,
				875	[]>;
				876
				877	def MPYSr16:
				878	RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
				879	"mpys\t$rT, $rA, $rB", IntegerMulDiv,
				880	[]>;
				881
				882	// mpyhh: multiply high-high (returns the 32-bit result from multiplying
				883	// the top 16 bits of the $rA, $rB)
				884	def MPYHHv8i16:
				885	RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				886	"mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
				887	[(set (v8i16 VECREG:$rT),
				888	(SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
				889
				890	def MPYHHr32:
				891	RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				892	"mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
				893	[]>;
				894
				895	// mpyhha: Multiply high-high, add to $rT:
				896	def MPYHHAvec:
				897	RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				898	"mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
				899	[]>;
				900
				901	def MPYHHAr32:
				902	RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				903	"mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
				904	[]>;
				905
				906	// mpyhhu: Multiply high-high, unsigned
				907	def MPYHHUvec:
				908	RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				909	"mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
				910	[]>;
				911
				912	def MPYHHUr32:
				913	RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				914	"mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
				915	[]>;
				916
				917	// mpyhhau: Multiply high-high, unsigned
				918	def MPYHHAUvec:
				919	RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				920	"mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
				921	[]>;
				922
				923	def MPYHHAUr32:
				924	RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				925	"mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
				926	[]>;
				927
				928	// clz: Count leading zeroes
				929	def CLZv4i32:
				930	RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA),
				931	"clz\t$rT, $rA", IntegerOp,
				932	[/* intrinsic */]>;
				933
				934	def CLZr32:
				935	RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA),
				936	"clz\t$rT, $rA", IntegerOp,
				937	[(set R32C:$rT, (ctlz R32C:$rA))]>;
				938
				939	// cntb: Count ones in bytes (aka "population count")
				940	// NOTE: This instruction is really a vector instruction, but the custom
				941	// lowering code uses it in unorthodox ways to support CTPOP for other
				942	// data types!
				943	def CNTBv16i8:
				944	RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
				945	"cntb\t$rT, $rA", IntegerOp,
				946	[(set (v16i8 VECREG:$rT), (SPUcntb_v16i8 (v16i8 VECREG:$rA)))]>;
				947
				948	def CNTBv8i16 :
				949	RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
				950	"cntb\t$rT, $rA", IntegerOp,
				951	[(set (v8i16 VECREG:$rT), (SPUcntb_v8i16 (v8i16 VECREG:$rA)))]>;
				952
				953	def CNTBv4i32 :
				954	RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
				955	"cntb\t$rT, $rA", IntegerOp,
				956	[(set (v4i32 VECREG:$rT), (SPUcntb_v4i32 (v4i32 VECREG:$rA)))]>;
				957
				958	// fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
				959	def FSMB:
				960	RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
				961	"fsmb\t$rT, $rA", SelectOp,
				962	[]>;
				963
				964	// fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
				965	// only 8-bits wide (even though it's input as 16-bits here)
				966	def FSMH:
				967	RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
				968	"fsmh\t$rT, $rA", SelectOp,
				969	[]>;
				970
				971	// fsm: Form select mask for words. Like the other fsm* instructions,
				972	// only the lower 4 bits of $rA are significant.
				973	def FSM:
				974	RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA),
				975	"fsm\t$rT, $rA", SelectOp,
				976	[]>;
				977
				978	// gbb: Gather all low order bits from each byte in $rA into a single 16-bit
				979	// quantity stored into $rT
				980	def GBB:
				981	RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA),
				982	"gbb\t$rT, $rA", GatherOp,
				983	[]>;
				984
				985	// gbh: Gather all low order bits from each halfword in $rA into a single
				986	// 8-bit quantity stored in $rT
				987	def GBH:
				988	RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA),
				989	"gbh\t$rT, $rA", GatherOp,
				990	[]>;
				991
				992	// gb: Gather all low order bits from each word in $rA into a single
				993	// 4-bit quantity stored in $rT
				994	def GB:
				995	RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA),
				996	"gb\t$rT, $rA", GatherOp,
				997	[]>;
				998
				999	// avgb: average bytes
				1000	def AVGB:
				1001	RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1002	"avgb\t$rT, $rA, $rB", ByteOp,
				1003	[]>;
				1004
				1005	// absdb: absolute difference of bytes
				1006	def ABSDB:
				1007	RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1008	"absdb\t$rT, $rA, $rB", ByteOp,
				1009	[]>;
				1010
				1011	// sumb: sum bytes into halfwords
				1012	def SUMB:
				1013	RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1014	"sumb\t$rT, $rA, $rB", ByteOp,
				1015	[]>;
				1016
				1017	// Sign extension operations:
				1018	def XSBHvec:
				1019	RRForm_1<0b01101101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
				1020	"xsbh\t$rDst, $rSrc", IntegerOp,
				1021	[(set (v8i16 VECREG:$rDst), (sext (v16i8 VECREG:$rSrc)))]>;
				1022
				1023	// Ordinary form for XSBH
				1024	def XSBHr16:
				1025	RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R16C:$rSrc),
				1026	"xsbh\t$rDst, $rSrc", IntegerOp,
				1027	[(set R16C:$rDst, (sext_inreg R16C:$rSrc, i8))]>;
				1028
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1029	def XSBHr8:
				1030	RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R8C:$rSrc),
				1031	"xsbh\t$rDst, $rSrc", IntegerOp,
				1032	[(set R16C:$rDst, (sext R8C:$rSrc))]>;
				1033
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1034	// 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
				1035	// quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
				1036	// pattern below). Intentionally doesn't match a pattern because we want the
				1037	// sext 8->32 pattern to do the work for us, namely because we need the extra
				1038	// XSHWr32.
				1039	def XSBHr32:
				1040	RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
				1041	"xsbh\t$rDst, $rSrc", IntegerOp,
				1042	[(set R32C:$rDst, (sext_inreg R32C:$rSrc, i8))]>;
				1043
				1044	// Sign extend halfwords to words:
				1045	def XSHWvec:
				1046	RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc),
				1047	"xshw\t$rDest, $rSrc", IntegerOp,
				1048	[(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>;
				1049
				1050	def XSHWr32:
				1051	RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
				1052	"xshw\t$rDst, $rSrc", IntegerOp,
				1053	[(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>;
				1054
				1055	def XSHWr16:
				1056	RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc),
				1057	"xshw\t$rDst, $rSrc", IntegerOp,
				1058	[(set R32C:$rDst, (sext R16C:$rSrc))]>;
				1059
				1060	def XSWDvec:
				1061	RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
				1062	"xswd\t$rDst, $rSrc", IntegerOp,
				1063	[(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>;
				1064
				1065	def XSWDr64:
				1066	RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc),
				1067	"xswd\t$rDst, $rSrc", IntegerOp,
				1068	[(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
				1069
				1070	def XSWDr32:
				1071	RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc),
				1072	"xswd\t$rDst, $rSrc", IntegerOp,
				1073	[(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>;
				1074
				1075	def : Pat<(sext R32C:$inp),
				1076	(XSWDr32 R32C:$inp)>;
				1077
				1078	// AND operations
				1079	def ANDv16i8:
				1080	RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1081	"and\t$rT, $rA, $rB", IntegerOp,
				1082	[(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA),
				1083	(v16i8 VECREG:$rB)))]>;
				1084
				1085	def ANDv8i16:
				1086	RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1087	"and\t$rT, $rA, $rB", IntegerOp,
				1088	[(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA),
				1089	(v8i16 VECREG:$rB)))]>;
				1090
				1091	def ANDv4i32:
				1092	RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1093	"and\t$rT, $rA, $rB", IntegerOp,
				1094	[(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA),
				1095	(v4i32 VECREG:$rB)))]>;
				1096
				1097	def ANDr32:
				1098	RRForm<0b10000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				1099	"and\t$rT, $rA, $rB", IntegerOp,
				1100	[(set R32C:$rT, (and R32C:$rA, R32C:$rB))]>;
				1101
				1102	//===---------------------------------------------
				1103	// Special instructions to perform the fabs instruction
				1104	def ANDfabs32:
				1105	RRForm<0b10000011000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
				1106	"and\t$rT, $rA, $rB", IntegerOp,
				1107	[/* Intentionally does not match a pattern */]>;
				1108
				1109	def ANDfabs64:
				1110	RRForm<0b10000011000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
				1111	"and\t$rT, $rA, $rB", IntegerOp,
				1112	[/* Intentionally does not match a pattern */]>;
				1113
				1114	// Could use ANDv4i32, but won't for clarity
				1115	def ANDfabsvec:
				1116	RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1117	"and\t$rT, $rA, $rB", IntegerOp,
				1118	[/* Intentionally does not match a pattern */]>;
				1119
				1120	//===---------------------------------------------
				1121
				1122	def ANDr16:
				1123	RRForm<0b10000011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				1124	"and\t$rT, $rA, $rB", IntegerOp,
				1125	[(set R16C:$rT, (and R16C:$rA, R16C:$rB))]>;
				1126
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1127	def ANDr8:
				1128	RRForm<0b10000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
				1129	"and\t$rT, $rA, $rB", IntegerOp,
				1130	[(set R8C:$rT, (and R8C:$rA, R8C:$rB))]>;
				1131
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1132	// Hacked form of AND to zero-extend 16-bit quantities to 32-bit
				1133	// quantities -- see 16->32 zext pattern.
				1134	//
				1135	// This pattern is somewhat artificial, since it might match some
				1136	// compiler generated pattern but it is unlikely to do so.
				1137	def AND2To4:
				1138	RRForm<0b10000011000, (outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
				1139	"and\t$rT, $rA, $rB", IntegerOp,
				1140	[(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
				1141
				1142	// N.B.: vnot_conv is one of those special target selection pattern fragments,
				1143	// in which we expect there to be a bit_convert on the constant. Bear in mind
				1144	// that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
				1145	// constant -1 vector.)
				1146	def ANDCv16i8:
				1147	RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1148	"andc\t$rT, $rA, $rB", IntegerOp,
				1149	[(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA),
				1150	(vnot (v16i8 VECREG:$rB))))]>;
				1151
				1152	def ANDCv8i16:
				1153	RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1154	"andc\t$rT, $rA, $rB", IntegerOp,
				1155	[(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA),
				1156	(vnot (v8i16 VECREG:$rB))))]>;
				1157
				1158	def ANDCv4i32:
				1159	RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1160	"andc\t$rT, $rA, $rB", IntegerOp,
				1161	[(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA),
				1162	(vnot (v4i32 VECREG:$rB))))]>;
				1163
				1164	def ANDCr32:
				1165	RRForm<0b10000011010, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				1166	"andc\t$rT, $rA, $rB", IntegerOp,
				1167	[(set R32C:$rT, (and R32C:$rA, (not R32C:$rB)))]>;
				1168
				1169	def ANDCr16:
				1170	RRForm<0b10000011010, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				1171	"andc\t$rT, $rA, $rB", IntegerOp,
				1172	[(set R16C:$rT, (and R16C:$rA, (not R16C:$rB)))]>;
				1173
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1174	def ANDCr8:
				1175	RRForm<0b10000011010, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
				1176	"andc\t$rT, $rA, $rB", IntegerOp,
				1177	[(set R8C:$rT, (and R8C:$rA, (not R8C:$rB)))]>;
				1178
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1179	def ANDBIv16i8:
				1180	RI10Form<0b01101000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
				1181	"andbi\t$rT, $rA, $val", IntegerOp,
				1182	[(set (v16i8 VECREG:$rT),
				1183	(and (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>;
				1184
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1185	def ANDBIr8:
				1186	RI10Form<0b01101000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
				1187	"andbi\t$rT, $rA, $val", IntegerOp,
				1188	[(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
				1189
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1190	def ANDHIv8i16:
				1191	RI10Form<0b10101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				1192	"andhi\t$rT, $rA, $val", IntegerOp,
				1193	[(set (v8i16 VECREG:$rT),
				1194	(and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
				1195
				1196	def ANDHIr16:
				1197	RI10Form<0b10101000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
				1198	"andhi\t$rT, $rA, $val", IntegerOp,
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1199	[(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
				1200
				1201	def ANDHI1To2:
				1202	RI10Form<0b10101000, (outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
				1203	"andhi\t$rT, $rA, $val", IntegerOp,
				1204	[(set R16C:$rT, (and (zext R8C:$rA), i16ImmSExt10:$val))]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1205
				1206	def ANDIv4i32:
				1207	RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				1208	"andi\t$rT, $rA, $val", IntegerOp,
				1209	[(set (v4i32 VECREG:$rT),
				1210	(and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
				1211
				1212	def ANDIr32:
				1213	RI10Form<0b10101000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
				1214	"andi\t$rT, $rA, $val", IntegerOp,
				1215	[(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
				1216
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1217	// Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
				1218	// pattern below.
				1219	def ANDI1To4:
				1220	RI10Form<0b10101000, (outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
				1221	"andi\t$rT, $rA, $val", IntegerOp,
				1222	[(set R32C:$rT, (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
				1223
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1224	// Hacked form of ANDI to zero-extend i16 quantities to i32. See the
				1225	// zext 16->32 pattern below.
				1226	//
				1227	// Note that this pattern is somewhat artificial, since it might match
				1228	// something the compiler generates but is unlikely to occur in practice.
				1229	def ANDI2To4:
				1230	RI10Form<0b10101000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
				1231	"andi\t$rT, $rA, $val", IntegerOp,
				1232	[(set R32C:$rT, (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
				1233
				1234	// Bitwise OR group:
				1235	// Bitwise "or" (N.B.: These are also register-register copy instructions...)
				1236	def ORv16i8:
				1237	RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1238	"or\t$rT, $rA, $rB", IntegerOp,
				1239	[(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
				1240
				1241	def ORv8i16:
				1242	RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1243	"or\t$rT, $rA, $rB", IntegerOp,
				1244	[(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
				1245
				1246	def ORv4i32:
				1247	RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1248	"or\t$rT, $rA, $rB", IntegerOp,
				1249	[(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
				1250
				1251	def ORv4f32:
				1252	RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1253	"or\t$rT, $rA, $rB", IntegerOp,
				1254	[(set (v4f32 VECREG:$rT),
				1255	(v4f32 (bitconvert (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))))]>;
				1256
				1257	def ORv2f64:
				1258	RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1259	"or\t$rT, $rA, $rB", IntegerOp,
				1260	[(set (v2f64 VECREG:$rT),
				1261	(v2f64 (bitconvert (or (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)))))]>;
				1262
				1263	def ORgprc:
				1264	RRForm<0b10000010000, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
				1265	"or\t$rT, $rA, $rB", IntegerOp,
				1266	[(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>;
				1267
				1268	def ORr64:
				1269	RRForm<0b10000010000, (outs R64C:$rT), (ins R64C:$rA, R64C:$rB),
				1270	"or\t$rT, $rA, $rB", IntegerOp,
				1271	[(set R64C:$rT, (or R64C:$rA, R64C:$rB))]>;
				1272
				1273	def ORr32:
				1274	RRForm<0b10000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				1275	"or\t$rT, $rA, $rB", IntegerOp,
				1276	[(set R32C:$rT, (or R32C:$rA, R32C:$rB))]>;
				1277
				1278	def ORr16:
				1279	RRForm<0b10000010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				1280	"or\t$rT, $rA, $rB", IntegerOp,
				1281	[(set R16C:$rT, (or R16C:$rA, R16C:$rB))]>;
				1282
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1283	def ORr8:
				1284	RRForm<0b10000010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
				1285	"or\t$rT, $rA, $rB", IntegerOp,
				1286	[(set R8C:$rT, (or R8C:$rA, R8C:$rB))]>;
				1287
Scott Michel	754d866	2007-12-20 00:44:13 +0000	[diff] [blame^]	1288	// OR instruction forms that are used to copy f32 and f64 registers.
				1289	// They do not match patterns.
				1290	def ORf32:
				1291	RRForm<0b10000010000, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
				1292	"or\t$rT, $rA, $rB", IntegerOp,
				1293	[/* no pattern */]>;
				1294
				1295	def ORf64:
				1296	RRForm<0b10000010000, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
				1297	"or\t$rT, $rA, $rB", IntegerOp,
				1298	[/* no pattern */]>;
				1299
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1300	// ORv_: Used in scalar->vector promotions:
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1301	def ORv16i8_i8:
				1302	RRForm<0b10000010000, (outs VECREG:$rT), (ins R8C:$rA, R8C:$rB),
				1303	"or\t$rT, $rA, $rB", IntegerOp,
				1304	[/* no pattern */]>;
				1305
				1306	def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)),
				1307	(ORv16i8_i8 R8C:$rA, R8C:$rA)>;
				1308
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1309	def ORv8i16_i16:
				1310	RRForm<0b10000010000, (outs VECREG:$rT), (ins R16C:$rA, R16C:$rB),
				1311	"or\t$rT, $rA, $rB", IntegerOp,
				1312	[/* no pattern */]>;
				1313
				1314	def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
				1315	(ORv8i16_i16 R16C:$rA, R16C:$rA)>;
				1316
				1317	def ORv4i32_i32:
				1318	RRForm<0b10000010000, (outs VECREG:$rT), (ins R32C:$rA, R32C:$rB),
				1319	"or\t$rT, $rA, $rB", IntegerOp,
				1320	[/* no pattern */]>;
				1321
				1322	def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
				1323	(ORv4i32_i32 R32C:$rA, R32C:$rA)>;
				1324
				1325	def ORv2i64_i64:
				1326	RRForm<0b10000010000, (outs VECREG:$rT), (ins R64C:$rA, R64C:$rB),
				1327	"or\t$rT, $rA, $rB", IntegerOp,
				1328	[/* no pattern */]>;
				1329
				1330	def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
				1331	(ORv2i64_i64 R64C:$rA, R64C:$rA)>;
				1332
				1333	def ORv4f32_f32:
				1334	RRForm<0b10000010000, (outs VECREG:$rT), (ins R32FP:$rA, R32FP:$rB),
				1335	"or\t$rT, $rA, $rB", IntegerOp,
				1336	[/* no pattern */]>;
				1337
				1338	def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
				1339	(ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
				1340
				1341	def ORv2f64_f64:
				1342	RRForm<0b10000010000, (outs VECREG:$rT), (ins R64FP:$rA, R64FP:$rB),
				1343	"or\t$rT, $rA, $rB", IntegerOp,
				1344	[/* no pattern */]>;
				1345
				1346	def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
				1347	(ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
				1348
				1349	// ORi_v: Used to extract vector element 0 (the preferred slot)
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1350	def ORi8_v16i8:
				1351	RRForm<0b10000010000, (outs R8C:$rT), (ins VECREG:$rA, VECREG:$rB),
				1352	"or\t$rT, $rA, $rB", IntegerOp,
				1353	[/* no pattern */]>;
				1354
				1355	def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)),
				1356	(ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
				1357
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1358	def ORi16_v8i16:
				1359	RRForm<0b10000010000, (outs R16C:$rT), (ins VECREG:$rA, VECREG:$rB),
				1360	"or\t$rT, $rA, $rB", IntegerOp,
				1361	[/* no pattern */]>;
				1362
				1363	def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)),
				1364	(ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
				1365
				1366	def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)),
				1367	(ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
				1368
				1369	def ORi32_v4i32:
				1370	RRForm<0b10000010000, (outs R32C:$rT), (ins VECREG:$rA, VECREG:$rB),
				1371	"or\t$rT, $rA, $rB", IntegerOp,
				1372	[/* no pattern */]>;
				1373
				1374	def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)),
				1375	(ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
				1376
				1377	def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)),
				1378	(ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
				1379
				1380	def ORi64_v2i64:
				1381	RRForm<0b10000010000, (outs R64C:$rT), (ins VECREG:$rA, VECREG:$rB),
				1382	"or\t$rT, $rA, $rB", IntegerOp,
				1383	[/* no pattern */]>;
				1384
				1385	def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)),
				1386	(ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
				1387
				1388	def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)),
				1389	(ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
				1390
				1391	def ORf32_v4f32:
				1392	RRForm<0b10000010000, (outs R32FP:$rT), (ins VECREG:$rA, VECREG:$rB),
				1393	"or\t$rT, $rA, $rB", IntegerOp,
				1394	[/* no pattern */]>;
				1395
				1396	def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)),
				1397	(ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
				1398
				1399	def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)),
				1400	(ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
				1401
				1402	def ORf64_v2f64:
				1403	RRForm<0b10000010000, (outs R64FP:$rT), (ins VECREG:$rA, VECREG:$rB),
				1404	"or\t$rT, $rA, $rB", IntegerOp,
				1405	[/* no pattern */]>;
				1406
				1407	def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)),
				1408	(ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
				1409
				1410	def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)),
				1411	(ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
				1412
				1413	// ORC: Bitwise "or" with complement (match before ORvec, ORr32)
				1414	def ORCv16i8:
				1415	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1416	"orc\t$rT, $rA, $rB", IntegerOp,
				1417	[(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA),
				1418	(vnot (v16i8 VECREG:$rB))))]>;
				1419
				1420	def ORCv8i16:
				1421	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1422	"orc\t$rT, $rA, $rB", IntegerOp,
				1423	[(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA),
				1424	(vnot (v8i16 VECREG:$rB))))]>;
				1425
				1426	def ORCv4i32:
				1427	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1428	"orc\t$rT, $rA, $rB", IntegerOp,
				1429	[(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA),
				1430	(vnot (v4i32 VECREG:$rB))))]>;
				1431
				1432	def ORCr32:
				1433	RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				1434	"orc\t$rT, $rA, $rB", IntegerOp,
				1435	[(set R32C:$rT, (or R32C:$rA, (not R32C:$rB)))]>;
				1436
				1437	def ORCr16:
				1438	RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				1439	"orc\t$rT, $rA, $rB", IntegerOp,
				1440	[(set R16C:$rT, (or R16C:$rA, (not R16C:$rB)))]>;
				1441
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1442	def ORCr8:
				1443	RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
				1444	"orc\t$rT, $rA, $rB", IntegerOp,
				1445	[(set R8C:$rT, (or R8C:$rA, (not R8C:$rB)))]>;
				1446
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1447	// OR byte immediate
				1448	def ORBIv16i8:
				1449	RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
				1450	"orbi\t$rT, $rA, $val", IntegerOp,
				1451	[(set (v16i8 VECREG:$rT),
				1452	(or (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>;
				1453
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1454	def ORBIr8:
				1455	RI10Form<0b01100000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
				1456	"orbi\t$rT, $rA, $val", IntegerOp,
				1457	[(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
				1458
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1459	// OR halfword immediate
				1460	def ORHIv8i16:
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1461	RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1462	"orhi\t$rT, $rA, $val", IntegerOp,
				1463	[(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA),
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1464	v8i16Uns10Imm:$val))]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1465
				1466	def ORHIr16:
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1467	RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1468	"orhi\t$rT, $rA, $val", IntegerOp,
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1469	[(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
				1470
				1471	// Hacked form of ORHI used to promote 8-bit registers to 16-bit
				1472	def ORHI1To2:
				1473	RI10Form<0b10100000, (outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
				1474	"orhi\t$rT, $rA, $val", IntegerOp,
				1475	[(set R16C:$rT, (or (anyext R8C:$rA), i16ImmSExt10:$val))]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1476
				1477	// Bitwise "or" with immediate
				1478	def ORIv4i32:
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1479	RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1480	"ori\t$rT, $rA, $val", IntegerOp,
				1481	[(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA),
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1482	v4i32Uns10Imm:$val))]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1483
				1484	def ORIr32:
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1485	RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1486	"ori\t$rT, $rA, $val", IntegerOp,
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1487	[(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1488
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1489	def ORIr64:
				1490	RI10Form_1<0b00100000, (outs R64C:$rT), (ins R64C:$rA, s10imm_i32:$val),
				1491	"ori\t$rT, $rA, $val", IntegerOp,
				1492	[/* no pattern */]>;
				1493
				1494	// ORI2To4: hacked version of the ori instruction to extend 16-bit quantities
				1495	// to 32-bit quantities. used exclusively to match "anyext" conversions (vide
				1496	// infra "anyext 16->32" pattern.)
				1497	def ORI2To4:
				1498	RI10Form<0b00100000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
				1499	"ori\t$rT, $rA, $val", IntegerOp,
				1500	[(set R32C:$rT, (or (anyext R16C:$rA), i32ImmSExt10:$val))]>;
				1501
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1502	// ORI1To4: Hacked version of the ORI instruction to extend 16-bit quantities
				1503	// to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
				1504	// infra "anyext 16->32" pattern.)
				1505	def ORI1To4:
				1506	RI10Form<0b00100000, (outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
				1507	"ori\t$rT, $rA, $val", IntegerOp,
				1508	[(set R32C:$rT, (or (anyext R8C:$rA), i32ImmSExt10:$val))]>;
				1509
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1510	// ORX: "or" across the vector: or's $rA's word slots leaving the result in
				1511	// $rT[0], slots 1-3 are zeroed.
				1512	//
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1513	// FIXME: Needs to match an intrinsic pattern.
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1514	def ORXv4i32:
				1515	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1516	"orx\t$rT, $rA, $rB", IntegerOp,
				1517	[]>;
				1518
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1519	// XOR:
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1520	def XORv16i8:
				1521	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1522	"xor\t$rT, $rA, $rB", IntegerOp,
				1523	[(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
				1524
				1525	def XORv8i16:
				1526	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1527	"xor\t$rT, $rA, $rB", IntegerOp,
				1528	[(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
				1529
				1530	def XORv4i32:
				1531	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1532	"xor\t$rT, $rA, $rB", IntegerOp,
				1533	[(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
				1534
				1535	def XORr32:
				1536	RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				1537	"xor\t$rT, $rA, $rB", IntegerOp,
				1538	[(set R32C:$rT, (xor R32C:$rA, R32C:$rB))]>;
				1539
				1540	//==----------------------------------------------------------
				1541	// Special forms for floating point instructions.
				1542	// Bitwise ORs and ANDs don't make sense for normal floating
				1543	// point numbers. These operations (fneg and fabs), however,
				1544	// require bitwise logical ops to manipulate the sign bit.
				1545	def XORfneg32:
				1546	RRForm<0b10010010000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
				1547	"xor\t$rT, $rA, $rB", IntegerOp,
				1548	[/* Intentionally does not match a pattern, see fneg32 */]>;
				1549
				1550	// KLUDGY! Better way to do this without a VECREG? bitconvert?
				1551	// VECREG is assumed to contain two identical 64-bit masks, so
				1552	// it doesn't matter which word we select for the xor
				1553	def XORfneg64:
				1554	RRForm<0b10010010000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
				1555	"xor\t$rT, $rA, $rB", IntegerOp,
				1556	[/* Intentionally does not match a pattern, see fneg64 */]>;
				1557
				1558	// Could use XORv4i32, but will use this for clarity
				1559	def XORfnegvec:
				1560	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1561	"xor\t$rT, $rA, $rB", IntegerOp,
				1562	[/* Intentionally does not match a pattern, see fneg{32,64} */]>;
				1563
				1564	//==----------------------------------------------------------
				1565
				1566	def XORr16:
				1567	RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				1568	"xor\t$rT, $rA, $rB", IntegerOp,
				1569	[(set R16C:$rT, (xor R16C:$rA, R16C:$rB))]>;
				1570
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1571	def XORr8:
				1572	RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
				1573	"xor\t$rT, $rA, $rB", IntegerOp,
				1574	[(set R8C:$rT, (xor R8C:$rA, R8C:$rB))]>;
				1575
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1576	def XORBIv16i8:
				1577	RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
				1578	"xorbi\t$rT, $rA, $val", IntegerOp,
				1579	[(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
				1580
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1581	def XORBIr8:
				1582	RI10Form<0b01100000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
				1583	"xorbi\t$rT, $rA, $val", IntegerOp,
				1584	[(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
				1585
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1586	def XORHIv8i16:
				1587	RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				1588	"xorhi\t$rT, $rA, $val", IntegerOp,
				1589	[(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
				1590	v8i16SExt10Imm:$val))]>;
				1591
				1592	def XORHIr16:
				1593	RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
				1594	"xorhi\t$rT, $rA, $val", IntegerOp,
				1595	[(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
				1596
				1597	def XORIv4i32:
				1598	RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				1599	"xori\t$rT, $rA, $val", IntegerOp,
				1600	[(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
				1601	v4i32SExt10Imm:$val))]>;
				1602
				1603	def XORIr32:
				1604	RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
				1605	"xori\t$rT, $rA, $val", IntegerOp,
				1606	[(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
				1607
				1608	// NAND:
				1609	def NANDv16i8:
				1610	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1611	"nand\t$rT, $rA, $rB", IntegerOp,
				1612	[(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
				1613	(v16i8 VECREG:$rB))))]>;
				1614
				1615	def NANDv8i16:
				1616	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1617	"nand\t$rT, $rA, $rB", IntegerOp,
				1618	[(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
				1619	(v8i16 VECREG:$rB))))]>;
				1620
				1621	def NANDv4i32:
				1622	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1623	"nand\t$rT, $rA, $rB", IntegerOp,
				1624	[(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
				1625	(v4i32 VECREG:$rB))))]>;
				1626
				1627	def NANDr32:
				1628	RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				1629	"nand\t$rT, $rA, $rB", IntegerOp,
				1630	[(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
				1631
				1632	def NANDr16:
				1633	RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				1634	"nand\t$rT, $rA, $rB", IntegerOp,
				1635	[(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
				1636
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1637	def NANDr8:
				1638	RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
				1639	"nand\t$rT, $rA, $rB", IntegerOp,
				1640	[(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>;
				1641
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1642	// NOR:
				1643	def NORv16i8:
				1644	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1645	"nor\t$rT, $rA, $rB", IntegerOp,
				1646	[(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
				1647	(v16i8 VECREG:$rB))))]>;
				1648
				1649	def NORv8i16:
				1650	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1651	"nor\t$rT, $rA, $rB", IntegerOp,
				1652	[(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
				1653	(v8i16 VECREG:$rB))))]>;
				1654
				1655	def NORv4i32:
				1656	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1657	"nor\t$rT, $rA, $rB", IntegerOp,
				1658	[(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
				1659	(v4i32 VECREG:$rB))))]>;
				1660
				1661	def NORr32:
				1662	RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				1663	"nor\t$rT, $rA, $rB", IntegerOp,
				1664	[(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
				1665
				1666	def NORr16:
				1667	RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				1668	"nor\t$rT, $rA, $rB", IntegerOp,
				1669	[(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
				1670
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1671	def NORr8:
				1672	RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
				1673	"nor\t$rT, $rA, $rB", IntegerOp,
				1674	[(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>;
				1675
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1676	// EQV: Equivalence (1 for each same bit, otherwise 0)
				1677	def EQVv16i8:
				1678	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1679	"eqv\t$rT, $rA, $rB", IntegerOp,
				1680	[(set (v16i8 VECREG:$rT), (or (and (v16i8 VECREG:$rA),
				1681	(v16i8 VECREG:$rB)),
				1682	(and (vnot (v16i8 VECREG:$rA)),
				1683	(vnot (v16i8 VECREG:$rB)))))]>;
				1684
				1685	def : Pat<(xor (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rB))),
				1686	(EQVv16i8 VECREG:$rA, VECREG:$rB)>;
				1687
				1688	def : Pat<(xor (vnot (v16i8 VECREG:$rA)), (v16i8 VECREG:$rB)),
				1689	(EQVv16i8 VECREG:$rA, VECREG:$rB)>;
				1690
				1691	def EQVv8i16:
				1692	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1693	"eqv\t$rT, $rA, $rB", IntegerOp,
				1694	[(set (v8i16 VECREG:$rT), (or (and (v8i16 VECREG:$rA),
				1695	(v8i16 VECREG:$rB)),
				1696	(and (vnot (v8i16 VECREG:$rA)),
				1697	(vnot (v8i16 VECREG:$rB)))))]>;
				1698
				1699	def : Pat<(xor (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rB))),
				1700	(EQVv8i16 VECREG:$rA, VECREG:$rB)>;
				1701
				1702	def : Pat<(xor (vnot (v8i16 VECREG:$rA)), (v8i16 VECREG:$rB)),
				1703	(EQVv8i16 VECREG:$rA, VECREG:$rB)>;
				1704
				1705	def EQVv4i32:
				1706	RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				1707	"eqv\t$rT, $rA, $rB", IntegerOp,
				1708	[(set (v4i32 VECREG:$rT), (or (and (v4i32 VECREG:$rA),
				1709	(v4i32 VECREG:$rB)),
				1710	(and (vnot (v4i32 VECREG:$rA)),
				1711	(vnot (v4i32 VECREG:$rB)))))]>;
				1712
				1713	def : Pat<(xor (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rB))),
				1714	(EQVv4i32 VECREG:$rA, VECREG:$rB)>;
				1715
				1716	def : Pat<(xor (vnot (v4i32 VECREG:$rA)), (v4i32 VECREG:$rB)),
				1717	(EQVv4i32 VECREG:$rA, VECREG:$rB)>;
				1718
				1719	def EQVr32:
				1720	RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				1721	"eqv\t$rT, $rA, $rB", IntegerOp,
				1722	[(set R32C:$rT, (or (and R32C:$rA, R32C:$rB),
				1723	(and (not R32C:$rA), (not R32C:$rB))))]>;
				1724
				1725	def : Pat<(xor R32C:$rA, (not R32C:$rB)),
				1726	(EQVr32 R32C:$rA, R32C:$rB)>;
				1727
				1728	def : Pat<(xor (not R32C:$rA), R32C:$rB),
				1729	(EQVr32 R32C:$rA, R32C:$rB)>;
				1730
				1731	def EQVr16:
				1732	RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				1733	"eqv\t$rT, $rA, $rB", IntegerOp,
				1734	[(set R16C:$rT, (or (and R16C:$rA, R16C:$rB),
				1735	(and (not R16C:$rA), (not R16C:$rB))))]>;
				1736
				1737	def : Pat<(xor R16C:$rA, (not R16C:$rB)),
				1738	(EQVr16 R16C:$rA, R16C:$rB)>;
				1739
				1740	def : Pat<(xor (not R16C:$rA), R16C:$rB),
				1741	(EQVr16 R16C:$rA, R16C:$rB)>;
				1742
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1743	def EQVr8:
				1744	RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
				1745	"eqv\t$rT, $rA, $rB", IntegerOp,
				1746	[(set R8C:$rT, (or (and R8C:$rA, R8C:$rB),
				1747	(and (not R8C:$rA), (not R8C:$rB))))]>;
				1748
				1749	def : Pat<(xor R8C:$rA, (not R8C:$rB)),
				1750	(EQVr8 R8C:$rA, R8C:$rB)>;
				1751
				1752	def : Pat<(xor (not R8C:$rA), R8C:$rB),
				1753	(EQVr8 R8C:$rA, R8C:$rB)>;
				1754
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1755	// gcc optimizes (p & q) \| (~p & ~q) -> ~(p \| q) \| (p & q), so match that
				1756	// pattern also:
				1757	def : Pat<(or (vnot (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))),
				1758	(and (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))),
				1759	(EQVv16i8 VECREG:$rA, VECREG:$rB)>;
				1760
				1761	def : Pat<(or (vnot (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))),
				1762	(and (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))),
				1763	(EQVv8i16 VECREG:$rA, VECREG:$rB)>;
				1764
				1765	def : Pat<(or (vnot (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))),
				1766	(and (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))),
				1767	(EQVv4i32 VECREG:$rA, VECREG:$rB)>;
				1768
				1769	def : Pat<(or (not (or R32C:$rA, R32C:$rB)), (and R32C:$rA, R32C:$rB)),
				1770	(EQVr32 R32C:$rA, R32C:$rB)>;
				1771
				1772	def : Pat<(or (not (or R16C:$rA, R16C:$rB)), (and R16C:$rA, R16C:$rB)),
				1773	(EQVr16 R16C:$rA, R16C:$rB)>;
				1774
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	1775	def : Pat<(or (not (or R8C:$rA, R8C:$rB)), (and R8C:$rA, R8C:$rB)),
				1776	(EQVr8 R8C:$rA, R8C:$rB)>;
				1777
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	1778	// Select bits:
				1779	def SELBv16i8:
				1780	RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				1781	"selb\t$rT, $rA, $rB, $rC", IntegerOp,
				1782	[(set (v16i8 VECREG:$rT),
				1783	(SPUselb_v16i8 (v16i8 VECREG:$rA), (v16i8 VECREG:$rB),
				1784	(v16i8 VECREG:$rC)))]>;
				1785
				1786	def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
				1787	(and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
				1788	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1789
				1790	def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
				1791	(and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
				1792	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1793
				1794	def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
				1795	(and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
				1796	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1797
				1798	def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
				1799	(and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
				1800	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1801
				1802	def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
				1803	(and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
				1804	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1805
				1806	def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
				1807	(and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
				1808	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1809
				1810	def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
				1811	(and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
				1812	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1813
				1814	def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
				1815	(and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
				1816	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1817
				1818	def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
				1819	(and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
				1820	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1821
				1822	def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
				1823	(and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
				1824	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1825
				1826	def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
				1827	(and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
				1828	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1829
				1830	def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
				1831	(and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
				1832	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1833
				1834	def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
				1835	(and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
				1836	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1837
				1838	def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
				1839	(and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
				1840	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1841
				1842	def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
				1843	(and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
				1844	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1845
				1846	def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
				1847	(and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
				1848	(SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1849
				1850	def SELBv8i16:
				1851	RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				1852	"selb\t$rT, $rA, $rB, $rC", IntegerOp,
				1853	[(set (v8i16 VECREG:$rT),
				1854	(SPUselb_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB),
				1855	(v8i16 VECREG:$rC)))]>;
				1856
				1857	def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
				1858	(and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
				1859	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1860
				1861	def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
				1862	(and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
				1863	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1864
				1865	def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
				1866	(and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
				1867	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1868
				1869	def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
				1870	(and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
				1871	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1872
				1873	def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
				1874	(and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
				1875	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1876
				1877	def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
				1878	(and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
				1879	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1880
				1881	def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
				1882	(and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
				1883	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1884
				1885	def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
				1886	(and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
				1887	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1888
				1889	def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
				1890	(and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
				1891	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1892
				1893	def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
				1894	(and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
				1895	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1896
				1897	def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
				1898	(and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
				1899	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1900
				1901	def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
				1902	(and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
				1903	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1904
				1905	def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
				1906	(and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
				1907	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1908
				1909	def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
				1910	(and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
				1911	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1912
				1913	def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
				1914	(and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
				1915	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1916
				1917	def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
				1918	(and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
				1919	(SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1920
				1921	def SELBv4i32:
				1922	RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				1923	"selb\t$rT, $rA, $rB, $rC", IntegerOp,
				1924	[(set (v4i32 VECREG:$rT),
				1925	(SPUselb_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB),
				1926	(v4i32 VECREG:$rC)))]>;
				1927
				1928	def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
				1929	(and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
				1930	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1931
				1932	def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
				1933	(and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
				1934	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1935
				1936	def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
				1937	(and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
				1938	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1939
				1940	def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
				1941	(and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
				1942	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1943
				1944	def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
				1945	(and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
				1946	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1947
				1948	def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
				1949	(and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
				1950	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1951
				1952	def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
				1953	(and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
				1954	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1955
				1956	def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
				1957	(and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
				1958	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1959
				1960	def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
				1961	(and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
				1962	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1963
				1964	def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
				1965	(and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
				1966	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1967
				1968	def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
				1969	(and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
				1970	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1971
				1972	def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
				1973	(and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
				1974	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1975
				1976	def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
				1977	(and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
				1978	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1979
				1980	def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
				1981	(and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
				1982	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1983
				1984	def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
				1985	(and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
				1986	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1987
				1988	def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
				1989	(and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
				1990	(SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				1991
				1992	def SELBr32:
				1993	RRRForm<0b1000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
				1994	"selb\t$rT, $rA, $rB, $rC", IntegerOp,
				1995	[]>;
				1996
				1997	// And the various patterns that can be matched... (all 8 of them :-)
				1998	def : Pat<(or (and R32C:$rA, R32C:$rC),
				1999	(and R32C:$rB, (not R32C:$rC))),
				2000	(SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
				2001
				2002	def : Pat<(or (and R32C:$rC, R32C:$rA),
				2003	(and R32C:$rB, (not R32C:$rC))),
				2004	(SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
				2005
				2006	def : Pat<(or (and R32C:$rA, R32C:$rC),
				2007	(and (not R32C:$rC), R32C:$rB)),
				2008	(SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
				2009
				2010	def : Pat<(or (and R32C:$rC, R32C:$rA),
				2011	(and (not R32C:$rC), R32C:$rB)),
				2012	(SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
				2013
				2014	def : Pat<(or (and R32C:$rA, (not R32C:$rC)),
				2015	(and R32C:$rB, R32C:$rC)),
				2016	(SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
				2017
				2018	def : Pat<(or (and R32C:$rA, (not R32C:$rC)),
				2019	(and R32C:$rC, R32C:$rB)),
				2020	(SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
				2021
				2022	def : Pat<(or (and (not R32C:$rC), R32C:$rA),
				2023	(and R32C:$rB, R32C:$rC)),
				2024	(SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
				2025
				2026	def : Pat<(or (and (not R32C:$rC), R32C:$rA),
				2027	(and R32C:$rC, R32C:$rB)),
				2028	(SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
				2029
				2030	def SELBr16:
				2031	RRRForm<0b1000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB, R16C:$rC),
				2032	"selb\t$rT, $rA, $rB, $rC", IntegerOp,
				2033	[]>;
				2034
				2035	def : Pat<(or (and R16C:$rA, R16C:$rC),
				2036	(and R16C:$rB, (not R16C:$rC))),
				2037	(SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
				2038
				2039	def : Pat<(or (and R16C:$rC, R16C:$rA),
				2040	(and R16C:$rB, (not R16C:$rC))),
				2041	(SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
				2042
				2043	def : Pat<(or (and R16C:$rA, R16C:$rC),
				2044	(and (not R16C:$rC), R16C:$rB)),
				2045	(SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
				2046
				2047	def : Pat<(or (and R16C:$rC, R16C:$rA),
				2048	(and (not R16C:$rC), R16C:$rB)),
				2049	(SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
				2050
				2051	def : Pat<(or (and R16C:$rA, (not R16C:$rC)),
				2052	(and R16C:$rB, R16C:$rC)),
				2053	(SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
				2054
				2055	def : Pat<(or (and R16C:$rA, (not R16C:$rC)),
				2056	(and R16C:$rC, R16C:$rB)),
				2057	(SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
				2058
				2059	def : Pat<(or (and (not R16C:$rC), R16C:$rA),
				2060	(and R16C:$rB, R16C:$rC)),
				2061	(SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
				2062
				2063	def : Pat<(or (and (not R16C:$rC), R16C:$rA),
				2064	(and R16C:$rC, R16C:$rB)),
				2065	(SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2066
				2067	def SELBr8:
				2068	RRRForm<0b1000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB, R8C:$rC),
				2069	"selb\t$rT, $rA, $rB, $rC", IntegerOp,
				2070	[]>;
				2071
				2072	def : Pat<(or (and R8C:$rA, R8C:$rC),
				2073	(and R8C:$rB, (not R8C:$rC))),
				2074	(SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
				2075
				2076	def : Pat<(or (and R8C:$rC, R8C:$rA),
				2077	(and R8C:$rB, (not R8C:$rC))),
				2078	(SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
				2079
				2080	def : Pat<(or (and R8C:$rA, R8C:$rC),
				2081	(and (not R8C:$rC), R8C:$rB)),
				2082	(SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
				2083
				2084	def : Pat<(or (and R8C:$rC, R8C:$rA),
				2085	(and (not R8C:$rC), R8C:$rB)),
				2086	(SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
				2087
				2088	def : Pat<(or (and R8C:$rA, (not R8C:$rC)),
				2089	(and R8C:$rB, R8C:$rC)),
				2090	(SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
				2091
				2092	def : Pat<(or (and R8C:$rA, (not R8C:$rC)),
				2093	(and R8C:$rC, R8C:$rB)),
				2094	(SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
				2095
				2096	def : Pat<(or (and (not R8C:$rC), R8C:$rA),
				2097	(and R8C:$rB, R8C:$rC)),
				2098	(SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
				2099
				2100	def : Pat<(or (and (not R8C:$rC), R8C:$rA),
				2101	(and R8C:$rC, R8C:$rB)),
				2102	(SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2103
				2104	//===----------------------------------------------------------------------===//
				2105	// Vector shuffle...
				2106	//===----------------------------------------------------------------------===//
				2107
				2108	def SHUFB:
				2109	RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				2110	"shufb\t$rT, $rA, $rB, $rC", IntegerOp,
Scott Michel	754d866	2007-12-20 00:44:13 +0000	[diff] [blame^]	2111	[/* no pattern */]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2112
				2113	// SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
				2114	// See the SPUshuffle SDNode operand above, which sets up the DAG pattern
				2115	// matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
				2116	// the SPUISD::SHUFB opcode.
				2117	def : Pat<(SPUshuffle (v16i8 VECREG:$rA), (v16i8 VECREG:$rB), VECREG:$rC),
				2118	(SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				2119
				2120	def : Pat<(SPUshuffle (v8i16 VECREG:$rA), (v8i16 VECREG:$rB), VECREG:$rC),
				2121	(SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				2122
				2123	def : Pat<(SPUshuffle (v4i32 VECREG:$rA), (v4i32 VECREG:$rB), VECREG:$rC),
				2124	(SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				2125
Scott Michel	754d866	2007-12-20 00:44:13 +0000	[diff] [blame^]	2126	def : Pat<(SPUshuffle (v4f32 VECREG:$rA), (v4f32 VECREG:$rB), VECREG:$rC),
				2127	(SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				2128
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2129	def : Pat<(SPUshuffle (v2i64 VECREG:$rA), (v2i64 VECREG:$rB), VECREG:$rC),
				2130	(SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				2131
Scott Michel	754d866	2007-12-20 00:44:13 +0000	[diff] [blame^]	2132	def : Pat<(SPUshuffle (v2f64 VECREG:$rA), (v2f64 VECREG:$rB), VECREG:$rC),
				2133	(SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				2134
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2135	//===----------------------------------------------------------------------===//
				2136	// Shift and rotate group:
				2137	//===----------------------------------------------------------------------===//
				2138
				2139	def SHLHv8i16:
				2140	RRForm<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
				2141	"shlh\t$rT, $rA, $rB", RotateShift,
				2142	[(set (v8i16 VECREG:$rT),
				2143	(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), R16C:$rB))]>;
				2144
				2145	// $rB gets promoted to 32-bit register type when confronted with
				2146	// this llvm assembly code:
				2147	//
				2148	// define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
				2149	// %A = shl i16 %arg1, %arg2
				2150	// ret i16 %A
				2151	// }
				2152	//
				2153	// However, we will generate this code when lowering 8-bit shifts and rotates.
				2154
				2155	def SHLHr16:
				2156	RRForm<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				2157	"shlh\t$rT, $rA, $rB", RotateShift,
				2158	[(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
				2159
				2160	def SHLHr16_r32:
				2161	RRForm<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
				2162	"shlh\t$rT, $rA, $rB", RotateShift,
				2163	[(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
				2164
				2165	def SHLHIv8i16:
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2166	RI7Form<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2167	"shlhi\t$rT, $rA, $val", RotateShift,
				2168	[(set (v8i16 VECREG:$rT),
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2169	(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i8 uimm7:$val)))]>;
				2170
				2171	def : Pat<(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i16 uimm7:$val)),
				2172	(SHLHIv8i16 VECREG:$rA, imm:$val)>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2173
				2174	def : Pat<(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val)),
				2175	(SHLHIv8i16 VECREG:$rA, imm:$val)>;
				2176
				2177	def SHLHIr16:
				2178	RI7Form<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
				2179	"shlhi\t$rT, $rA, $val", RotateShift,
				2180	[(set R16C:$rT, (shl R16C:$rA, (i32 uimm7:$val)))]>;
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2181
				2182	def : Pat<(shl R16C:$rA, (i8 uimm7:$val)),
				2183	(SHLHIr16 R16C:$rA, uimm7:$val)>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2184
				2185	def : Pat<(shl R16C:$rA, (i16 uimm7:$val)),
				2186	(SHLHIr16 R16C:$rA, uimm7:$val)>;
				2187
				2188	def SHLv4i32:
				2189	RRForm<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
				2190	"shl\t$rT, $rA, $rB", RotateShift,
				2191	[(set (v4i32 VECREG:$rT),
				2192	(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), R16C:$rB))]>;
				2193
				2194	def SHLr32:
				2195	RRForm<0b11111010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				2196	"shl\t$rT, $rA, $rB", RotateShift,
				2197	[(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
				2198
				2199	def SHLIv4i32:
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2200	RI7Form<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2201	"shli\t$rT, $rA, $val", RotateShift,
				2202	[(set (v4i32 VECREG:$rT),
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2203	(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i8 uimm7:$val)))]>;
				2204
				2205	def: Pat<(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i16 uimm7:$val)),
				2206	(SHLIv4i32 VECREG:$rA, uimm7:$val)>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2207
				2208	def: Pat<(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i32 uimm7:$val)),
				2209	(SHLIv4i32 VECREG:$rA, uimm7:$val)>;
				2210
				2211	def SHLIr32:
				2212	RI7Form<0b11111010000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
				2213	"shli\t$rT, $rA, $val", RotateShift,
				2214	[(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
				2215
				2216	def : Pat<(shl R32C:$rA, (i16 uimm7:$val)),
				2217	(SHLIr32 R32C:$rA, uimm7:$val)>;
				2218
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2219	def : Pat<(shl R32C:$rA, (i8 uimm7:$val)),
				2220	(SHLIr32 R32C:$rA, uimm7:$val)>;
				2221
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2222	// SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
				2223	// register) to the left. Vector form is here to ensure type correctness.
				2224	def SHLQBIvec:
				2225	RRForm<0b11011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2226	"shlqbi\t$rT, $rA, $rB", RotateShift,
				2227	[/* intrinsic */]>;
				2228
				2229	// See note above on SHLQBI.
				2230	def SHLQBIIvec:
				2231	RI7Form<0b11011111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
				2232	"shlqbii\t$rT, $rA, $val", RotateShift,
				2233	[/* intrinsic */]>;
				2234
				2235	// SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
				2236	// not by bits.
				2237	def SHLQBYvec:
				2238	RI7Form<0b11111011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2239	"shlqbyi\t$rT, $rA, $rB", RotateShift,
				2240	[/* intrinsic */]>;
				2241
				2242	def SHLQBYIvec:
				2243	RI7Form<0b11111111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
				2244	"shlqbyi\t$rT, $rA, $val", RotateShift,
				2245	[/* intrinsic */]>;
				2246
				2247	// ROTH v8i16 form:
				2248	def ROTHv8i16:
				2249	RRForm<0b00111010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2250	"roth\t$rT, $rA, $rB", RotateShift,
				2251	[(set (v8i16 VECREG:$rT),
				2252	(SPUvec_rotl_v8i16 VECREG:$rA, VECREG:$rB))]>;
				2253
				2254	def ROTHr16:
				2255	RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				2256	"roth\t$rT, $rA, $rB", RotateShift,
				2257	[(set R16C:$rT, (rotl R16C:$rA, R16C:$rB))]>;
				2258
				2259	def ROTHr16_r32:
				2260	RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
				2261	"roth\t$rT, $rA, $rB", RotateShift,
				2262	[(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
				2263
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2264	// The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
				2265	// 32-bit register
				2266	def ROTHr16_r8:
				2267	RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R8C:$rB),
				2268	"roth\t$rT, $rA, $rB", RotateShift,
				2269	[(set R16C:$rT, (rotl R16C:$rA, (i32 (zext R8C:$rB))))]>;
				2270
				2271	def : Pat<(rotl R16C:$rA, (i32 (sext R8C:$rB))),
				2272	(ROTHr16_r8 R16C:$rA, R8C:$rB)>;
				2273
				2274	def : Pat<(rotl R16C:$rA, (i32 (zext R8C:$rB))),
				2275	(ROTHr16_r8 R16C:$rA, R8C:$rB)>;
				2276
				2277	def : Pat<(rotl R16C:$rA, (i32 (anyext R8C:$rB))),
				2278	(ROTHr16_r8 R16C:$rA, R8C:$rB)>;
				2279
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2280	def ROTHIv8i16:
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2281	RI7Form<0b00111110000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2282	"rothi\t$rT, $rA, $val", RotateShift,
				2283	[(set (v8i16 VECREG:$rT),
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2284	(SPUvec_rotl_v8i16 VECREG:$rA, (i8 uimm7:$val)))]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2285
				2286	def : Pat<(SPUvec_rotl_v8i16 VECREG:$rA, (i16 uimm7:$val)),
				2287	(ROTHIv8i16 VECREG:$rA, imm:$val)>;
				2288
				2289	def : Pat<(SPUvec_rotl_v8i16 VECREG:$rA, (i32 uimm7:$val)),
				2290	(ROTHIv8i16 VECREG:$rA, imm:$val)>;
				2291
				2292	def ROTHIr16:
				2293	RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
				2294	"rothi\t$rT, $rA, $val", RotateShift,
				2295	[(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
				2296
				2297	def ROTHIr16_i32:
				2298	RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
				2299	"rothi\t$rT, $rA, $val", RotateShift,
				2300	[(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
				2301
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2302	def ROTHIr16_i8:
				2303	RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i8:$val),
				2304	"rothi\t$rT, $rA, $val", RotateShift,
				2305	[(set R16C:$rT, (rotl R16C:$rA, (i8 uimm7:$val)))]>;
				2306
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2307	def ROTv4i32:
				2308	RRForm<0b00011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
				2309	"rot\t$rT, $rA, $rB", RotateShift,
				2310	[(set (v4i32 VECREG:$rT),
				2311	(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), R32C:$rB))]>;
				2312
				2313	def ROTr32:
				2314	RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				2315	"rot\t$rT, $rA, $rB", RotateShift,
				2316	[(set R32C:$rT, (rotl R32C:$rA, R32C:$rB))]>;
				2317
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2318	// The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
				2319	// 32-bit register
				2320	def ROTr32_r16_anyext:
				2321	RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
				2322	"rot\t$rT, $rA, $rB", RotateShift,
				2323	[(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
				2324
				2325	def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
				2326	(ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
				2327
				2328	def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
				2329	(ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
				2330
				2331	def ROTr32_r8_anyext:
				2332	RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
				2333	"rot\t$rT, $rA, $rB", RotateShift,
				2334	[(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
				2335
				2336	def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
				2337	(ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
				2338
				2339	def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
				2340	(ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
				2341
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2342	def ROTIv4i32:
				2343	RI7Form<0b00011110000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
				2344	"roti\t$rT, $rA, $val", RotateShift,
				2345	[(set (v4i32 VECREG:$rT),
				2346	(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
				2347
				2348	def : Pat<(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i16 uimm7:$val)),
				2349	(ROTIv4i32 VECREG:$rA, imm:$val)>;
				2350
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2351	def : Pat<(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i8 uimm7:$val)),
				2352	(ROTIv4i32 VECREG:$rA, imm:$val)>;
				2353
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2354	def ROTIr32:
				2355	RI7Form<0b00011110000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
				2356	"roti\t$rT, $rA, $val", RotateShift,
				2357	[(set R32C:$rT, (rotl R32C:$rA, (i32 uimm7:$val)))]>;
				2358
				2359	def ROTIr32_i16:
				2360	RI7Form<0b00111110000, (outs R32C:$rT), (ins R32C:$rA, u7imm:$val),
				2361	"roti\t$rT, $rA, $val", RotateShift,
				2362	[(set R32C:$rT, (rotl R32C:$rA, (i16 uimm7:$val)))]>;
				2363
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2364	def ROTIr32_i8:
				2365	RI7Form<0b00111110000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i8:$val),
				2366	"roti\t$rT, $rA, $val", RotateShift,
				2367	[(set R32C:$rT, (rotl R32C:$rA, (i8 uimm7:$val)))]>;
				2368
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2369	// ROTQBY* vector forms: This rotates the entire vector, but vector registers
				2370	// are used here for type checking (instances where ROTQBI is used actually
				2371	// use vector registers)
				2372	def ROTQBYvec:
				2373	RRForm<0b00111011100, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
				2374	"rotqby\t$rT, $rA, $rB", RotateShift,
				2375	[(set (v16i8 VECREG:$rT), (SPUrotbytes_left (v16i8 VECREG:$rA), R16C:$rB))]>;
				2376
				2377	def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R16C:$rB),
				2378	(ROTQBYvec VECREG:$rA, R16C:$rB)>;
				2379
				2380	// See ROTQBY note above.
				2381	def ROTQBYIvec:
				2382	RI7Form<0b00111111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
				2383	"rotqbyi\t$rT, $rA, $val", RotateShift,
				2384	[(set (v16i8 VECREG:$rT),
				2385	(SPUrotbytes_left (v16i8 VECREG:$rA), (i16 uimm7:$val)))]>;
				2386
				2387	def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
				2388	(ROTQBYIvec VECREG:$rA, uimm7:$val)>;
				2389
				2390	// See ROTQBY note above.
				2391	def ROTQBYBIvec:
				2392	RI7Form<0b00110011100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
				2393	"rotqbybi\t$rT, $rA, $val", RotateShift,
				2394	[/* intrinsic */]>;
				2395
				2396	// See ROTQBY note above.
				2397	//
				2398	// Assume that the user of this instruction knows to shift the rotate count
				2399	// into bit 29
				2400	def ROTQBIvec:
				2401	RRForm<0b00011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2402	"rotqbi\t$rT, $rA, $rB", RotateShift,
				2403	[/* insert intrinsic here */]>;
				2404
				2405	// See ROTQBY note above.
				2406	def ROTQBIIvec:
				2407	RI7Form<0b00011111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
				2408	"rotqbii\t$rT, $rA, $val", RotateShift,
				2409	[/* insert intrinsic here */]>;
				2410
				2411	// ROTHM v8i16 form:
				2412	// NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
				2413	// so this only matches a synthetically generated/lowered code
				2414	// fragment.
				2415	// NOTE(2): $rB must be negated before the right rotate!
				2416	def ROTHMv8i16:
				2417	RRForm<0b10111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
				2418	"rothm\t$rT, $rA, $rB", RotateShift,
				2419	[/* see patterns below - $rB must be negated */]>;
				2420
				2421	def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R32C:$rB),
				2422	(ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
				2423
				2424	def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R16C:$rB),
				2425	(ROTHMv8i16 VECREG:$rA,
				2426	(SFIr32 (XSHWr16 R16C:$rB), 0))>;
				2427
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2428	def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R8C:$rB),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2429	(ROTHMv8i16 VECREG:$rA,
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2430	(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2431
				2432	// ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
				2433	// Note: This instruction doesn't match a pattern because rB must be negated
				2434	// for the instruction to work. Thus, the pattern below the instruction!
				2435	def ROTHMr16:
				2436	RRForm<0b10111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
				2437	"rothm\t$rT, $rA, $rB", RotateShift,
				2438	[/* see patterns below - $rB must be negated! */]>;
				2439
				2440	def : Pat<(srl R16C:$rA, R32C:$rB),
				2441	(ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
				2442
				2443	def : Pat<(srl R16C:$rA, R16C:$rB),
				2444	(ROTHMr16 R16C:$rA,
				2445	(SFIr32 (XSHWr16 R16C:$rB), 0))>;
				2446
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2447	def : Pat<(srl R16C:$rA, R8C:$rB),
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2448	(ROTHMr16 R16C:$rA,
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2449	(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2450
				2451	// ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
				2452	// that the immediate can be complemented, so that the user doesn't have to
				2453	// worry about it.
				2454	def ROTHMIv8i16:
				2455	RI7Form<0b10111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
				2456	"rothmi\t$rT, $rA, $val", RotateShift,
				2457	[(set (v8i16 VECREG:$rT),
				2458	(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i32 imm:$val)))]>;
				2459
				2460	def: Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i16 imm:$val)),
				2461	(ROTHMIv8i16 VECREG:$rA, imm:$val)>;
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2462
				2463	def: Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i8 imm:$val)),
				2464	(ROTHMIv8i16 VECREG:$rA, imm:$val)>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2465
				2466	def ROTHMIr16:
				2467	RI7Form<0b10111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
				2468	"rothmi\t$rT, $rA, $val", RotateShift,
				2469	[(set R16C:$rT, (srl R16C:$rA, (i32 uimm7:$val)))]>;
				2470
				2471	def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
				2472	(ROTHMIr16 R16C:$rA, uimm7:$val)>;
				2473
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2474	def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
				2475	(ROTHMIr16 R16C:$rA, uimm7:$val)>;
				2476
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2477	// ROTM v4i32 form: See the ROTHM v8i16 comments.
				2478	def ROTMv4i32:
				2479	RRForm<0b10011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
				2480	"rotm\t$rT, $rA, $rB", RotateShift,
				2481	[/* see patterns below - $rB must be negated */]>;
				2482
				2483	def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, R32C:$rB),
				2484	(ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
				2485
				2486	def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, R16C:$rB),
				2487	(ROTMv4i32 VECREG:$rA,
				2488	(SFIr32 (XSHWr16 R16C:$rB), 0))>;
				2489
				2490	def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, /* R8C */ R16C:$rB),
				2491	(ROTMv4i32 VECREG:$rA,
				2492	(SFIr32 (XSHWr16 /* (XSBHr8 R8C / R16C:$rB) /)*/, 0))>;
				2493
				2494	def ROTMr32:
				2495	RRForm<0b10011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				2496	"rotm\t$rT, $rA, $rB", RotateShift,
				2497	[/* see patterns below - $rB must be negated */]>;
				2498
				2499	def : Pat<(srl R32C:$rA, R32C:$rB),
				2500	(ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
				2501
				2502	def : Pat<(srl R32C:$rA, R16C:$rB),
				2503	(ROTMr32 R32C:$rA,
				2504	(SFIr32 (XSHWr16 R16C:$rB), 0))>;
				2505
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2506	def : Pat<(srl R32C:$rA, R8C:$rB),
				2507	(ROTMr32 R32C:$rA,
				2508	(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
				2509
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2510	// ROTMI v4i32 form: See the comment for ROTHM v8i16.
				2511	def ROTMIv4i32:
				2512	RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
				2513	"rotmi\t$rT, $rA, $val", RotateShift,
				2514	[(set (v4i32 VECREG:$rT),
				2515	(SPUvec_srl_v4i32 VECREG:$rA, (i32 uimm7:$val)))]>;
				2516
				2517	def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, (i16 uimm7:$val)),
				2518	(ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2519
				2520	def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, (i8 uimm7:$val)),
				2521	(ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2522
				2523	// ROTMI r32 form: know how to complement the immediate value.
				2524	def ROTMIr32:
				2525	RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
				2526	"rotmi\t$rT, $rA, $val", RotateShift,
				2527	[(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
				2528
				2529	def : Pat<(srl R32C:$rA, (i16 imm:$val)),
				2530	(ROTMIr32 R32C:$rA, uimm7:$val)>;
				2531
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2532	def : Pat<(srl R32C:$rA, (i8 imm:$val)),
				2533	(ROTMIr32 R32C:$rA, uimm7:$val)>;
				2534
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2535	// ROTQMBYvec: This is a vector form merely so that when used in an
				2536	// instruction pattern, type checking will succeed. This instruction assumes
				2537	// that the user knew to complement $rB.
				2538	def ROTQMBYvec:
				2539	RRForm<0b10111011100, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
				2540	"rotqmby\t$rT, $rA, $rB", RotateShift,
				2541	[(set (v16i8 VECREG:$rT),
				2542	(SPUrotbytes_right_zfill (v16i8 VECREG:$rA), R32C:$rB))]>;
				2543
				2544	def ROTQMBYIvec:
				2545	RI7Form<0b10111111100, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
				2546	"rotqmbyi\t$rT, $rA, $val", RotateShift,
				2547	[(set (v16i8 VECREG:$rT),
				2548	(SPUrotbytes_right_zfill (v16i8 VECREG:$rA), (i32 uimm7:$val)))]>;
				2549
				2550	def : Pat<(SPUrotbytes_right_zfill VECREG:$rA, (i16 uimm7:$val)),
				2551	(ROTQMBYIvec VECREG:$rA, uimm7:$val)>;
				2552
				2553	def ROTQMBYBIvec:
				2554	RRForm<0b10110011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2555	"rotqmbybi\t$rT, $rA, $rB", RotateShift,
				2556	[/* intrinsic */]>;
				2557
				2558	def ROTQMBIvec:
				2559	RRForm<0b10011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2560	"rotqmbi\t$rT, $rA, $rB", RotateShift,
				2561	[/* intrinsic */]>;
				2562
				2563	def ROTQMBIIvec:
				2564	RI7Form<0b10011111100, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
				2565	"rotqmbii\t$rT, $rA, $val", RotateShift,
				2566	[/* intrinsic */]>;
				2567
				2568	def ROTMAHv8i16:
				2569	RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
				2570	"rotmah\t$rT, $rA, $rB", RotateShift,
				2571	[/* see patterns below - $rB must be negated */]>;
				2572
				2573	def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R32C:$rB),
				2574	(ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
				2575
				2576	def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R16C:$rB),
				2577	(ROTMAHv8i16 VECREG:$rA,
				2578	(SFIr32 (XSHWr16 R16C:$rB), 0))>;
				2579
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2580	def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R8C:$rB),
				2581	(ROTMAHv8i16 VECREG:$rA,
				2582	(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
				2583
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2584	def ROTMAHr16:
				2585	RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
				2586	"rotmah\t$rT, $rA, $rB", RotateShift,
				2587	[/* see patterns below - $rB must be negated */]>;
				2588
				2589	def : Pat<(sra R16C:$rA, R32C:$rB),
				2590	(ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
				2591
				2592	def : Pat<(sra R16C:$rA, R16C:$rB),
				2593	(ROTMAHr16 R16C:$rA,
				2594	(SFIr32 (XSHWr16 R16C:$rB), 0))>;
				2595
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2596	def : Pat<(sra R16C:$rA, R8C:$rB),
				2597	(ROTMAHr16 R16C:$rA,
				2598	(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
				2599
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2600	def ROTMAHIv8i16:
				2601	RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
				2602	"rotmahi\t$rT, $rA, $val", RotateShift,
				2603	[(set (v8i16 VECREG:$rT),
				2604	(SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
				2605
				2606	def : Pat<(SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i16 uimm7:$val)),
				2607	(ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
				2608
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2609	def : Pat<(SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i8 uimm7:$val)),
				2610	(ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
				2611
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2612	def ROTMAHIr16:
				2613	RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
				2614	"rotmahi\t$rT, $rA, $val", RotateShift,
				2615	[(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
				2616
				2617	def : Pat<(sra R16C:$rA, (i32 imm:$val)),
				2618	(ROTMAHIr16 R16C:$rA, uimm7:$val)>;
				2619
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2620	def : Pat<(sra R16C:$rA, (i8 imm:$val)),
				2621	(ROTMAHIr16 R16C:$rA, uimm7:$val)>;
				2622
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2623	def ROTMAv4i32:
				2624	RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
				2625	"rotma\t$rT, $rA, $rB", RotateShift,
				2626	[/* see patterns below - $rB must be negated */]>;
				2627
				2628	def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R32C:$rB),
				2629	(ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
				2630
				2631	def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R16C:$rB),
				2632	(ROTMAv4i32 (v4i32 VECREG:$rA),
				2633	(SFIr32 (XSHWr16 R16C:$rB), 0))>;
				2634
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2635	def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R8C:$rB),
				2636	(ROTMAv4i32 (v4i32 VECREG:$rA),
				2637	(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
				2638
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2639	def ROTMAr32:
				2640	RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				2641	"rotma\t$rT, $rA, $rB", RotateShift,
				2642	[/* see patterns below - $rB must be negated */]>;
				2643
				2644	def : Pat<(sra R32C:$rA, R32C:$rB),
				2645	(ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
				2646
				2647	def : Pat<(sra R32C:$rA, R16C:$rB),
				2648	(ROTMAr32 R32C:$rA,
				2649	(SFIr32 (XSHWr16 R16C:$rB), 0))>;
				2650
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2651	def : Pat<(sra R32C:$rA, R8C:$rB),
				2652	(ROTMAr32 R32C:$rA,
				2653	(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
				2654
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2655	def ROTMAIv4i32:
				2656	RRForm<0b01011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
				2657	"rotmai\t$rT, $rA, $val", RotateShift,
				2658	[(set (v4i32 VECREG:$rT),
				2659	(SPUvec_sra_v4i32 VECREG:$rA, (i32 uimm7:$val)))]>;
				2660
				2661	def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, (i16 uimm7:$val)),
				2662	(ROTMAIv4i32 VECREG:$rA, uimm7:$val)>;
				2663
				2664	def ROTMAIr32:
				2665	RRForm<0b01011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
				2666	"rotmai\t$rT, $rA, $val", RotateShift,
				2667	[(set R32C:$rT, (sra R32C:$rA, (i32 uimm7:$val)))]>;
				2668
				2669	def : Pat<(sra R32C:$rA, (i16 uimm7:$val)),
				2670	(ROTMAIr32 R32C:$rA, uimm7:$val)>;
				2671
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2672	def : Pat<(sra R32C:$rA, (i8 uimm7:$val)),
				2673	(ROTMAIr32 R32C:$rA, uimm7:$val)>;
				2674
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2675	//===----------------------------------------------------------------------===//
				2676	// Branch and conditionals:
				2677	//===----------------------------------------------------------------------===//
				2678
				2679	let isTerminator = 1, isBarrier = 1 in {
				2680	// Halt If Equal (r32 preferred slot only, no vector form)
				2681	def HEQr32:
				2682	RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
				2683	"heq\t$rA, $rB", BranchResolv,
				2684	[/* no pattern to match */]>;
				2685
				2686	def HEQIr32 :
				2687	RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
				2688	"heqi\t$rA, $val", BranchResolv,
				2689	[/* no pattern to match */]>;
				2690
				2691	// HGT/HGTI: These instructions use signed arithmetic for the comparison,
				2692	// contrasting with HLGT/HLGTI, which use unsigned comparison:
				2693	def HGTr32:
				2694	RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
				2695	"hgt\t$rA, $rB", BranchResolv,
				2696	[/* no pattern to match */]>;
				2697
				2698	def HGTIr32:
				2699	RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
				2700	"hgti\t$rA, $val", BranchResolv,
				2701	[/* no pattern to match */]>;
				2702
				2703	def HLGTr32:
				2704	RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
				2705	"hlgt\t$rA, $rB", BranchResolv,
				2706	[/* no pattern to match */]>;
				2707
				2708	def HLGTIr32:
				2709	RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
				2710	"hlgti\t$rA, $val", BranchResolv,
				2711	[/* no pattern to match */]>;
				2712	}
				2713
				2714	// Comparison operators:
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2715	def CEQBr8:
				2716	RRForm<0b00001011110, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
				2717	"ceqb\t$rT, $rA, $rB", ByteOp,
				2718	[/* no pattern to match */]>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2719
				2720	def CEQBv16i8:
				2721	RRForm<0b00001011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2722	"ceqb\t$rT, $rA, $rB", ByteOp,
				2723	[/* no pattern to match: intrinsic */]>;
				2724
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	2725	def CEQBIr8:
				2726	RI10Form<0b01111110, (outs R8C:$rT), (ins R8C:$rA, s7imm:$val),
				2727	"ceqbi\t$rT, $rA, $val", ByteOp,
				2728	[/* no pattern to match: intrinsic */]>;
				2729
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	2730	def CEQBIv16i8:
				2731	RI10Form<0b01111110, (outs VECREG:$rT), (ins VECREG:$rA, s7imm:$val),
				2732	"ceqbi\t$rT, $rA, $val", ByteOp,
				2733	[/* no pattern to match: intrinsic */]>;
				2734
				2735	def CEQHr16:
				2736	RRForm<0b00010011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
				2737	"ceqh\t$rT, $rA, $rB", ByteOp,
				2738	[/* no pattern to match */]>;
				2739
				2740	def CEQHv8i16:
				2741	RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2742	"ceqh\t$rT, $rA, $rB", ByteOp,
				2743	[/* no pattern to match: intrinsic */]>;
				2744
				2745	def CEQHIr16:
				2746	RI10Form<0b10111110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
				2747	"ceqhi\t$rT, $rA, $val", ByteOp,
				2748	[/* no pattern to match: intrinsic */]>;
				2749
				2750	def CEQHIv8i16:
				2751	RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				2752	"ceqhi\t$rT, $rA, $val", ByteOp,
				2753	[/* no pattern to match: intrinsic */]>;
				2754
				2755	def CEQr32:
				2756	RRForm<0b00000011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
				2757	"ceq\t$rT, $rA, $rB", ByteOp,
				2758	[/* no pattern to match: intrinsic */]>;
				2759
				2760	def CEQv4i32:
				2761	RRForm<0b00000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2762	"ceq\t$rT, $rA, $rB", ByteOp,
				2763	[/* no pattern to match: intrinsic */]>;
				2764
				2765	def CEQIr32:
				2766	RI10Form<0b00111110, (outs R32C:$rT), (ins R32C:$rA, s10imm:$val),
				2767	"ceqi\t$rT, $rA, $val", ByteOp,
				2768	[/* no pattern to match: intrinsic */]>;
				2769
				2770	def CEQIv4i32:
				2771	RI10Form<0b00111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
				2772	"ceqi\t$rT, $rA, $val", ByteOp,
				2773	[/* no pattern to match: intrinsic */]>;
				2774
				2775	let isCall = 1,
				2776	// All calls clobber the non-callee-saved registers:
				2777	Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
				2778	R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
				2779	R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
				2780	R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
				2781	R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
				2782	R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
				2783	R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
				2784	R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
				2785	// All of these instructions use $lr (aka $0)
				2786	Uses = [R0] in {
				2787	// Branch relative and set link: Used if we actually know that the target
				2788	// is within [-32768, 32767] bytes of the target
				2789	def BRSL:
				2790	BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
				2791	"brsl\t$$lr, $func",
				2792	[(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
				2793
				2794	// Branch absolute and set link: Used if we actually know that the target
				2795	// is an absolute address
				2796	def BRASL:
				2797	BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
				2798	"brasl\t$$lr, $func",
				2799	[(SPUcall tglobaladdr:$func)]>;
				2800
				2801	// Branch indirect and set link if external data. These instructions are not
				2802	// actually generated, matched by an intrinsic:
				2803	def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
				2804	def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
				2805	def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
				2806	def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
				2807
				2808	// Branch indirect and set link. This is the "X-form" address version of a
				2809	// function call
				2810	def BISL:
				2811	BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
				2812	}
				2813
				2814	// Unconditional branches:
				2815	let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
				2816	def BR :
				2817	UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
				2818	"br\t$dest",
				2819	[(br bb:$dest)]>;
				2820
				2821	// Unconditional, absolute address branch
				2822	def BRA:
				2823	UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
				2824	"bra\t$dest",
				2825	[/* no pattern */]>;
				2826
				2827	// Indirect branch
				2828	def BI:
				2829	BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
				2830
				2831	// Various branches:
				2832	def BRNZ:
				2833	RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest),
				2834	"brnz\t$rCond,$dest",
				2835	BranchResolv,
				2836	[(brcond R32C:$rCond, bb:$dest)]>;
				2837
				2838	def BRZ:
				2839	RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest),
				2840	"brz\t$rT,$dest",
				2841	BranchResolv,
				2842	[/* no pattern */]>;
				2843
				2844	def BRHNZ:
				2845	RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest),
				2846	"brhnz\t$rCond,$dest",
				2847	BranchResolv,
				2848	[(brcond R16C:$rCond, bb:$dest)]>;
				2849
				2850	def BRHZ:
				2851	RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest),
				2852	"brhz\t$rT,$dest",
				2853	BranchResolv,
				2854	[/* no pattern */]>;
				2855
				2856	/*
				2857	def BINZ:
				2858	BICondForm<0b10010100100, "binz\t$rA, $func",
				2859	[(SPUbinz R32C:$rA, R32C:$func)]>;
				2860
				2861	def BIZ:
				2862	BICondForm<0b00010100100, "biz\t$rA, $func",
				2863	[(SPUbiz R32C:$rA, R32C:$func)]>;
				2864	*/
				2865	}
				2866
				2867	def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
				2868	(BRHZ R16C:$rA, bb:$dest)>;
				2869	def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
				2870	(BRHNZ R16C:$rA, bb:$dest)>;
				2871
				2872	def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
				2873	(BRZ R32C:$rA, bb:$dest)>;
				2874	def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
				2875	(BRZ R32C:$rA, bb:$dest)>;
				2876
				2877	let isTerminator = 1, isBarrier = 1 in {
				2878	let isReturn = 1 in {
				2879	def RET:
				2880	RETForm<"bi\t$$lr", [(retflag)]>;
				2881	}
				2882	}
				2883
				2884	//===----------------------------------------------------------------------===//
				2885	// Various brcond predicates:
				2886	//===----------------------------------------------------------------------===//
				2887	/*
				2888	def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
				2889	(BRZ R32C:$rA, bb:$dest)>;
				2890
				2891	def : Pat<(brcond (i32 (seteq R32C:$rA, R32C:$rB)), bb:$dest),
				2892	(BRNZ (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
				2893
				2894	def : Pat<(brcond (i16 (seteq R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
				2895	(BRHNZ (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
				2896
				2897	def : Pat<(brcond (i16 (seteq R16C:$rA, R16C:$rB)), bb:$dest),
				2898	(BRHNZ (CEQHr16 R16C:$rA, R16C:$rB), bb:$dest)>;
				2899	*/
				2900
				2901	//===----------------------------------------------------------------------===//
				2902	// Single precision floating point instructions
				2903	//===----------------------------------------------------------------------===//
				2904
				2905	def FAv4f32:
				2906	RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2907	"fa\t$rT, $rA, $rB", SPrecFP,
				2908	[(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
				2909
				2910	def FAf32 :
				2911	RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
				2912	"fa\t$rT, $rA, $rB", SPrecFP,
				2913	[(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
				2914
				2915	def FSv4f32:
				2916	RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2917	"fs\t$rT, $rA, $rB", SPrecFP,
				2918	[(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
				2919
				2920	def FSf32 :
				2921	RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
				2922	"fs\t$rT, $rA, $rB", SPrecFP,
				2923	[(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
				2924
				2925	// Floating point reciprocal estimate
				2926	def FREv4f32 :
				2927	RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA),
				2928	"frest\t$rT, $rA", SPrecFP,
				2929	[(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>;
				2930
				2931	def FREf32 :
				2932	RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA),
				2933	"frest\t$rT, $rA", SPrecFP,
				2934	[(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>;
				2935
				2936	// Floating point interpolate (used in conjunction with reciprocal estimate)
				2937	def FIv4f32 :
				2938	RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				2939	"fi\t$rT, $rA, $rB", SPrecFP,
				2940	[(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA),
				2941	(v4f32 VECREG:$rB)))]>;
				2942
				2943	def FIf32 :
				2944	RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
				2945	"fi\t$rT, $rA, $rB", SPrecFP,
				2946	[(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
				2947
				2948	// Floating Compare Equal
				2949	def FCEQf32 :
				2950	RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
				2951	"fceq\t$rT, $rA, $rB", SPrecFP,
				2952	[(set R32C:$rT, (setoeq R32FP:$rA, R32FP:$rB))]>;
				2953
				2954	def FCMEQf32 :
				2955	RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
				2956	"fcmeq\t$rT, $rA, $rB", SPrecFP,
				2957	[(set R32C:$rT, (setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
				2958
				2959	def FCGTf32 :
				2960	RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
				2961	"fcgt\t$rT, $rA, $rB", SPrecFP,
				2962	[(set R32C:$rT, (setogt R32FP:$rA, R32FP:$rB))]>;
				2963
				2964	def FCMGTf32 :
				2965	RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
				2966	"fcmgt\t$rT, $rA, $rB", SPrecFP,
				2967	[(set R32C:$rT, (setogt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
				2968
				2969	// FP Status and Control Register Write
				2970	// Why isn't rT a don't care in the ISA?
				2971	// Should we create a special RRForm_3 for this guy and zero out the rT?
				2972	def FSCRWf32 :
				2973	RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
				2974	"fscrwr\t$rA", SPrecFP,
				2975	[/* This instruction requires an intrinsic. Note: rT is unused. */]>;
				2976
				2977	// FP Status and Control Register Read
				2978	def FSCRRf32 :
				2979	RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
				2980	"fscrrd\t$rT", SPrecFP,
				2981	[/* This instruction requires an intrinsic */]>;
				2982
				2983	// llvm instruction space
				2984	// How do these map onto cell instructions?
				2985	// fdiv rA rB
				2986	// frest rC rB # c = 1/b (both lines)
				2987	// fi rC rB rC
				2988	// fm rD rA rC # d = a * 1/b
				2989	// fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
				2990	// fma rB rB rC rD # b = b * c + d
				2991	// = -(d b -a) c + d
				2992	// = a * c - c ( a b c - a)
				2993
				2994	// fcopysign (???)
				2995
				2996	// Library calls:
				2997	// These llvm instructions will actually map to library calls.
				2998	// All that's needed, then, is to check that the appropriate library is
				2999	// imported and do a brsl to the proper function name.
				3000	// frem # fmod(x, y): x - (x/y) * y
				3001	// (Note: fmod(double, double), fmodf(float,float)
				3002	// fsqrt?
				3003	// fsin?
				3004	// fcos?
				3005	// Unimplemented SPU instruction space
				3006	// floating reciprocal absolute square root estimate (frsqest)
				3007
				3008	// The following are probably just intrinsics
				3009	// status and control register write
				3010	// status and control register read
				3011
				3012	//--------------------------------------
				3013	// Floating point multiply instructions
				3014	//--------------------------------------
				3015
				3016	def FMv4f32:
				3017	RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				3018	"fm\t$rT, $rA, $rB", SPrecFP,
				3019	[(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
				3020	(v4f32 VECREG:$rB)))]>;
				3021
				3022	def FMf32 :
				3023	RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
				3024	"fm\t$rT, $rA, $rB", SPrecFP,
				3025	[(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
				3026
				3027	// Floating point multiply and add
				3028	// e.g. d = c + (a * b)
				3029	def FMAv4f32:
				3030	RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				3031	"fma\t$rT, $rA, $rB, $rC", SPrecFP,
				3032	[(set (v4f32 VECREG:$rT),
				3033	(fadd (v4f32 VECREG:$rC),
				3034	(fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
				3035
				3036	def FMAf32:
				3037	RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
				3038	"fma\t$rT, $rA, $rB, $rC", SPrecFP,
				3039	[(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
				3040
				3041	// FP multiply and subtract
				3042	// Subtracts value in rC from product
				3043	// res = a * b - c
				3044	def FMSv4f32 :
				3045	RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				3046	"fms\t$rT, $rA, $rB, $rC", SPrecFP,
				3047	[(set (v4f32 VECREG:$rT),
				3048	(fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
				3049	(v4f32 VECREG:$rC)))]>;
				3050
				3051	def FMSf32 :
				3052	RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
				3053	"fms\t$rT, $rA, $rB, $rC", SPrecFP,
				3054	[(set R32FP:$rT,
				3055	(fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
				3056
				3057	// Floating Negative Mulitply and Subtract
				3058	// Subtracts product from value in rC
				3059	// res = fneg(fms a b c)
				3060	// = - (a * b - c)
				3061	// = c - a * b
				3062	// NOTE: subtraction order
				3063	// fsub a b = a - b
				3064	// fs a b = b - a?
				3065	def FNMSf32 :
				3066	RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
				3067	"fnms\t$rT, $rA, $rB, $rC", SPrecFP,
				3068	[(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
				3069
				3070	def FNMSv4f32 :
				3071	RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				3072	"fnms\t$rT, $rA, $rB, $rC", SPrecFP,
				3073	[(set (v4f32 VECREG:$rT),
				3074	(fsub (v4f32 VECREG:$rC),
				3075	(fmul (v4f32 VECREG:$rA),
				3076	(v4f32 VECREG:$rB))))]>;
				3077
				3078	//--------------------------------------
				3079	// Floating Point Conversions
				3080	// Signed conversions:
				3081	def CSiFv4f32:
				3082	CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
				3083	"csflt\t$rT, $rA, 0", SPrecFP,
				3084	[(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
				3085
				3086	// Convert signed integer to floating point
				3087	def CSiFf32 :
				3088	CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
				3089	"csflt\t$rT, $rA, 0", SPrecFP,
				3090	[(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
				3091
				3092	// Convert unsigned into to float
				3093	def CUiFv4f32 :
				3094	CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
				3095	"cuflt\t$rT, $rA, 0", SPrecFP,
				3096	[(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
				3097
				3098	def CUiFf32 :
				3099	CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
				3100	"cuflt\t$rT, $rA, 0", SPrecFP,
				3101	[(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
				3102
				3103	// Convert float to unsigned int
				3104	// Assume that scale = 0
				3105
				3106	def CFUiv4f32 :
				3107	CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
				3108	"cfltu\t$rT, $rA, 0", SPrecFP,
				3109	[(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
				3110
				3111	def CFUif32 :
				3112	CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
				3113	"cfltu\t$rT, $rA, 0", SPrecFP,
				3114	[(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
				3115
				3116	// Convert float to signed int
				3117	// Assume that scale = 0
				3118
				3119	def CFSiv4f32 :
				3120	CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
				3121	"cflts\t$rT, $rA, 0", SPrecFP,
				3122	[(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
				3123
				3124	def CFSif32 :
				3125	CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
				3126	"cflts\t$rT, $rA, 0", SPrecFP,
				3127	[(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
				3128
				3129	//===----------------------------------------------------------------------==//
				3130	// Single<->Double precision conversions
				3131	//===----------------------------------------------------------------------==//
				3132
				3133	// NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
				3134	// v4f32, output is v2f64--which goes in the name?)
				3135
				3136	// Floating point extend single to double
				3137	// NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
				3138	// operates on two double-word slots (i.e. 1st and 3rd fp numbers
				3139	// are ignored).
				3140	def FESDvec :
				3141	RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
				3142	"fesd\t$rT, $rA", SPrecFP,
				3143	[(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
				3144
				3145	def FESDf32 :
				3146	RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
				3147	"fesd\t$rT, $rA", SPrecFP,
				3148	[(set R64FP:$rT, (fextend R32FP:$rA))]>;
				3149
				3150	// Floating point round double to single
				3151	//def FRDSvec :
				3152	// RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
				3153	// "frds\t$rT, $rA,", SPrecFP,
				3154	// [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
				3155
				3156	def FRDSf64 :
				3157	RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
				3158	"frds\t$rT, $rA", SPrecFP,
				3159	[(set R32FP:$rT, (fround R64FP:$rA))]>;
				3160
				3161	//ToDo include anyextend?
				3162
				3163	//===----------------------------------------------------------------------==//
				3164	// Double precision floating point instructions
				3165	//===----------------------------------------------------------------------==//
				3166	def FAf64 :
				3167	RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
				3168	"dfa\t$rT, $rA, $rB", DPrecFP,
				3169	[(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
				3170
				3171	def FAv2f64 :
				3172	RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				3173	"dfa\t$rT, $rA, $rB", DPrecFP,
				3174	[(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
				3175
				3176	def FSf64 :
				3177	RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
				3178	"dfs\t$rT, $rA, $rB", DPrecFP,
				3179	[(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
				3180
				3181	def FSv2f64 :
				3182	RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				3183	"dfs\t$rT, $rA, $rB", DPrecFP,
				3184	[(set (v2f64 VECREG:$rT),
				3185	(fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
				3186
				3187	def FMf64 :
				3188	RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
				3189	"dfm\t$rT, $rA, $rB", DPrecFP,
				3190	[(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
				3191
				3192	def FMv2f64:
				3193	RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
				3194	"dfm\t$rT, $rA, $rB", DPrecFP,
				3195	[(set (v2f64 VECREG:$rT),
				3196	(fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
				3197
				3198	def FMAf64:
				3199	RRForm<0b00111010110, (outs R64FP:$rT),
				3200	(ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
				3201	"dfma\t$rT, $rA, $rB", DPrecFP,
				3202	[(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
				3203	RegConstraint<"$rC = $rT">,
				3204	NoEncode<"$rC">;
				3205
				3206	def FMAv2f64:
				3207	RRForm<0b00111010110, (outs VECREG:$rT),
				3208	(ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				3209	"dfma\t$rT, $rA, $rB", DPrecFP,
				3210	[(set (v2f64 VECREG:$rT),
				3211	(fadd (v2f64 VECREG:$rC),
				3212	(fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
				3213	RegConstraint<"$rC = $rT">,
				3214	NoEncode<"$rC">;
				3215
				3216	def FMSf64 :
				3217	RRForm<0b10111010110, (outs R64FP:$rT),
				3218	(ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
				3219	"dfms\t$rT, $rA, $rB", DPrecFP,
				3220	[(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
				3221	RegConstraint<"$rC = $rT">,
				3222	NoEncode<"$rC">;
				3223
				3224	def FMSv2f64 :
				3225	RRForm<0b10111010110, (outs VECREG:$rT),
				3226	(ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				3227	"dfms\t$rT, $rA, $rB", DPrecFP,
				3228	[(set (v2f64 VECREG:$rT),
				3229	(fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
				3230	(v2f64 VECREG:$rC)))]>;
				3231
				3232	// FNMS: - (a * b - c)
				3233	// - (a * b) + c => c - (a * b)
				3234	def FNMSf64 :
				3235	RRForm<0b01111010110, (outs R64FP:$rT),
				3236	(ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
				3237	"dfnms\t$rT, $rA, $rB", DPrecFP,
				3238	[(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
				3239	RegConstraint<"$rC = $rT">,
				3240	NoEncode<"$rC">;
				3241
				3242	def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)),
				3243	(FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>;
				3244
				3245	def FNMSv2f64 :
				3246	RRForm<0b01111010110, (outs VECREG:$rT),
				3247	(ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				3248	"dfnms\t$rT, $rA, $rB", DPrecFP,
				3249	[(set (v2f64 VECREG:$rT),
				3250	(fsub (v2f64 VECREG:$rC),
				3251	(fmul (v2f64 VECREG:$rA),
				3252	(v2f64 VECREG:$rB))))]>,
				3253	RegConstraint<"$rC = $rT">,
				3254	NoEncode<"$rC">;
				3255
				3256	def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
				3257	(v2f64 VECREG:$rC))),
				3258	(FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
				3259
				3260	// - (a * b + c)
				3261	// - (a * b) - c
				3262	def FNMAf64 :
				3263	RRForm<0b11111010110, (outs R64FP:$rT),
				3264	(ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
				3265	"dfnma\t$rT, $rA, $rB", DPrecFP,
				3266	[(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
				3267	RegConstraint<"$rC = $rT">,
				3268	NoEncode<"$rC">;
				3269
				3270	def FNMAv2f64 :
				3271	RRForm<0b11111010110, (outs VECREG:$rT),
				3272	(ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
				3273	"dfnma\t$rT, $rA, $rB", DPrecFP,
				3274	[(set (v2f64 VECREG:$rT),
				3275	(fneg (fadd (v2f64 VECREG:$rC),
				3276	(fmul (v2f64 VECREG:$rA),
				3277	(v2f64 VECREG:$rB)))))]>,
				3278	RegConstraint<"$rC = $rT">,
				3279	NoEncode<"$rC">;
				3280
				3281	//===----------------------------------------------------------------------==//
				3282	// Floating point negation and absolute value
				3283	//===----------------------------------------------------------------------==//
				3284
				3285	def : Pat<(fneg (v4f32 VECREG:$rA)),
				3286	(XORfnegvec (v4f32 VECREG:$rA),
				3287	(v4f32 (ILHUv4i32 0x8000)))>;
				3288
				3289	def : Pat<(fneg R32FP:$rA),
				3290	(XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
				3291
				3292	def : Pat<(fneg (v2f64 VECREG:$rA)),
				3293	(XORfnegvec (v2f64 VECREG:$rA),
				3294	(v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>;
				3295
				3296	def : Pat<(fneg R64FP:$rA),
				3297	(XORfneg64 R64FP:$rA,
				3298	(ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>;
				3299
				3300	// Floating point absolute value
				3301
				3302	def : Pat<(fabs R32FP:$rA),
				3303	(ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
				3304
				3305	def : Pat<(fabs (v4f32 VECREG:$rA)),
				3306	(ANDfabsvec (v4f32 VECREG:$rA),
				3307	(v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
				3308
				3309	def : Pat<(fabs R64FP:$rA),
				3310	(ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>;
				3311
				3312	def : Pat<(fabs (v2f64 VECREG:$rA)),
				3313	(ANDfabsvec (v2f64 VECREG:$rA),
				3314	(v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
				3315
				3316	//===----------------------------------------------------------------------===//
				3317	// Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
				3318	// in the odd pipeline)
				3319	//===----------------------------------------------------------------------===//
				3320
				3321	def ENOP : I<(outs), (ins), "enop", ExecNOP> {
				3322	let Pattern = [];
				3323
				3324	let Inst{0-10} = 0b10000000010;
				3325	let Inst{11-17} = 0;
				3326	let Inst{18-24} = 0;
				3327	let Inst{25-31} = 0;
				3328	}
				3329
				3330	def LNOP : I<(outs), (ins), "lnop", LoadNOP> {
				3331	let Pattern = [];
				3332
				3333	let Inst{0-10} = 0b10000000000;
				3334	let Inst{11-17} = 0;
				3335	let Inst{18-24} = 0;
				3336	let Inst{25-31} = 0;
				3337	}
				3338
				3339	//===----------------------------------------------------------------------===//
				3340	// Bit conversions (type conversions between vector/packed types)
				3341	// NOTE: Promotions are handled using the XS* instructions. Truncation
				3342	// is not handled.
				3343	//===----------------------------------------------------------------------===//
				3344	def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
				3345	def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
				3346	def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
				3347	def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
				3348	def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
				3349
				3350	def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
				3351	def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
				3352	def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
				3353	def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
				3354	def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
				3355
				3356	def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
				3357	def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
				3358	def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
				3359	def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
				3360	def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
				3361
				3362	def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
				3363	def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
				3364	def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
				3365	def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
				3366	def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
				3367
				3368	def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
				3369	def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
				3370	def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
				3371	def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
				3372	def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
				3373
				3374	def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
				3375	def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
				3376	def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
				3377	def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
				3378	def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
				3379
				3380	def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
Scott Michel	754d866	2007-12-20 00:44:13 +0000	[diff] [blame^]	3381	def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	3382
				3383	//===----------------------------------------------------------------------===//
				3384	// Instruction patterns:
				3385	//===----------------------------------------------------------------------===//
				3386
				3387	// General 32-bit constants:
				3388	def : Pat<(i32 imm:$imm),
				3389	(IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
				3390
				3391	// Single precision float constants:
				3392	def : Pat<(SPUFPconstant (f32 fpimm:$imm)),
				3393	(IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
				3394
				3395	// General constant 32-bit vectors
				3396	def : Pat<(v4i32 v4i32Imm:$imm),
				3397	(IOHLvec (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
				3398	(LO16_vec v4i32Imm:$imm))>;
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	3399
				3400	// 8-bit constants
				3401	def : Pat<(i8 imm:$imm),
				3402	(ILHr8 imm:$imm)>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	3403
				3404	//===----------------------------------------------------------------------===//
				3405	// Call instruction patterns:
				3406	//===----------------------------------------------------------------------===//
				3407	// Return void
				3408	def : Pat<(ret),
				3409	(RET)>;
				3410
				3411	//===----------------------------------------------------------------------===//
				3412	// Zero/Any/Sign extensions
				3413	//===----------------------------------------------------------------------===//
				3414
				3415	// zext 1->32: Zero extend i1 to i32
				3416	def : Pat<(SPUextract_i1_zext R32C:$rSrc),
				3417	(ANDIr32 R32C:$rSrc, 0x1)>;
				3418
				3419	// sext 8->32: Sign extend bytes to words
				3420	def : Pat<(sext_inreg R32C:$rSrc, i8),
				3421	(XSHWr32 (XSBHr32 R32C:$rSrc))>;
				3422
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	3423	def : Pat<(i32 (sext R8C:$rSrc)),
				3424	(XSHWr16 (XSBHr8 R8C:$rSrc))>;
				3425
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	3426	def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
				3427	(XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
				3428	(v4i32 VECREG:$rSrc))))>;
				3429
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	3430	// zext 8->16: Zero extend bytes to halfwords
				3431	def : Pat<(i16 (zext R8C:$rSrc)),
				3432	(ANDHI1To2 R8C:$rSrc, 0xff)>;
				3433
				3434	// zext 8->32 from preferred slot in load/store
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	3435	def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
				3436	(ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
				3437	0xff)>;
				3438
Scott Michel	438be25	2007-12-17 22:32:34 +0000	[diff] [blame]	3439	// zext 8->32: Zero extend bytes to words
				3440	def : Pat<(i32 (zext R8C:$rSrc)),
				3441	(ANDI1To4 R8C:$rSrc, 0xff)>;
				3442
				3443	// anyext 8->16: Extend 8->16 bits, irrespective of sign
				3444	def : Pat<(i16 (anyext R8C:$rSrc)),
				3445	(ORHI1To2 R8C:$rSrc, 0)>;
				3446
				3447	// anyext 8->32: Extend 8->32 bits, irrespective of sign
				3448	def : Pat<(i32 (anyext R8C:$rSrc)),
				3449	(ORI1To4 R8C:$rSrc, 0)>;
				3450
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	3451	// zext 16->32: Zero extend halfwords to words (note that we have to juggle the
				3452	// 0xffff constant since it will not fit into an immediate.)
				3453	def : Pat<(i32 (zext R16C:$rSrc)),
				3454	(AND2To4 R16C:$rSrc, (ILAr32 0xffff))>;
				3455
				3456	def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
				3457	(ANDI2To4 R16C:$rSrc, 0xf)>;
				3458
				3459	def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
				3460	(ANDI2To4 R16C:$rSrc, 0xff)>;
				3461
				3462	def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
				3463	(ANDI2To4 R16C:$rSrc, 0xfff)>;
				3464
				3465	// anyext 16->32: Extend 16->32 bits, irrespective of sign
				3466	def : Pat<(i32 (anyext R16C:$rSrc)),
				3467	(ORI2To4 R16C:$rSrc, 0)>;
				3468
				3469	//===----------------------------------------------------------------------===//
				3470	// Address translation: SPU, like PPC, has to split addresses into high and
				3471	// low parts in order to load them into a register.
				3472	//===----------------------------------------------------------------------===//
				3473
				3474	def : Pat<(SPUhi tglobaladdr:$in, 0), (ILHUhi tglobaladdr:$in)>;
				3475	def : Pat<(SPUlo tglobaladdr:$in, 0), (ILAlo tglobaladdr:$in)>;
				3476	def : Pat<(SPUdform tglobaladdr:$in, imm:$imm), (ILAlsa tglobaladdr:$in)>;
				3477	def : Pat<(SPUhi tconstpool:$in , 0), (ILHUhi tconstpool:$in)>;
				3478	def : Pat<(SPUlo tconstpool:$in , 0), (ILAlo tconstpool:$in)>;
				3479	def : Pat<(SPUdform tconstpool:$in, imm:$imm), (ILAlsa tconstpool:$in)>;
				3480	def : Pat<(SPUhi tjumptable:$in, 0), (ILHUhi tjumptable:$in)>;
				3481	def : Pat<(SPUlo tjumptable:$in, 0), (ILAlo tjumptable:$in)>;
				3482	def : Pat<(SPUdform tjumptable:$in, imm:$imm), (ILAlsa tjumptable:$in)>;
				3483
				3484	// Force load of global address to a register. These forms show up in
				3485	// SPUISD::DFormAddr pseudo instructions:
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	3486	def : Pat<(add tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
				3487	def : Pat<(add tconstpool:$in, 0), (ILAlsa tglobaladdr:$in)>;
				3488	def : Pat<(add tjumptable:$in, 0), (ILAlsa tglobaladdr:$in)>;
Scott Michel	8b6b420	2007-12-04 22:35:58 +0000	[diff] [blame]	3489	// Instrinsics:
				3490	include "CellSDKIntrinsics.td"