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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 810848d5b3bc53747722db0d30a21dc168c5503e / . / lib / Target / Hexagon / HexagonInstrInfo.h
blob: 47e815d6238ea50557c65c8bf9275697f2c0c976 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef HexagonINSTRUCTIONINFO_H
15#define HexagonINSTRUCTIONINFO_H
16
Craig Topper79aa3412012-03-17 18:46:09 +0000[diff] [blame]17#include "HexagonRegisterInfo.h"
Brendon Cahoonc635ebd2012-02-08 18:25:47 +0000[diff] [blame]18#include "MCTargetDesc/HexagonBaseInfo.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]19#include "llvm/Target/TargetFrameLowering.h"
Chandler Carrutha1514e22012-12-04 07:12:27 +0000[diff] [blame]20#include "llvm/Target/TargetInstrInfo.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]21
22
23#define GET_INSTRINFO_HEADER
24#include "HexagonGenInstrInfo.inc"
25
26namespace llvm {
27
28class HexagonInstrInfo : public HexagonGenInstrInfo {
29 const HexagonRegisterInfo RI;
30 const HexagonSubtarget& Subtarget;
31public:
32 explicit HexagonInstrInfo(HexagonSubtarget &ST);
33
34 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
35 /// such, whenever a client has an instance of instruction info, it should
36 /// always be able to get register info as well (through this method).
37 ///
38 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
39
40 /// isLoadFromStackSlot - If the specified machine instruction is a direct
41 /// load from a stack slot, return the virtual or physical register number of
42 /// the destination along with the FrameIndex of the loaded stack slot. If
43 /// not, return 0. This predicate must return 0 if the instruction has
44 /// any side effects other than loading from the stack slot.
45 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
46 int &FrameIndex) const;
47
48 /// isStoreToStackSlot - If the specified machine instruction is a direct
49 /// store to a stack slot, return the virtual or physical register number of
50 /// the source reg along with the FrameIndex of the loaded stack slot. If
51 /// not, return 0. This predicate must return 0 if the instruction has
52 /// any side effects other than storing to the stack slot.
53 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
54 int &FrameIndex) const;
55
56
57 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
58 MachineBasicBlock *&FBB,
59 SmallVectorImpl<MachineOperand> &Cond,
60 bool AllowModify) const;
61
62 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
63
64 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
65 MachineBasicBlock *FBB,
66 const SmallVectorImpl<MachineOperand> &Cond,
67 DebugLoc DL) const;
68
Krzysztof Parzyszekce55d912013-02-11 20:04:29 +0000[diff] [blame]69 virtual bool analyzeCompare(const MachineInstr *MI,
70 unsigned &SrcReg, unsigned &SrcReg2,
71 int &Mask, int &Value) const;
72
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]73 virtual void copyPhysReg(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator I, DebugLoc DL,
75 unsigned DestReg, unsigned SrcReg,
76 bool KillSrc) const;
77
78 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MBBI,
80 unsigned SrcReg, bool isKill, int FrameIndex,
81 const TargetRegisterClass *RC,
82 const TargetRegisterInfo *TRI) const;
83
84 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
85 SmallVectorImpl<MachineOperand> &Addr,
86 const TargetRegisterClass *RC,
87 SmallVectorImpl<MachineInstr*> &NewMIs) const;
88
89 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator MBBI,
91 unsigned DestReg, int FrameIndex,
92 const TargetRegisterClass *RC,
93 const TargetRegisterInfo *TRI) const;
94
95 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
96 SmallVectorImpl<MachineOperand> &Addr,
97 const TargetRegisterClass *RC,
98 SmallVectorImpl<MachineInstr*> &NewMIs) const;
99
100 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
101 MachineInstr* MI,
102 const SmallVectorImpl<unsigned> &Ops,
103 int FrameIndex) const;
104
105 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
106 MachineInstr* MI,
107 const SmallVectorImpl<unsigned> &Ops,
108 MachineInstr* LoadMI) const {
109 return 0;
110 }
111
112 unsigned createVR(MachineFunction* MF, MVT VT) const;
113
114 virtual bool isPredicable(MachineInstr *MI) const;
115 virtual bool
116 PredicateInstruction(MachineInstr *MI,
117 const SmallVectorImpl<MachineOperand> &Cond) const;
118
Kay Tiong Khoo575e90e2012-06-13 15:53:04 +0000[diff] [blame]119 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]120 unsigned ExtraPredCycles,
121 const BranchProbability &Probability) const;
122
123 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
124 unsigned NumTCycles, unsigned ExtraTCycles,
125 MachineBasicBlock &FMBB,
126 unsigned NumFCycles, unsigned ExtraFCycles,
127 const BranchProbability &Probability) const;
128
129 virtual bool isPredicated(const MachineInstr *MI) const;
Jyotsna Verma810848d2013-03-28 19:44:04 +0000[diff] [blame^]130 virtual bool isPredicatedNew(const MachineInstr *MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]131 virtual bool DefinesPredicate(MachineInstr *MI,
132 std::vector<MachineOperand> &Pred) const;
133 virtual bool
134 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
135 const SmallVectorImpl<MachineOperand> &Pred2) const;
136
137 virtual bool
138 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
139
140 virtual bool
141 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
142 const BranchProbability &Probability) const;
143
Andrew Trickee498d32012-02-01 22:13:57 +0000[diff] [blame]144 virtual DFAPacketizer*
145 CreateTargetScheduleState(const TargetMachine *TM,
146 const ScheduleDAG *DAG) const;
147
148 virtual bool isSchedulingBoundary(const MachineInstr *MI,
149 const MachineBasicBlock *MBB,
150 const MachineFunction &MF) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]151 bool isValidOffset(const int Opcode, const int Offset) const;
152 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
153 bool isMemOp(const MachineInstr *MI) const;
154 bool isSpillPredRegOp(const MachineInstr *MI) const;
155 bool isU6_3Immediate(const int value) const;
156 bool isU6_2Immediate(const int value) const;
157 bool isU6_1Immediate(const int value) const;
158 bool isU6_0Immediate(const int value) const;
159 bool isS4_3Immediate(const int value) const;
160 bool isS4_2Immediate(const int value) const;
161 bool isS4_1Immediate(const int value) const;
162 bool isS4_0Immediate(const int value) const;
163 bool isS12_Immediate(const int value) const;
164 bool isU6_Immediate(const int value) const;
165 bool isS8_Immediate(const int value) const;
166 bool isS6_Immediate(const int value) const;
167
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]168 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
169 bool isConditionalTransfer(const MachineInstr* MI) const;
Chandler Carruthd410eab2012-04-23 18:25:57 +0000[diff] [blame]170 bool isConditionalALU32 (const MachineInstr* MI) const;
171 bool isConditionalLoad (const MachineInstr* MI) const;
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]172 bool isConditionalStore(const MachineInstr* MI) const;
Jyotsna Verma9feabc22013-03-05 18:51:42 +0000[diff] [blame]173 bool isNewValueInst(const MachineInstr* MI) const;
Jyotsna Verma810848d2013-03-28 19:44:04 +0000[diff] [blame^]174 bool isDotNewInst(const MachineInstr* MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]175 bool isDeallocRet(const MachineInstr *MI) const;
Chandler Carruthd410eab2012-04-23 18:25:57 +0000[diff] [blame]176 unsigned getInvertedPredicatedOpcode(const int Opc) const;
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]177 bool isExtendable(const MachineInstr* MI) const;
178 bool isExtended(const MachineInstr* MI) const;
179 bool isPostIncrement(const MachineInstr* MI) const;
180 bool isNewValueStore(const MachineInstr* MI) const;
181 bool isNewValueJump(const MachineInstr* MI) const;
Sirish Pandeb3385702012-05-12 05:10:30 +0000[diff] [blame]182 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]183
Jyotsna Vermaef94c6c2013-03-01 17:37:13 +0000[diff] [blame]184
185 void immediateExtend(MachineInstr *MI) const;
186 bool isConstExtended(MachineInstr *MI) const;
187 unsigned getAddrMode(const MachineInstr* MI) const;
188 bool isOperandExtended(const MachineInstr *MI,
189 unsigned short OperandNum) const;
190 unsigned short getCExtOpNum(const MachineInstr *MI) const;
191 int getMinValue(const MachineInstr *MI) const;
192 int getMaxValue(const MachineInstr *MI) const;
193 bool NonExtEquivalentExists (const MachineInstr *MI) const;
194 short getNonExtOpcode(const MachineInstr *MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]195private:
196 int getMatchingCondBranchOpcode(int Opc, bool sense) const;
197
198};
199
200}
201
202#endif