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Dan Gohmanf17a25c2007-07-18 16:29:46 +00001//===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Alpha implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ALPHAINSTRUCTIONINFO_H
15#define ALPHAINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "AlphaRegisterInfo.h"
19
20namespace llvm {
21
Chris Lattnerd2fd6db2008-01-01 01:03:04 +000022class AlphaInstrInfo : public TargetInstrInfoImpl {
Dan Gohmanf17a25c2007-07-18 16:29:46 +000023 const AlphaRegisterInfo RI;
24public:
25 AlphaInstrInfo();
26
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
30 ///
Dan Gohmanb41dfba2008-05-14 01:58:56 +000031 virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
Dan Gohmanf17a25c2007-07-18 16:29:46 +000032
Evan Chengf97496a2009-01-20 19:12:24 +000033 /// Return true if the instruction is a register to register move and return
34 /// the source and dest operands and their sub-register indices by reference.
Dan Gohmanf17a25c2007-07-18 16:29:46 +000035 virtual bool isMoveInstr(const MachineInstr &MI,
Evan Chengf97496a2009-01-20 19:12:24 +000036 unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000038
Dan Gohman90feee22008-11-18 19:49:32 +000039 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
40 int &FrameIndex) const;
41 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
42 int &FrameIndex) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000043
44 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
45 MachineBasicBlock *FBB,
Owen Andersond131b5b2008-08-14 22:49:33 +000046 const SmallVectorImpl<MachineOperand> &Cond) const;
Owen Anderson9fa72d92008-08-26 18:03:31 +000047 virtual bool copyRegToReg(MachineBasicBlock &MBB,
Owen Anderson8f2c8932007-12-31 06:32:00 +000048 MachineBasicBlock::iterator MI,
49 unsigned DestReg, unsigned SrcReg,
50 const TargetRegisterClass *DestRC,
51 const TargetRegisterClass *SrcRC) const;
Owen Anderson81875432008-01-01 21:11:32 +000052 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MBBI,
54 unsigned SrcReg, bool isKill, int FrameIndex,
55 const TargetRegisterClass *RC) const;
56
Owen Anderson81875432008-01-01 21:11:32 +000057 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI,
59 unsigned DestReg, int FrameIndex,
60 const TargetRegisterClass *RC) const;
Owen Anderson9a184ef2008-01-07 01:35:02 +000061
Dan Gohmanedc83d62008-12-03 18:43:12 +000062 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
63 MachineInstr* MI,
64 const SmallVectorImpl<unsigned> &Ops,
65 int FrameIndex) const;
Owen Anderson9a184ef2008-01-07 01:35:02 +000066
Dan Gohmanedc83d62008-12-03 18:43:12 +000067 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
68 MachineInstr* MI,
69 const SmallVectorImpl<unsigned> &Ops,
70 MachineInstr* LoadMI) const {
Owen Anderson9a184ef2008-01-07 01:35:02 +000071 return 0;
72 }
73
Dan Gohmanf17a25c2007-07-18 16:29:46 +000074 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
75 MachineBasicBlock *&FBB,
Evan Chengeac31642009-02-09 07:14:22 +000076 SmallVectorImpl<MachineOperand> &Cond,
77 bool AllowModify) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000078 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
79 void insertNoop(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator MI) const;
Dan Gohman46b948e2008-10-16 01:49:15 +000081 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
Owen Andersond131b5b2008-08-14 22:49:33 +000082 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
Dan Gohman40653f32009-06-03 20:30:14 +000083
84 /// getGlobalBaseReg - Return a virtual register initialized with the
85 /// the global base register value. Output instructions required to
86 /// initialize the register in the function entry block, if necessary.
87 ///
88 unsigned getGlobalBaseReg(MachineFunction *MF) const;
89
90 /// getGlobalRetAddr - Return a virtual register initialized with the
91 /// the global return address register value. Output instructions required to
92 /// initialize the register in the function entry block, if necessary.
93 ///
94 unsigned getGlobalRetAddr(MachineFunction *MF) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000095};
96
97}
98
99#endif