blob: ed485308e17d6314dee6f5936bb445721670f325 [file] [log] [blame]
Misha Brukmanbc9ccf62005-02-04 20:25:52 +00001//===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
Misha Brukman4633f1c2005-04-21 23:13:11 +00002//
Andrew Lenharth304d0f32005-01-22 23:41:55 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukman4633f1c2005-04-21 23:13:11 +00007//
Andrew Lenharth304d0f32005-01-22 23:41:55 +00008//===----------------------------------------------------------------------===//
9//
10// This file contains the Alpha implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ALPHAINSTRUCTIONINFO_H
15#define ALPHAINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "AlphaRegisterInfo.h"
19
20namespace llvm {
21
Chris Lattner64105522008-01-01 01:03:04 +000022class AlphaInstrInfo : public TargetInstrInfoImpl {
Andrew Lenharth304d0f32005-01-22 23:41:55 +000023 const AlphaRegisterInfo RI;
24public:
25 AlphaInstrInfo();
26
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
30 ///
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +000031 virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
Andrew Lenharth304d0f32005-01-22 23:41:55 +000032
Evan Cheng04ee5a12009-01-20 19:12:24 +000033 /// Return true if the instruction is a register to register move and return
34 /// the source and dest operands and their sub-register indices by reference.
Andrew Lenharth304d0f32005-01-22 23:41:55 +000035 virtual bool isMoveInstr(const MachineInstr &MI,
Evan Cheng04ee5a12009-01-20 19:12:24 +000036 unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
Chris Lattner40839602006-02-02 20:12:32 +000038
Dan Gohmancbad42c2008-11-18 19:49:32 +000039 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
40 int &FrameIndex) const;
41 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
42 int &FrameIndex) const;
Chris Lattner0476b282006-10-24 16:41:36 +000043
Evan Chengb5cdaa22007-05-18 00:05:48 +000044 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
Stuart Hastings3bf91252010-06-17 22:43:56 +000045 MachineBasicBlock *FBB,
46 const SmallVectorImpl<MachineOperand> &Cond,
47 DebugLoc DL) const;
Jakob Stoklund Olesen99666a32010-07-11 01:08:23 +000048 virtual void copyPhysReg(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MI, DebugLoc DL,
50 unsigned DestReg, unsigned SrcReg,
51 bool KillSrc) const;
Owen Andersonf6372aa2008-01-01 21:11:32 +000052 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MBBI,
54 unsigned SrcReg, bool isKill, int FrameIndex,
Evan Cheng746ad692010-05-06 19:06:44 +000055 const TargetRegisterClass *RC,
56 const TargetRegisterInfo *TRI) const;
Owen Andersonf6372aa2008-01-01 21:11:32 +000057
Owen Andersonf6372aa2008-01-01 21:11:32 +000058 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator MBBI,
60 unsigned DestReg, int FrameIndex,
Evan Cheng746ad692010-05-06 19:06:44 +000061 const TargetRegisterClass *RC,
62 const TargetRegisterInfo *TRI) const;
Owen Anderson43dbe052008-01-07 01:35:02 +000063
Dan Gohmanc54baa22008-12-03 18:43:12 +000064 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
65 MachineInstr* MI,
66 const SmallVectorImpl<unsigned> &Ops,
67 int FrameIndex) const;
Owen Anderson43dbe052008-01-07 01:35:02 +000068
Dan Gohmanc54baa22008-12-03 18:43:12 +000069 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
70 MachineInstr* MI,
71 const SmallVectorImpl<unsigned> &Ops,
72 MachineInstr* LoadMI) const {
Owen Anderson43dbe052008-01-07 01:35:02 +000073 return 0;
74 }
75
Andrew Lenharthf81173f2006-10-31 16:49:55 +000076 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
77 MachineBasicBlock *&FBB,
Evan Chengdc54d312009-02-09 07:14:22 +000078 SmallVectorImpl<MachineOperand> &Cond,
79 bool AllowModify) const;
Evan Chengb5cdaa22007-05-18 00:05:48 +000080 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
Andrew Lenharthf81173f2006-10-31 16:49:55 +000081 void insertNoop(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MI) const;
Owen Anderson44eb65c2008-08-14 22:49:33 +000083 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
Dan Gohman99114052009-06-03 20:30:14 +000084
85 /// getGlobalBaseReg - Return a virtual register initialized with the
86 /// the global base register value. Output instructions required to
87 /// initialize the register in the function entry block, if necessary.
88 ///
89 unsigned getGlobalBaseReg(MachineFunction *MF) const;
90
91 /// getGlobalRetAddr - Return a virtual register initialized with the
92 /// the global return address register value. Output instructions required to
93 /// initialize the register in the function entry block, if necessary.
94 ///
95 unsigned getGlobalRetAddr(MachineFunction *MF) const;
Andrew Lenharth304d0f32005-01-22 23:41:55 +000096};
97
98}
99
100#endif