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Jia Liu31d157a2012-02-18 12:03:15 +00001//===-- SPU.td - Describe the STI Cell SPU Target Machine --*- tablegen -*-===//
2//
Scott Michela589a082007-12-03 23:14:43 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Scott Michela589a082007-12-03 23:14:43 +00007//
Scott Michela589a082007-12-03 23:14:43 +00008//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the STI Cell SPU target machine.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing.
15//
Evan Cheng027fdbe2008-11-24 07:34:46 +000016include "llvm/Target/Target.td"
Scott Michela589a082007-12-03 23:14:43 +000017
Scott Michel02d711b2008-12-30 23:28:25 +000018// Holder of code fragments (you'd think this'd already be in
19// a td file somewhere... :-)
20
21class CodeFrag<dag frag> {
22 dag Fragment = frag;
23}
24
Scott Michela589a082007-12-03 23:14:43 +000025//===----------------------------------------------------------------------===//
26// Register File Description
27//===----------------------------------------------------------------------===//
28
29include "SPURegisterInfo.td"
30
31//===----------------------------------------------------------------------===//
32// Instruction formats, instructions
33//===----------------------------------------------------------------------===//
34
35include "SPUNodes.td"
36include "SPUOperands.td"
37include "SPUSchedule.td"
38include "SPUInstrFormats.td"
39include "SPUInstrInfo.td"
40
41//===----------------------------------------------------------------------===//
42// Subtarget features:
43//===----------------------------------------------------------------------===//
44
45def DefaultProc: SubtargetFeature<"", "ProcDirective", "SPU::DEFAULT_PROC", "">;
46def LargeMemFeature:
47 SubtargetFeature<"large_mem","UseLargeMem", "true",
48 "Use large (>256) LSA memory addressing [default = false]">;
49
50def SPURev0 : Processor<"v0", SPUItineraries, [DefaultProc]>;
51
52//===----------------------------------------------------------------------===//
53// Calling convention:
54//===----------------------------------------------------------------------===//
55
56include "SPUCallingConv.td"
57
58// Target:
59
60def SPUInstrInfo : InstrInfo {
61 let isLittleEndianEncoding = 1;
62}
63
64def SPU : Target {
65 let InstructionSet = SPUInstrInfo;
66}