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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / c23b933d5f8be9b51a1d22e717c0311f65f87dcd / . / lib / Target / PowerPC / PPCScheduleG4Plus.td
blob: e7446cb028a365f5f63a04371dd380b5cbc6c739 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
2//
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]7//
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the G4+ (7450) processor.
11//
12//===----------------------------------------------------------------------===//
13
Anton Korobeynikov928eb492010-04-18 20:31:01 +0000[diff] [blame]14def IU3 : FuncUnit; // integer unit 3 (7450 simple)
15def IU4 : FuncUnit; // integer unit 4 (7450 simple)
16
17def G4PlusItineraries : ProcessorItineraries<
Evan Cheng63d66ee2010-09-28 23:50:49 +0000[diff] [blame]18 [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [
Hal Finkel16803092012-06-12 19:01:24 +0000[diff] [blame]19 InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]20 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
21 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]22 InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
23 InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>,
24 InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>,
25 InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]26 InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>,
27 InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>,
28 InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]29 InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
30 InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]31 InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
32 InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
33 InstrItinData<BrCR , [InstrStage<2, [IU2]>]>,
34 InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>,
35 InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]36 InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
37 InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
Hal Finkel20b529b2012-04-01 04:44:16 +0000[diff] [blame]38 InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>,
39 InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]40 InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
41 InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]42 InstrItinData<LdStUX , [InstrStage<3, [SLU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]43 InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
44 InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
45 InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
46 InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>,
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]47 InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]48 InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
49 InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]50 InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
51 InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>,
52 InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>,
53 InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>,
54 InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
55 InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
56 InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>,
57 InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>,
58 InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>,
59 InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>,
60 InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>,
61 InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>,
62 InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>,
63 InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>,
64 InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>,
65 InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>,
66 InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
67 InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
68 InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>,
69 InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>,
70 InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>,
71 InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>,
72 InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>,
73 InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]74 InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
75 InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
76 InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
77 InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>,
78 InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>,
79 InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>,
80 InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>,
81 InstrItinData<VecVSR , [InstrStage<2, [VPU]>]>
82]>;