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Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]6 <title>Writing an LLVM Compiler Backend</title>
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8</head>
9
10<body>
11
Chris Lattner611944b2008-11-11 19:31:26 +0000[diff] [blame]12<div class="doc_title">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]13 Writing an LLVM Compiler Backend
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]14</div>
15
16<ol>
17 <li><a href="#intro">Introduction</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]18 <ul>
19 <li><a href="#Audience">Audience</a></li>
20 <li><a href="#Prerequisite">Prerequisite Reading</a></li>
21 <li><a href="#Basic">Basic Steps</a></li>
22 <li><a href="#Preliminaries">Preliminaries</a></li>
23 </ul>
24 <li><a href="#TargetMachine">Target Machine</a></li>
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]25 <li><a href="#TargetRegistration">Target Registration</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]26 <li><a href="#RegisterSet">Register Set and Register Classes</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]27 <ul>
28 <li><a href="#RegisterDef">Defining a Register</a></li>
29 <li><a href="#RegisterClassDef">Defining a Register Class</a></li>
30 <li><a href="#implementRegister">Implement a subclass of TargetRegisterInfo</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]31 </ul></li>
32 <li><a href="#InstructionSet">Instruction Set</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]33 <ul>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]34 <li><a href="#operandMapping">Instruction Operand Mapping</a></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]35 <li><a href="#implementInstr">Implement a subclass of TargetInstrInfo</a></li>
36 <li><a href="#branchFolding">Branch Folding and If Conversion</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]37 </ul></li>
38 <li><a href="#InstructionSelector">Instruction Selector</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]39 <ul>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]40 <li><a href="#LegalizePhase">The SelectionDAG Legalize Phase</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]41 <ul>
42 <li><a href="#promote">Promote</a></li>
43 <li><a href="#expand">Expand</a></li>
44 <li><a href="#custom">Custom</a></li>
45 <li><a href="#legal">Legal</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]46 </ul></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]47 <li><a href="#callingConventions">Calling Conventions</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]48 </ul></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]49 <li><a href="#assemblyPrinter">Assembly Printer</a></li>
50 <li><a href="#subtargetSupport">Subtarget Support</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]51 <li><a href="#jitSupport">JIT Support</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]52 <ul>
53 <li><a href="#mce">Machine Code Emitter</a></li>
54 <li><a href="#targetJITInfo">Target JIT Info</a></li>
Chris Lattner528875c2008-11-11 19:34:28 +0000[diff] [blame]55 </ul></li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]56</ol>
57
58<div class="doc_author">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]59 <p>Written by <a href="http://www.woo.com">Mason Woo</a> and
60 <a href="http://misha.brukman.net">Misha Brukman</a></p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]61</div>
62
63<!-- *********************************************************************** -->
64<div class="doc_section">
65 <a name="intro">Introduction</a>
66</div>
67<!-- *********************************************************************** -->
68
69<div class="doc_text">
70
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]71<p>
72This document describes techniques for writing compiler backends that convert
73the LLVM Intermediate Representation (IR) to code for a specified machine or
74other languages. Code intended for a specific machine can take the form of
75either assembly code or binary code (usable for a JIT compiler).
76</p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]77
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]78<p>
79The backend of LLVM features a target-independent code generator that may create
80output for several types of target CPUs &mdash; including X86, PowerPC, Alpha,
81and SPARC. The backend may also be used to generate code targeted at SPUs of the
82Cell processor or GPUs to support the execution of compute kernels.
83</p>
84
85<p>
86The document focuses on existing examples found in subdirectories
87of <tt>llvm/lib/Target</tt> in a downloaded LLVM release. In particular, this
88document focuses on the example of creating a static compiler (one that emits
89text assembly) for a SPARC target, because SPARC has fairly standard
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]90characteristics, such as a RISC instruction set and straightforward calling
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]91conventions.
92</p>
93
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]94</div>
95
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]96<div class="doc_subsection">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]97 <a name="Audience">Audience</a>
98</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]99
100<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]101
102<p>
103The audience for this document is anyone who needs to write an LLVM backend to
104generate code for a specific hardware or software target.
105</p>
106
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]107</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]108
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]109<div class="doc_subsection">
110 <a name="Prerequisite">Prerequisite Reading</a>
111</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]112
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]113<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]114
115<p>
116These essential documents must be read before reading this document:
117</p>
118
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]119<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]120<li><i><a href="http://www.llvm.org/docs/LangRef.html">LLVM Language Reference
121 Manual</a></i> &mdash; a reference manual for the LLVM assembly language.</li>
122
123<li><i><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
124 Target-Independent Code Generator</a></i> &mdash; a guide to the components
125 (classes and code generation algorithms) for translating the LLVM internal
126 representation into machine code for a specified target. Pay particular
127 attention to the descriptions of code generation stages: Instruction
128 Selection, Scheduling and Formation, SSA-based Optimization, Register
129 Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations,
130 and Code Emission.</li>
131
132<li><i><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen
133 Fundamentals</a></i> &mdash;a document that describes the TableGen
134 (<tt>tblgen</tt>) application that manages domain-specific information to
135 support LLVM code generation. TableGen processes input from a target
136 description file (<tt>.td</tt> suffix) and generates C++ code that can be
137 used for code generation.</li>
138
139<li><i><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM
140 Pass</a></i> &mdash; The assembly printer is a <tt>FunctionPass</tt>, as are
141 several SelectionDAG processing steps.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]142</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]143
144<p>
145To follow the SPARC examples in this document, have a copy of
146<i><a href="http://www.sparc.org/standards/V8.pdf">The SPARC Architecture
147Manual, Version 8</a></i> for reference. For details about the ARM instruction
148set, refer to the <i><a href="http://infocenter.arm.com/">ARM Architecture
149Reference Manual</a></i>. For more about the GNU Assembler format
150(<tt>GAS</tt>), see
151<i><a href="http://sourceware.org/binutils/docs/as/index.html">Using As</a></i>,
152especially for the assembly printer. <i>Using As</i> contains a list of target
153machine dependent features.
154</p>
155
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]156</div>
157
158<div class="doc_subsection">
159 <a name="Basic">Basic Steps</a>
160</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]161
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]162<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]163
164<p>
165To write a compiler backend for LLVM that converts the LLVM IR to code for a
166specified target (machine or other language), follow these steps:
167</p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]168
169<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]170<li>Create a subclass of the TargetMachine class that describes characteristics
171 of your target machine. Copy existing examples of specific TargetMachine
172 class and header files; for example, start with
173 <tt>SparcTargetMachine.cpp</tt> and <tt>SparcTargetMachine.h</tt>, but
174 change the file names for your target. Similarly, change code that
175 references "Sparc" to reference your target. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]176
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]177<li>Describe the register set of the target. Use TableGen to generate code for
178 register definition, register aliases, and register classes from a
179 target-specific <tt>RegisterInfo.td</tt> input file. You should also write
180 additional code for a subclass of the TargetRegisterInfo class that
181 represents the class register file data used for register allocation and
182 also describes the interactions between registers.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]183
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]184<li>Describe the instruction set of the target. Use TableGen to generate code
185 for target-specific instructions from target-specific versions of
186 <tt>TargetInstrFormats.td</tt> and <tt>TargetInstrInfo.td</tt>. You should
187 write additional code for a subclass of the TargetInstrInfo class to
188 represent machine instructions supported by the target machine. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]189
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]190<li>Describe the selection and conversion of the LLVM IR from a Directed Acyclic
191 Graph (DAG) representation of instructions to native target-specific
192 instructions. Use TableGen to generate code that matches patterns and
193 selects instructions based on additional information in a target-specific
194 version of <tt>TargetInstrInfo.td</tt>. Write code
195 for <tt>XXXISelDAGToDAG.cpp</tt>, where XXX identifies the specific target,
196 to perform pattern matching and DAG-to-DAG instruction selection. Also write
197 code in <tt>XXXISelLowering.cpp</tt> to replace or remove operations and
198 data types that are not supported natively in a SelectionDAG. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]199
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]200<li>Write code for an assembly printer that converts LLVM IR to a GAS format for
201 your target machine. You should add assembly strings to the instructions
202 defined in your target-specific version of <tt>TargetInstrInfo.td</tt>. You
203 should also write code for a subclass of AsmPrinter that performs the
204 LLVM-to-assembly conversion and a trivial subclass of TargetAsmInfo.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]205
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]206<li>Optionally, add support for subtargets (i.e., variants with different
207 capabilities). You should also write code for a subclass of the
208 TargetSubtarget class, which allows you to use the <tt>-mcpu=</tt>
209 and <tt>-mattr=</tt> command-line options.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]210
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]211<li>Optionally, add JIT support and create a machine code emitter (subclass of
212 TargetJITInfo) that is used to emit binary code directly into memory. </li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]213</ul>
214
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]215<p>
216In the <tt>.cpp</tt> and <tt>.h</tt>. files, initially stub up these methods and
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]217then implement them later. Initially, you may not know which private members
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]218that the class will need and which components will need to be subclassed.
219</p>
220
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]221</div>
222
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]223<div class="doc_subsection">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]224 <a name="Preliminaries">Preliminaries</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]225</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]226
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]227<div class="doc_text">
228
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]229<p>
230To actually create your compiler backend, you need to create and modify a few
231files. The absolute minimum is discussed here. But to actually use the LLVM
232target-independent code generator, you must perform the steps described in
233the <a href="http://www.llvm.org/docs/CodeGenerator.html">LLVM
234Target-Independent Code Generator</a> document.
235</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]236
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]237<p>
238First, you should create a subdirectory under <tt>lib/Target</tt> to hold all
239the files related to your target. If your target is called "Dummy," create the
240directory <tt>lib/Target/Dummy</tt>.
241</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]242
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]243<p>
244In this new
245directory, create a <tt>Makefile</tt>. It is easiest to copy a
246<tt>Makefile</tt> of another target and modify it. It should at least contain
247the <tt>LEVEL</tt>, <tt>LIBRARYNAME</tt> and <tt>TARGET</tt> variables, and then
248include <tt>$(LEVEL)/Makefile.common</tt>. The library can be
249named <tt>LLVMDummy</tt> (for example, see the MIPS target). Alternatively, you
250can split the library into <tt>LLVMDummyCodeGen</tt>
251and <tt>LLVMDummyAsmPrinter</tt>, the latter of which should be implemented in a
252subdirectory below <tt>lib/Target/Dummy</tt> (for example, see the PowerPC
253target).
254</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]255
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]256<p>
257Note that these two naming schemes are hardcoded into <tt>llvm-config</tt>.
258Using any other naming scheme will confuse <tt>llvm-config</tt> and produce a
259lot of (seemingly unrelated) linker errors when linking <tt>llc</tt>.
260</p>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]261
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]262<p>
263To make your target actually do something, you need to implement a subclass of
264<tt>TargetMachine</tt>. This implementation should typically be in the file
265<tt>lib/Target/DummyTargetMachine.cpp</tt>, but any file in
266the <tt>lib/Target</tt> directory will be built and should work. To use LLVM's
267target independent code generator, you should do what all current machine
268backends do: create a subclass of <tt>LLVMTargetMachine</tt>. (To create a
269target from scratch, create a subclass of <tt>TargetMachine</tt>.)
270</p>
271
272<p>
273To get LLVM to actually build and link your target, you need to add it to
274the <tt>TARGETS_TO_BUILD</tt> variable. To do this, you modify the configure
275script to know about your target when parsing the <tt>--enable-targets</tt>
276option. Search the configure script for <tt>TARGETS_TO_BUILD</tt>, add your
277target to the lists there (some creativity required), and then
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]278reconfigure. Alternatively, you can change <tt>autotools/configure.ac</tt> and
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]279regenerate configure by running <tt>./autoconf/AutoRegen.sh</tt>.
280</p>
281
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame]282</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]283
284<!-- *********************************************************************** -->
285<div class="doc_section">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]286 <a name="TargetMachine">Target Machine</a>
287</div>
288<!-- *********************************************************************** -->
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]289
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]290<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]291
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]292<p>
293<tt>LLVMTargetMachine</tt> is designed as a base class for targets implemented
294with the LLVM target-independent code generator. The <tt>LLVMTargetMachine</tt>
295class should be specialized by a concrete target class that implements the
296various virtual methods. <tt>LLVMTargetMachine</tt> is defined as a subclass of
297<tt>TargetMachine</tt> in <tt>include/llvm/Target/TargetMachine.h</tt>. The
298<tt>TargetMachine</tt> class implementation (<tt>TargetMachine.cpp</tt>) also
299processes numerous command-line options.
300</p>
301
302<p>
303To create a concrete target-specific subclass of <tt>LLVMTargetMachine</tt>,
304start by copying an existing <tt>TargetMachine</tt> class and header. You
305should name the files that you create to reflect your specific target. For
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]306instance, for the SPARC target, name the files <tt>SparcTargetMachine.h</tt> and
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]307<tt>SparcTargetMachine.cpp</tt>.
308</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]309
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]310<p>
311For a target machine <tt>XXX</tt>, the implementation of
312<tt>XXXTargetMachine</tt> must have access methods to obtain objects that
313represent target components. These methods are named <tt>get*Info</tt>, and are
314intended to obtain the instruction set (<tt>getInstrInfo</tt>), register set
315(<tt>getRegisterInfo</tt>), stack frame layout (<tt>getFrameInfo</tt>), and
316similar information. <tt>XXXTargetMachine</tt> must also implement the
317<tt>getTargetData</tt> method to access an object with target-specific data
318characteristics, such as data type size and alignment requirements.
319</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]320
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]321<p>
322For instance, for the SPARC target, the header file
323<tt>SparcTargetMachine.h</tt> declares prototypes for several <tt>get*Info</tt>
324and <tt>getTargetData</tt> methods that simply return a class member.
325</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]326
327<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]328<pre>
329namespace llvm {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]330
331class Module;
332
333class SparcTargetMachine : public LLVMTargetMachine {
334 const TargetData DataLayout; // Calculates type size &amp; alignment
335 SparcSubtarget Subtarget;
336 SparcInstrInfo InstrInfo;
337 TargetFrameInfo FrameInfo;
338
339protected:
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]340 virtual const TargetAsmInfo *createTargetAsmInfo() const;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]341
342public:
343 SparcTargetMachine(const Module &amp;M, const std::string &amp;FS);
344
345 virtual const SparcInstrInfo *getInstrInfo() const {return &amp;InstrInfo; }
346 virtual const TargetFrameInfo *getFrameInfo() const {return &amp;FrameInfo; }
347 virtual const TargetSubtarget *getSubtargetImpl() const{return &amp;Subtarget; }
348 virtual const TargetRegisterInfo *getRegisterInfo() const {
349 return &amp;InstrInfo.getRegisterInfo();
350 }
351 virtual const TargetData *getTargetData() const { return &amp;DataLayout; }
352 static unsigned getModuleMatchQuality(const Module &amp;M);
353
354 // Pass Pipeline Configuration
355 virtual bool addInstSelector(PassManagerBase &amp;PM, bool Fast);
356 virtual bool addPreEmitPass(PassManagerBase &amp;PM, bool Fast);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]357};
358
359} // end namespace llvm
360</pre>
361</div>
362
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]363</div>
364
365
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]366<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]367
368<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]369<li><tt>getInstrInfo()</tt></li>
370<li><tt>getRegisterInfo()</tt></li>
371<li><tt>getFrameInfo()</tt></li>
372<li><tt>getTargetData()</tt></li>
373<li><tt>getSubtargetImpl()</tt></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]374</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]375
376<p>For some targets, you also need to support the following methods:</p>
377
378<ul>
379<li><tt>getTargetLowering()</tt></li>
380<li><tt>getJITInfo()</tt></li>
381</ul>
382
383<p>
384In addition, the <tt>XXXTargetMachine</tt> constructor should specify a
385<tt>TargetDescription</tt> string that determines the data layout for the target
386machine, including characteristics such as pointer size, alignment, and
387endianness. For example, the constructor for SparcTargetMachine contains the
388following:
389</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]390
391<div class="doc_code">
392<pre>
393SparcTargetMachine::SparcTargetMachine(const Module &amp;M, const std::string &amp;FS)
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]394 : DataLayout("E-p:32:32-f128:128:128"),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]395 Subtarget(M, FS), InstrInfo(Subtarget),
396 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
397}
398</pre>
399</div>
400
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]401</div>
402
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]403<div class="doc_text">
404
405<p>Hyphens separate portions of the <tt>TargetDescription</tt> string.</p>
406
407<ul>
408<li>An upper-case "<tt>E</tt>" in the string indicates a big-endian target data
409 model. a lower-case "<tt>e</tt>" indicates little-endian.</li>
410
411<li>"<tt>p:</tt>" is followed by pointer information: size, ABI alignment, and
412 preferred alignment. If only two figures follow "<tt>p:</tt>", then the
413 first value is pointer size, and the second value is both ABI and preferred
414 alignment.</li>
415
416<li>Then a letter for numeric type alignment: "<tt>i</tt>", "<tt>f</tt>",
417 "<tt>v</tt>", or "<tt>a</tt>" (corresponding to integer, floating point,
418 vector, or aggregate). "<tt>i</tt>", "<tt>v</tt>", or "<tt>a</tt>" are
419 followed by ABI alignment and preferred alignment. "<tt>f</tt>" is followed
420 by three values: the first indicates the size of a long double, then ABI
421 alignment, and then ABI preferred alignment.</li>
422</ul>
423
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]424</div>
425
426<!-- *********************************************************************** -->
427<div class="doc_section">
428 <a name="TargetRegistration">Target Registration</a>
429</div>
430<!-- *********************************************************************** -->
431
432<div class="doc_text">
433
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]434<p>
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]435You must also register your target with the <tt>TargetRegistry</tt>, which is
436what other LLVM tools use to be able to lookup and use your target at
437runtime. The <tt>TargetRegistry</tt> can be used directly, but for most targets
438there are helper templates which should take care of the work for you.</p>
439
440<p>
441All targets should declare a global <tt>Target</tt> object which is used to
442represent the target during registration. Then, in the target's TargetInfo
443library, the target should define that object and use
444the <tt>RegisterTarget</tt> template to register the target. For example, the Sparc registration code looks like this:
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]445</p>
446
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]447<div class="doc_code">
448<pre>
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]449Target llvm::TheSparcTarget;
450
451extern "C" void LLVMInitializeSparcTargetInfo() {
Benjamin Kramere15192b2009-08-05 15:42:44 +0000[diff] [blame]452 RegisterTarget&lt;Triple::sparc, /*HasJIT=*/false&gt;
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]453 X(TheSparcTarget, "sparc", "Sparc");
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]454}
455</pre>
456</div>
457
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]458<p>
459This allows the <tt>TargetRegistry</tt> to look up the target by name or by
460target triple. In addition, most targets will also register additional features
461which are available in separate libraries. These registration steps are
462separate, because some clients may wish to only link in some parts of the target
463-- the JIT code generator does not require the use of the assembler printer, for
464example. Here is an example of registering the Sparc assembly printer:
465</p>
466
467<div class="doc_code">
468<pre>
469extern "C" void LLVMInitializeSparcAsmPrinter() {
Benjamin Kramere15192b2009-08-05 15:42:44 +0000[diff] [blame]470 RegisterAsmPrinter&lt;SparcAsmPrinter&gt; X(TheSparcTarget);
Daniel Dunbard6b06b12009-07-26 05:41:39 +0000[diff] [blame]471}
472</pre>
473</div>
474
475<p>
476For more information, see
477"<a href="/doxygen/TargetRegistry_8h-source.html">llvm/Target/TargetRegistry.h</a>".
478</p>
479
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]480</div>
481
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]482<!-- *********************************************************************** -->
483<div class="doc_section">
484 <a name="RegisterSet">Register Set and Register Classes</a>
485</div>
486<!-- *********************************************************************** -->
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]487
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]488<div class="doc_text">
489
490<p>
491You should describe a concrete target-specific class that represents the
492register file of a target machine. This class is called <tt>XXXRegisterInfo</tt>
493(where <tt>XXX</tt> identifies the target) and represents the class register
494file data that is used for register allocation. It also describes the
495interactions between registers.
496</p>
497
498<p>
499You also need to define register classes to categorize related registers. A
500register class should be added for groups of registers that are all treated the
501same way for some instruction. Typical examples are register classes for
502integer, floating-point, or vector registers. A register allocator allows an
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]503instruction to use any register in a specified register class to perform the
504instruction in a similar manner. Register classes allocate virtual registers to
505instructions from these sets, and register classes let the target-independent
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]506register allocator automatically choose the actual registers.
507</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]508
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]509<p>
510Much of the code for registers, including register definition, register aliases,
511and register classes, is generated by TableGen from <tt>XXXRegisterInfo.td</tt>
512input files and placed in <tt>XXXGenRegisterInfo.h.inc</tt> and
513<tt>XXXGenRegisterInfo.inc</tt> output files. Some of the code in the
514implementation of <tt>XXXRegisterInfo</tt> requires hand-coding.
515</p>
516
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]517</div>
518
519<!-- ======================================================================= -->
520<div class="doc_subsection">
521 <a name="RegisterDef">Defining a Register</a>
522</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]523
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]524<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]525
526<p>
527The <tt>XXXRegisterInfo.td</tt> file typically starts with register definitions
528for a target machine. The <tt>Register</tt> class (specified
529in <tt>Target.td</tt>) is used to define an object for each register. The
530specified string <tt>n</tt> becomes the <tt>Name</tt> of the register. The
531basic <tt>Register</tt> object does not have any subregisters and does not
532specify any aliases.
533</p>
534
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]535<div class="doc_code">
536<pre>
537class Register&lt;string n&gt; {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]538 string Namespace = "";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]539 string AsmName = n;
540 string Name = n;
541 int SpillSize = 0;
542 int SpillAlignment = 0;
543 list&lt;Register&gt; Aliases = [];
544 list&lt;Register&gt; SubRegs = [];
545 list&lt;int&gt; DwarfNumbers = [];
546}
547</pre>
548</div>
549
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]550<p>
551For example, in the <tt>X86RegisterInfo.td</tt> file, there are register
552definitions that utilize the Register class, such as:
553</p>
554
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]555<div class="doc_code">
556<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]557def AL : Register&lt;"AL"&gt;, DwarfRegNum&lt;[0, 0, 0]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]558</pre>
559</div>
560
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]561<p>
562This defines the register <tt>AL</tt> and assigns it values (with
563<tt>DwarfRegNum</tt>) that are used by <tt>gcc</tt>, <tt>gdb</tt>, or a debug
564information writer (such as <tt>DwarfWriter</tt>
565in <tt>llvm/lib/CodeGen/AsmPrinter</tt>) to identify a register. For register
566<tt>AL</tt>, <tt>DwarfRegNum</tt> takes an array of 3 values representing 3
567different modes: the first element is for X86-64, the second for exception
568handling (EH) on X86-32, and the third is generic. -1 is a special Dwarf number
569that indicates the gcc number is undefined, and -2 indicates the register number
570is invalid for this mode.
571</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]572
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]573<p>
574From the previously described line in the <tt>X86RegisterInfo.td</tt> file,
575TableGen generates this code in the <tt>X86GenRegisterInfo.inc</tt> file:
576</p>
577
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]578<div class="doc_code">
579<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]580static const unsigned GR8[] = { X86::AL, ... };
581
582const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
583
584const TargetRegisterDesc RegisterDescriptors[] = {
585 ...
586{ "AL", "AL", AL_AliasSet, Empty_SubRegsSet, Empty_SubRegsSet, AL_SuperRegsSet }, ...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]587</pre>
588</div>
589
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]590<p>
591From the register info file, TableGen generates a <tt>TargetRegisterDesc</tt>
592object for each register. <tt>TargetRegisterDesc</tt> is defined in
593<tt>include/llvm/Target/TargetRegisterInfo.h</tt> with the following fields:
594</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]595
596<div class="doc_code">
597<pre>
598struct TargetRegisterDesc {
599 const char *AsmName; // Assembly language name for the register
600 const char *Name; // Printable name for the reg (for debugging)
601 const unsigned *AliasSet; // Register Alias Set
602 const unsigned *SubRegs; // Sub-register set
603 const unsigned *ImmSubRegs; // Immediate sub-register set
604 const unsigned *SuperRegs; // Super-register set
605};</pre>
606</div>
607
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]608<p>
609TableGen uses the entire target description file (<tt>.td</tt>) to determine
610text names for the register (in the <tt>AsmName</tt> and <tt>Name</tt> fields of
611<tt>TargetRegisterDesc</tt>) and the relationships of other registers to the
612defined register (in the other <tt>TargetRegisterDesc</tt> fields). In this
613example, other definitions establish the registers "<tt>AX</tt>",
614"<tt>EAX</tt>", and "<tt>RAX</tt>" as aliases for one another, so TableGen
615generates a null-terminated array (<tt>AL_AliasSet</tt>) for this register alias
616set.
617</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]618
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]619<p>
620The <tt>Register</tt> class is commonly used as a base class for more complex
621classes. In <tt>Target.td</tt>, the <tt>Register</tt> class is the base for the
622<tt>RegisterWithSubRegs</tt> class that is used to define registers that need to
623specify subregisters in the <tt>SubRegs</tt> list, as shown here:
624</p>
625
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]626<div class="doc_code">
627<pre>
628class RegisterWithSubRegs&lt;string n,
629list&lt;Register&gt; subregs&gt; : Register&lt;n&gt; {
630 let SubRegs = subregs;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]631}
632</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]633</div>
634
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]635<p>
636In <tt>SparcRegisterInfo.td</tt>, additional register classes are defined for
637SPARC: a Register subclass, SparcReg, and further subclasses: <tt>Ri</tt>,
638<tt>Rf</tt>, and <tt>Rd</tt>. SPARC registers are identified by 5-bit ID
639numbers, which is a feature common to these subclasses. Note the use of
640'<tt>let</tt>' expressions to override values that are initially defined in a
641superclass (such as <tt>SubRegs</tt> field in the <tt>Rd</tt> class).
642</p>
643
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]644<div class="doc_code">
645<pre>
646class SparcReg&lt;string n&gt; : Register&lt;n&gt; {
647 field bits&lt;5&gt; Num;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]648 let Namespace = "SP";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]649}
650// Ri - 32-bit integer registers
651class Ri&lt;bits&lt;5&gt; num, string n&gt; :
652SparcReg&lt;n&gt; {
653 let Num = num;
654}
655// Rf - 32-bit floating-point registers
656class Rf&lt;bits&lt;5&gt; num, string n&gt; :
657SparcReg&lt;n&gt; {
658 let Num = num;
659}
660// Rd - Slots in the FP register file for 64-bit
661floating-point values.
662class Rd&lt;bits&lt;5&gt; num, string n,
663list&lt;Register&gt; subregs&gt; : SparcReg&lt;n&gt; {
664 let Num = num;
665 let SubRegs = subregs;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]666}
667</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]668</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]669
670<p>
671In the <tt>SparcRegisterInfo.td</tt> file, there are register definitions that
672utilize these subclasses of <tt>Register</tt>, such as:
673</p>
674
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]675<div class="doc_code">
676<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]677def G0 : Ri&lt; 0, "G0"&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]678DwarfRegNum&lt;[0]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]679def G1 : Ri&lt; 1, "G1"&gt;, DwarfRegNum&lt;[1]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]680...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]681def F0 : Rf&lt; 0, "F0"&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]682DwarfRegNum&lt;[32]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]683def F1 : Rf&lt; 1, "F1"&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]684DwarfRegNum&lt;[33]&gt;;
685...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]686def D0 : Rd&lt; 0, "F0", [F0, F1]&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]687DwarfRegNum&lt;[32]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]688def D1 : Rd&lt; 2, "F2", [F2, F3]&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]689DwarfRegNum&lt;[34]&gt;;
690</pre>
691</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]692
693<p>
694The last two registers shown above (<tt>D0</tt> and <tt>D1</tt>) are
695double-precision floating-point registers that are aliases for pairs of
696single-precision floating-point sub-registers. In addition to aliases, the
697sub-register and super-register relationships of the defined register are in
698fields of a register's TargetRegisterDesc.
699</p>
700
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]701</div>
702
703<!-- ======================================================================= -->
704<div class="doc_subsection">
705 <a name="RegisterClassDef">Defining a Register Class</a>
706</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]707
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]708<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]709
710<p>
711The <tt>RegisterClass</tt> class (specified in <tt>Target.td</tt>) is used to
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]712define an object that represents a group of related registers and also defines
713the default allocation order of the registers. A target description file
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]714<tt>XXXRegisterInfo.td</tt> that uses <tt>Target.td</tt> can construct register
715classes using the following class:
716</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]717
718<div class="doc_code">
719<pre>
720class RegisterClass&lt;string namespace,
721list&lt;ValueType&gt; regTypes, int alignment,
722 list&lt;Register&gt; regList&gt; {
723 string Namespace = namespace;
724 list&lt;ValueType&gt; RegTypes = regTypes;
725 int Size = 0; // spill size, in bits; zero lets tblgen pick the size
726 int Alignment = alignment;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]727
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]728 // CopyCost is the cost of copying a value between two registers
729 // default value 1 means a single instruction
730 // A negative value means copying is extremely expensive or impossible
731 int CopyCost = 1;
732 list&lt;Register&gt; MemberList = regList;
733
734 // for register classes that are subregisters of this class
735 list&lt;RegisterClass&gt; SubRegClassList = [];
736
737 code MethodProtos = [{}]; // to insert arbitrary code
738 code MethodBodies = [{}];
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]739}
740</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]741</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]742
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]743<p>To define a RegisterClass, use the following 4 arguments:</p>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]744
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]745<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]746<li>The first argument of the definition is the name of the namespace.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]747
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]748<li>The second argument is a list of <tt>ValueType</tt> register type values
749 that are defined in <tt>include/llvm/CodeGen/ValueTypes.td</tt>. Defined
750 values include integer types (such as <tt>i16</tt>, <tt>i32</tt>,
751 and <tt>i1</tt> for Boolean), floating-point types
752 (<tt>f32</tt>, <tt>f64</tt>), and vector types (for example, <tt>v8i16</tt>
753 for an <tt>8 x i16</tt> vector). All registers in a <tt>RegisterClass</tt>
754 must have the same <tt>ValueType</tt>, but some registers may store vector
755 data in different configurations. For example a register that can process a
756 128-bit vector may be able to handle 16 8-bit integer elements, 8 16-bit
757 integers, 4 32-bit integers, and so on. </li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]758
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]759<li>The third argument of the <tt>RegisterClass</tt> definition specifies the
760 alignment required of the registers when they are stored or loaded to
761 memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]762
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]763<li>The final argument, <tt>regList</tt>, specifies which registers are in this
764 class. If an <tt>allocation_order_*</tt> method is not specified,
765 then <tt>regList</tt> also defines the order of allocation used by the
766 register allocator.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]767</ul>
768
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]769<p>
770In <tt>SparcRegisterInfo.td</tt>, three RegisterClass objects are defined:
771<tt>FPRegs</tt>, <tt>DFPRegs</tt>, and <tt>IntRegs</tt>. For all three register
772classes, the first argument defines the namespace with the string
773'<tt>SP</tt>'. <tt>FPRegs</tt> defines a group of 32 single-precision
774floating-point registers (<tt>F0</tt> to <tt>F31</tt>); <tt>DFPRegs</tt> defines
775a group of 16 double-precision registers
776(<tt>D0-D15</tt>). For <tt>IntRegs</tt>, the <tt>MethodProtos</tt>
777and <tt>MethodBodies</tt> methods are used by TableGen to insert the specified
778code into generated output.
779</p>
780
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]781<div class="doc_code">
782<pre>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]783def FPRegs : RegisterClass&lt;"SP", [f32], 32,
784 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,
785 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]&gt;;
786
787def DFPRegs : RegisterClass&lt;"SP", [f64], 64,
788 [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]789&nbsp;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]790def IntRegs : RegisterClass&lt;"SP", [i32], 32,
791 [L0, L1, L2, L3, L4, L5, L6, L7,
792 I0, I1, I2, I3, I4, I5,
793 O0, O1, O2, O3, O4, O5, O7,
794 G1,
795 // Non-allocatable regs:
796 G2, G3, G4,
797 O6, // stack ptr
798 I6, // frame ptr
799 I7, // return address
800 G0, // constant zero
801 G5, G6, G7 // reserved for kernel
802 ]&gt; {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]803 let MethodProtos = [{
804 iterator allocation_order_end(const MachineFunction &amp;MF) const;
805 }];
806 let MethodBodies = [{
807 IntRegsClass::iterator
808 IntRegsClass::allocation_order_end(const MachineFunction &amp;MF) const {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]809 return end() - 10 // Don't allocate special registers
810 -1;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]811 }
812 }];
813}
814</pre>
815</div>
816
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]817<p>
818Using <tt>SparcRegisterInfo.td</tt> with TableGen generates several output files
819that are intended for inclusion in other source code that you write.
820<tt>SparcRegisterInfo.td</tt> generates <tt>SparcGenRegisterInfo.h.inc</tt>,
821which should be included in the header file for the implementation of the SPARC
822register implementation that you write (<tt>SparcRegisterInfo.h</tt>). In
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]823<tt>SparcGenRegisterInfo.h.inc</tt> a new structure is defined called
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]824<tt>SparcGenRegisterInfo</tt> that uses <tt>TargetRegisterInfo</tt> as its
825base. It also specifies types, based upon the defined register
826classes: <tt>DFPRegsClass</tt>, <tt>FPRegsClass</tt>, and <tt>IntRegsClass</tt>.
827</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]828
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]829<p>
830<tt>SparcRegisterInfo.td</tt> also generates <tt>SparcGenRegisterInfo.inc</tt>,
831which is included at the bottom of <tt>SparcRegisterInfo.cpp</tt>, the SPARC
832register implementation. The code below shows only the generated integer
833registers and associated register classes. The order of registers
834in <tt>IntRegs</tt> reflects the order in the definition of <tt>IntRegs</tt> in
835the target description file. Take special note of the use
836of <tt>MethodBodies</tt> in <tt>SparcRegisterInfo.td</tt> to create code in
837<tt>SparcGenRegisterInfo.inc</tt>. <tt>MethodProtos</tt> generates similar code
838in <tt>SparcGenRegisterInfo.h.inc</tt>.
839</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]840
841<div class="doc_code">
842<pre> // IntRegs Register Class...
843 static const unsigned IntRegs[] = {
844 SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5,
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]845 SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3,
846 SP::I4, SP::I5, SP::O0, SP::O1, SP::O2, SP::O3,
847 SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3,
848 SP::G4, SP::O6, SP::I6, SP::I7, SP::G0, SP::G5,
849 SP::G6, SP::G7,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]850 };
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]851
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]852 // IntRegsVTs Register Class Value Types...
853 static const MVT::ValueType IntRegsVTs[] = {
854 MVT::i32, MVT::Other
855 };
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]856
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]857namespace SP { // Register class instances
858 DFPRegsClass&nbsp;&nbsp;&nbsp; DFPRegsRegClass;
859 FPRegsClass&nbsp;&nbsp;&nbsp;&nbsp; FPRegsRegClass;
860 IntRegsClass&nbsp;&nbsp;&nbsp; IntRegsRegClass;
861...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]862 // IntRegs Sub-register Classess...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]863 static const TargetRegisterClass* const IntRegsSubRegClasses [] = {
864 NULL
865 };
866...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]867 // IntRegs Super-register Classess...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]868 static const TargetRegisterClass* const IntRegsSuperRegClasses [] = {
869 NULL
870 };
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]871...
872 // IntRegs Register Class sub-classes...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]873 static const TargetRegisterClass* const IntRegsSubclasses [] = {
874 NULL
875 };
876...
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]877 // IntRegs Register Class super-classes...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]878 static const TargetRegisterClass* const IntRegsSuperclasses [] = {
879 NULL
880 };
881...
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]882 IntRegsClass::iterator
883 IntRegsClass::allocation_order_end(const MachineFunction &amp;MF) const {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]884 return end()-10 // Don't allocate special registers
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]885 -1;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]886 }
887
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]888 IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID,
889 IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses,
890 IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]891}
892</pre>
893</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]894
895</div>
896
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]897<!-- ======================================================================= -->
898<div class="doc_subsection">
Chris Lattner7d12b4b2008-11-11 19:36:31 +0000[diff] [blame]899 <a name="implementRegister">Implement a subclass of</a>
900 <a href="http://www.llvm.org/docs/CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]901</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]902
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]903<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]904
905<p>
906The final step is to hand code portions of <tt>XXXRegisterInfo</tt>, which
907implements the interface described in <tt>TargetRegisterInfo.h</tt>. These
908functions return <tt>0</tt>, <tt>NULL</tt>, or <tt>false</tt>, unless
909overridden. Here is a list of functions that are overridden for the SPARC
910implementation in <tt>SparcRegisterInfo.cpp</tt>:
911</p>
912
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]913<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]914<li><tt>getCalleeSavedRegs</tt> &mdash; Returns a list of callee-saved registers
915 in the order of the desired callee-save stack frame offset.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]916
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]917<li><tt>getCalleeSavedRegClasses</tt> &mdash; Returns a list of preferred
918 register classes with which to spill each callee saved register.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]919
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]920<li><tt>getReservedRegs</tt> &mdash; Returns a bitset indexed by physical
921 register numbers, indicating if a particular register is unavailable.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]922
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]923<li><tt>hasFP</tt> &mdash; Return a Boolean indicating if a function should have
924 a dedicated frame pointer register.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]925
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]926<li><tt>eliminateCallFramePseudoInstr</tt> &mdash; If call frame setup or
927 destroy pseudo instructions are used, this can be called to eliminate
928 them.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]929
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]930<li><tt>eliminateFrameIndex</tt> &mdash; Eliminate abstract frame indices from
931 instructions that may use them.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]932
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]933<li><tt>emitPrologue</tt> &mdash; Insert prologue code into the function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]934
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]935<li><tt>emitEpilogue</tt> &mdash; Insert epilogue code into the function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]936</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]937
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]938</div>
939
940<!-- *********************************************************************** -->
941<div class="doc_section">
942 <a name="InstructionSet">Instruction Set</a>
943</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]944
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]945<!-- *********************************************************************** -->
946<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]947
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]948<p>
949During the early stages of code generation, the LLVM IR code is converted to a
950<tt>SelectionDAG</tt> with nodes that are instances of the <tt>SDNode</tt> class
951containing target instructions. An <tt>SDNode</tt> has an opcode, operands, type
952requirements, and operation properties. For example, is an operation
953commutative, does an operation load from memory. The various operation node
954types are described in the <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>
955file (values of the <tt>NodeType</tt> enum in the <tt>ISD</tt> namespace).
956</p>
957
958<p>
959TableGen uses the following target description (<tt>.td</tt>) input files to
960generate much of the code for instruction definition:
961</p>
962
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]963<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]964<li><tt>Target.td</tt> &mdash; Where the <tt>Instruction</tt>, <tt>Operand</tt>,
965 <tt>InstrInfo</tt>, and other fundamental classes are defined.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]966
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]967<li><tt>TargetSelectionDAG.td</tt>&mdash; Used by <tt>SelectionDAG</tt>
968 instruction selection generators, contains <tt>SDTC*</tt> classes (selection
969 DAG type constraint), definitions of <tt>SelectionDAG</tt> nodes (such as
970 <tt>imm</tt>, <tt>cond</tt>, <tt>bb</tt>, <tt>add</tt>, <tt>fadd</tt>,
971 <tt>sub</tt>), and pattern support (<tt>Pattern</tt>, <tt>Pat</tt>,
972 <tt>PatFrag</tt>, <tt>PatLeaf</tt>, <tt>ComplexPattern</tt>.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]973
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]974<li><tt>XXXInstrFormats.td</tt> &mdash; Patterns for definitions of
975 target-specific instructions.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]976
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]977<li><tt>XXXInstrInfo.td</tt> &mdash; Target-specific definitions of instruction
978 templates, condition codes, and instructions of an instruction set. For
979 architecture modifications, a different file name may be used. For example,
980 for Pentium with SSE instruction, this file is <tt>X86InstrSSE.td</tt>, and
981 for Pentium with MMX, this file is <tt>X86InstrMMX.td</tt>.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]982</ul>
983
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]984<p>
985There is also a target-specific <tt>XXX.td</tt> file, where <tt>XXX</tt> is the
986name of the target. The <tt>XXX.td</tt> file includes the other <tt>.td</tt>
987input files, but its contents are only directly important for subtargets.
988</p>
989
990<p>
991You should describe a concrete target-specific class <tt>XXXInstrInfo</tt> that
992represents machine instructions supported by a target machine.
993<tt>XXXInstrInfo</tt> contains an array of <tt>XXXInstrDescriptor</tt> objects,
994each of which describes one instruction. An instruction descriptor defines:</p>
995
996<ul>
997<li>Opcode mnemonic</li>
998
999<li>Number of operands</li>
1000
1001<li>List of implicit register definitions and uses</li>
1002
1003<li>Target-independent properties (such as memory access, is commutable)</li>
1004
1005<li>Target-specific flags </li>
1006</ul>
1007
1008<p>
1009The Instruction class (defined in <tt>Target.td</tt>) is mostly used as a base
1010for more complex instruction classes.
1011</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1012
1013<div class="doc_code">
1014<pre>class Instruction {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1015 string Namespace = "";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1016 dag OutOperandList; // An dag containing the MI def operand list.
1017 dag InOperandList; // An dag containing the MI use operand list.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1018 string AsmString = ""; // The .s format to print the instruction with.
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1019 list&lt;dag&gt; Pattern; // Set to the DAG pattern for this instruction
1020 list&lt;Register&gt; Uses = [];
1021 list&lt;Register&gt; Defs = [];
1022 list&lt;Predicate&gt; Predicates = []; // predicates turned into isel match code
1023 ... remainder not shown for space ...
1024}
1025</pre>
1026</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1027
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1028<p>
1029A <tt>SelectionDAG</tt> node (<tt>SDNode</tt>) should contain an object
1030representing a target-specific instruction that is defined
1031in <tt>XXXInstrInfo.td</tt>. The instruction objects should represent
1032instructions from the architecture manual of the target machine (such as the
1033SPARC Architecture Manual for the SPARC target).
1034</p>
1035
1036<p>
1037A single instruction from the architecture manual is often modeled as multiple
1038target instructions, depending upon its operands. For example, a manual might
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1039describe an add instruction that takes a register or an immediate operand. An
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1040LLVM target could model this with two instructions named <tt>ADDri</tt> and
1041<tt>ADDrr</tt>.
1042</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1043
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1044<p>
1045You should define a class for each instruction category and define each opcode
1046as a subclass of the category with appropriate parameters such as the fixed
1047binary encoding of opcodes and extended opcodes. You should map the register
1048bits to the bits of the instruction in which they are encoded (for the
1049JIT). Also you should specify how the instruction should be printed when the
1050automatic assembly printer is used.
1051</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1052
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1053<p>
1054As is described in the SPARC Architecture Manual, Version 8, there are three
1055major 32-bit formats for instructions. Format 1 is only for the <tt>CALL</tt>
1056instruction. Format 2 is for branch on condition codes and <tt>SETHI</tt> (set
1057high bits of a register) instructions. Format 3 is for other instructions.
1058</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1059
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1060<p>
1061Each of these formats has corresponding classes in <tt>SparcInstrFormat.td</tt>.
1062<tt>InstSP</tt> is a base class for other instruction classes. Additional base
1063classes are specified for more precise formats: for example
1064in <tt>SparcInstrFormat.td</tt>, <tt>F2_1</tt> is for <tt>SETHI</tt>,
1065and <tt>F2_2</tt> is for branches. There are three other base
1066classes: <tt>F3_1</tt> for register/register operations, <tt>F3_2</tt> for
1067register/immediate operations, and <tt>F3_3</tt> for floating-point
1068operations. <tt>SparcInstrInfo.td</tt> also adds the base class Pseudo for
1069synthetic SPARC instructions.
1070</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1071
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1072<p>
1073<tt>SparcInstrInfo.td</tt> largely consists of operand and instruction
1074definitions for the SPARC target. In <tt>SparcInstrInfo.td</tt>, the following
1075target description file entry, <tt>LDrr</tt>, defines the Load Integer
1076instruction for a Word (the <tt>LD</tt> SPARC opcode) from a memory address to a
1077register. The first parameter, the value 3 (<tt>11<sub>2</sub></tt>), is the
1078operation value for this category of operation. The second parameter
1079(<tt>000000<sub>2</sub></tt>) is the specific operation value
1080for <tt>LD</tt>/Load Word. The third parameter is the output destination, which
1081is a register operand and defined in the <tt>Register</tt> target description
1082file (<tt>IntRegs</tt>).
1083</p>
1084
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1085<div class="doc_code">
1086<pre>def LDrr : F3_1 &lt;3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1087 "ld [$addr], $dst",
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1088 [(set IntRegs:$dst, (load ADDRrr:$addr))]&gt;;
1089</pre>
1090</div>
1091
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1092<p>
1093The fourth parameter is the input source, which uses the address
1094operand <tt>MEMrr</tt> that is defined earlier in <tt>SparcInstrInfo.td</tt>:
1095</p>
1096
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1097<div class="doc_code">
1098<pre>def MEMrr : Operand&lt;i32&gt; {
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1099 let PrintMethod = "printMemOperand";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1100 let MIOperandInfo = (ops IntRegs, IntRegs);
1101}
1102</pre>
1103</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1104
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1105<p>
1106The fifth parameter is a string that is used by the assembly printer and can be
1107left as an empty string until the assembly printer interface is implemented. The
1108sixth and final parameter is the pattern used to match the instruction during
1109the SelectionDAG Select Phase described in
1110(<a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
1111Target-Independent Code Generator</a>). This parameter is detailed in the next
1112section, <a href="#InstructionSelector">Instruction Selector</a>.
1113</p>
1114
1115<p>
1116Instruction class definitions are not overloaded for different operand types, so
1117separate versions of instructions are needed for register, memory, or immediate
1118value operands. For example, to perform a Load Integer instruction for a Word
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1119from an immediate operand to a register, the following instruction class is
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1120defined:
1121</p>
1122
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1123<div class="doc_code">
1124<pre>def LDri : F3_2 &lt;3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1125 "ld [$addr], $dst",
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1126 [(set IntRegs:$dst, (load ADDRri:$addr))]&gt;;
1127</pre>
1128</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1129
1130<p>
1131Writing these definitions for so many similar instructions can involve a lot of
1132cut and paste. In td files, the <tt>multiclass</tt> directive enables the
1133creation of templates to define several instruction classes at once (using
1134the <tt>defm</tt> directive). For example in <tt>SparcInstrInfo.td</tt>, the
1135<tt>multiclass</tt> pattern <tt>F3_12</tt> is defined to create 2 instruction
1136classes each time <tt>F3_12</tt> is invoked:
1137</p>
1138
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1139<div class="doc_code">
1140<pre>multiclass F3_12 &lt;string OpcStr, bits&lt;6&gt; Op3Val, SDNode OpNode&gt; {
1141 def rr : F3_1 &lt;2, Op3Val,
1142 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1143 !strconcat(OpcStr, " $b, $c, $dst"),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1144 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]&gt;;
1145 def ri : F3_2 &lt;2, Op3Val,
1146 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1147 !strconcat(OpcStr, " $b, $c, $dst"),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1148 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]&gt;;
1149}
1150</pre>
1151</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1152
1153<p>
1154So when the <tt>defm</tt> directive is used for the <tt>XOR</tt>
1155and <tt>ADD</tt> instructions, as seen below, it creates four instruction
1156objects: <tt>XORrr</tt>, <tt>XORri</tt>, <tt>ADDrr</tt>, and <tt>ADDri</tt>.
1157</p>
1158
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1159<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1160<pre>
1161defm XOR : F3_12&lt;"xor", 0b000011, xor&gt;;
1162defm ADD : F3_12&lt;"add", 0b000000, add&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1163</pre>
1164</div>
1165
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1166<p>
1167<tt>SparcInstrInfo.td</tt> also includes definitions for condition codes that
1168are referenced by branch instructions. The following definitions
1169in <tt>SparcInstrInfo.td</tt> indicate the bit location of the SPARC condition
1170code. For example, the 10<sup>th</sup> bit represents the 'greater than'
1171condition for integers, and the 22<sup>nd</sup> bit represents the 'greater
1172than' condition for floats.
1173</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1174
1175<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1176<pre>
1177def ICC_NE : ICC_VAL&lt; 9&gt;; // Not Equal
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1178def ICC_E : ICC_VAL&lt; 1&gt;; // Equal
1179def ICC_G : ICC_VAL&lt;10&gt;; // Greater
1180...
1181def FCC_U : FCC_VAL&lt;23&gt;; // Unordered
1182def FCC_G : FCC_VAL&lt;22&gt;; // Greater
1183def FCC_UG : FCC_VAL&lt;21&gt;; // Unordered or Greater
1184...
1185</pre>
1186</div>
1187
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1188<p>
1189(Note that <tt>Sparc.h</tt> also defines enums that correspond to the same SPARC
1190condition codes. Care must be taken to ensure the values in <tt>Sparc.h</tt>
1191correspond to the values in <tt>SparcInstrInfo.td</tt>. I.e.,
1192<tt>SPCC::ICC_NE = 9</tt>, <tt>SPCC::FCC_U = 23</tt> and so on.)
1193</p>
1194
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1195</div>
1196
1197<!-- ======================================================================= -->
1198<div class="doc_subsection">
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1199 <a name="operandMapping">Instruction Operand Mapping</a>
1200</div>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1201
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1202<div class="doc_text">
1203
1204<p>
1205The code generator backend maps instruction operands to fields in the
1206instruction. Operands are assigned to unbound fields in the instruction in the
1207order they are defined. Fields are bound when they are assigned a value. For
1208example, the Sparc target defines the <tt>XNORrr</tt> instruction as
1209a <tt>F3_1</tt> format instruction having three operands.
1210</p>
1211
1212<div class="doc_code">
1213<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1214def XNORrr : F3_1&lt;2, 0b000111,
1215 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1216 "xnor $b, $c, $dst",
1217 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]&gt;;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1218</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1219</div>
1220
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1221<p>
1222The instruction templates in <tt>SparcInstrFormats.td</tt> show the base class
1223for <tt>F3_1</tt> is <tt>InstSP</tt>.
1224</p>
1225
1226<div class="doc_code">
1227<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1228class InstSP&lt;dag outs, dag ins, string asmstr, list&lt;dag&gt; pattern&gt; : Instruction {
1229 field bits&lt;32&gt; Inst;
1230 let Namespace = "SP";
1231 bits&lt;2&gt; op;
1232 let Inst{31-30} = op;
1233 dag OutOperandList = outs;
1234 dag InOperandList = ins;
1235 let AsmString = asmstr;
1236 let Pattern = pattern;
1237}
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1238</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1239</div>
1240
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1241<p><tt>InstSP</tt> leaves the <tt>op</tt> field unbound.</p>
1242
1243<div class="doc_code">
1244<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1245class F3&lt;dag outs, dag ins, string asmstr, list&lt;dag&gt; pattern&gt;
1246 : InstSP&lt;outs, ins, asmstr, pattern&gt; {
1247 bits&lt;5&gt; rd;
1248 bits&lt;6&gt; op3;
1249 bits&lt;5&gt; rs1;
1250 let op{1} = 1; // Op = 2 or 3
1251 let Inst{29-25} = rd;
1252 let Inst{24-19} = op3;
1253 let Inst{18-14} = rs1;
1254}
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1255</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1256</div>
1257
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1258<p>
1259<tt>F3</tt> binds the <tt>op</tt> field and defines the <tt>rd</tt>,
1260<tt>op3</tt>, and <tt>rs1</tt> fields. <tt>F3</tt> format instructions will
1261bind the operands <tt>rd</tt>, <tt>op3</tt>, and <tt>rs1</tt> fields.
1262</p>
1263
1264<div class="doc_code">
1265<pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1266class F3_1&lt;bits&lt;2&gt; opVal, bits&lt;6&gt; op3val, dag outs, dag ins,
1267 string asmstr, list&lt;dag&gt; pattern&gt; : F3&lt;outs, ins, asmstr, pattern&gt; {
1268 bits&lt;8&gt; asi = 0; // asi not currently used
1269 bits&lt;5&gt; rs2;
1270 let op = opVal;
1271 let op3 = op3val;
1272 let Inst{13} = 0; // i field = 0
1273 let Inst{12-5} = asi; // address space identifier
1274 let Inst{4-0} = rs2;
1275}
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1276</pre>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1277</div>
1278
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1279<p>
1280<tt>F3_1</tt> binds the <tt>op3</tt> field and defines the <tt>rs2</tt>
1281fields. <tt>F3_1</tt> format instructions will bind the operands to the <tt>rd</tt>,
1282<tt>rs1</tt>, and <tt>rs2</tt> fields. This results in the <tt>XNORrr</tt>
1283instruction binding <tt>$dst</tt>, <tt>$b</tt>, and <tt>$c</tt> operands to
1284the <tt>rd</tt>, <tt>rs1</tt>, and <tt>rs2</tt> fields respectively.
1285</p>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1286
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1287</div>
Chris Lattner7a152732008-11-22 19:10:48 +0000[diff] [blame]1288
1289<!-- ======================================================================= -->
1290<div class="doc_subsection">
Chris Lattner7d12b4b2008-11-11 19:36:31 +0000[diff] [blame]1291 <a name="implementInstr">Implement a subclass of </a>
1292 <a href="http://www.llvm.org/docs/CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1293</div>
1294
1295<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1296
1297<p>
1298The final step is to hand code portions of <tt>XXXInstrInfo</tt>, which
1299implements the interface described in <tt>TargetInstrInfo.h</tt>. These
1300functions return <tt>0</tt> or a Boolean or they assert, unless
1301overridden. Here's a list of functions that are overridden for the SPARC
1302implementation in <tt>SparcInstrInfo.cpp</tt>:
1303</p>
1304
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1305<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1306<li><tt>isMoveInstr</tt> &mdash; Return true if the instruction is a register to
1307 register move; false, otherwise.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1308
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1309<li><tt>isLoadFromStackSlot</tt> &mdash; If the specified machine instruction is
1310 a direct load from a stack slot, return the register number of the
1311 destination and the <tt>FrameIndex</tt> of the stack slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1312
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1313<li><tt>isStoreToStackSlot</tt> &mdash; If the specified machine instruction is
1314 a direct store to a stack slot, return the register number of the
1315 destination and the <tt>FrameIndex</tt> of the stack slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1316
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1317<li><tt>copyRegToReg</tt> &mdash; Copy values between a pair of registers.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1318
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1319<li><tt>storeRegToStackSlot</tt> &mdash; Store a register value to a stack
1320 slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1321
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1322<li><tt>loadRegFromStackSlot</tt> &mdash; Load a register value from a stack
1323 slot.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1324
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1325<li><tt>storeRegToAddr</tt> &mdash; Store a register value to memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1326
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1327<li><tt>loadRegFromAddr</tt> &mdash; Load a register value from memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1328
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1329<li><tt>foldMemoryOperand</tt> &mdash; Attempt to combine instructions of any
1330 load or store instruction for the specified operand(s).</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1331</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1332
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1333</div>
1334
1335<!-- ======================================================================= -->
1336<div class="doc_subsection">
1337 <a name="branchFolding">Branch Folding and If Conversion</a>
1338</div>
1339<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1340
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1341<p>
1342Performance can be improved by combining instructions or by eliminating
1343instructions that are never reached. The <tt>AnalyzeBranch</tt> method
1344in <tt>XXXInstrInfo</tt> may be implemented to examine conditional instructions
1345and remove unnecessary instructions. <tt>AnalyzeBranch</tt> looks at the end of
1346a machine basic block (MBB) for opportunities for improvement, such as branch
1347folding and if conversion. The <tt>BranchFolder</tt> and <tt>IfConverter</tt>
1348machine function passes (see the source files <tt>BranchFolding.cpp</tt> and
1349<tt>IfConversion.cpp</tt> in the <tt>lib/CodeGen</tt> directory) call
1350<tt>AnalyzeBranch</tt> to improve the control flow graph that represents the
1351instructions.
1352</p>
1353
1354<p>
1355Several implementations of <tt>AnalyzeBranch</tt> (for ARM, Alpha, and X86) can
1356be examined as models for your own <tt>AnalyzeBranch</tt> implementation. Since
1357SPARC does not implement a useful <tt>AnalyzeBranch</tt>, the ARM target
1358implementation is shown below.
1359</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1360
1361<p><tt>AnalyzeBranch</tt> returns a Boolean value and takes four parameters:</p>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1362
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1363<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1364<li><tt>MachineBasicBlock &amp;MBB</tt> &mdash; The incoming block to be
1365 examined.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1366
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1367<li><tt>MachineBasicBlock *&amp;TBB</tt> &mdash; A destination block that is
1368 returned. For a conditional branch that evaluates to true, <tt>TBB</tt> is
1369 the destination.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1370
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1371<li><tt>MachineBasicBlock *&amp;FBB</tt> &mdash; For a conditional branch that
1372 evaluates to false, <tt>FBB</tt> is returned as the destination.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1373
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1374<li><tt>std::vector&lt;MachineOperand&gt; &amp;Cond</tt> &mdash; List of
1375 operands to evaluate a condition for a conditional branch.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1376</ul>
1377
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1378<p>
1379In the simplest case, if a block ends without a branch, then it falls through to
1380the successor block. No destination blocks are specified for either <tt>TBB</tt>
1381or <tt>FBB</tt>, so both parameters return <tt>NULL</tt>. The start of
1382the <tt>AnalyzeBranch</tt> (see code below for the ARM target) shows the
1383function parameters and the code for the simplest case.
1384</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1385
1386<div class="doc_code">
1387<pre>bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &amp;MBB,
1388 MachineBasicBlock *&amp;TBB, MachineBasicBlock *&amp;FBB,
1389 std::vector&lt;MachineOperand&gt; &amp;Cond) const
1390{
1391 MachineBasicBlock::iterator I = MBB.end();
1392 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
1393 return false;
1394</pre>
1395</div>
1396
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1397<p>
1398If a block ends with a single unconditional branch instruction, then
1399<tt>AnalyzeBranch</tt> (shown below) should return the destination of that
1400branch in the <tt>TBB</tt> parameter.
1401</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1402
1403<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1404<pre>
1405 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
1406 TBB = LastInst-&gt;getOperand(0).getMBB();
1407 return false;
1408 }
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1409</pre>
1410</div>
1411
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1412<p>
1413If a block ends with two unconditional branches, then the second branch is never
1414reached. In that situation, as shown below, remove the last branch instruction
1415and return the penultimate branch in the <tt>TBB</tt> parameter.
1416</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1417
1418<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1419<pre>
1420 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &amp;&amp;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1421 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
1422 TBB = SecondLastInst-&gt;getOperand(0).getMBB();
1423 I = LastInst;
1424 I-&gt;eraseFromParent();
1425 return false;
1426 }
1427</pre>
1428</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1429
1430<p>
1431A block may end with a single conditional branch instruction that falls through
1432to successor block if the condition evaluates to false. In that case,
1433<tt>AnalyzeBranch</tt> (shown below) should return the destination of that
1434conditional branch in the <tt>TBB</tt> parameter and a list of operands in
1435the <tt>Cond</tt> parameter to evaluate the condition.
1436</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1437
1438<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1439<pre>
1440 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
1441 // Block ends with fall-through condbranch.
1442 TBB = LastInst-&gt;getOperand(0).getMBB();
1443 Cond.push_back(LastInst-&gt;getOperand(1));
1444 Cond.push_back(LastInst-&gt;getOperand(2));
1445 return false;
1446 }
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1447</pre>
1448</div>
1449
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1450<p>
1451If a block ends with both a conditional branch and an ensuing unconditional
1452branch, then <tt>AnalyzeBranch</tt> (shown below) should return the conditional
1453branch destination (assuming it corresponds to a conditional evaluation of
1454'<tt>true</tt>') in the <tt>TBB</tt> parameter and the unconditional branch
1455destination in the <tt>FBB</tt> (corresponding to a conditional evaluation of
1456'<tt>false</tt>'). A list of operands to evaluate the condition should be
1457returned in the <tt>Cond</tt> parameter.
1458</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1459
1460<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1461<pre>
1462 unsigned SecondLastOpc = SecondLastInst-&gt;getOpcode();
1463
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1464 if ((SecondLastOpc == ARM::Bcc &amp;&amp; LastOpc == ARM::B) ||
1465 (SecondLastOpc == ARM::tBcc &amp;&amp; LastOpc == ARM::tB)) {
1466 TBB = SecondLastInst-&gt;getOperand(0).getMBB();
1467 Cond.push_back(SecondLastInst-&gt;getOperand(1));
1468 Cond.push_back(SecondLastInst-&gt;getOperand(2));
1469 FBB = LastInst-&gt;getOperand(0).getMBB();
1470 return false;
1471 }
1472</pre>
1473</div>
1474
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1475<p>
1476For the last two cases (ending with a single conditional branch or ending with
1477one conditional and one unconditional branch), the operands returned in
1478the <tt>Cond</tt> parameter can be passed to methods of other instructions to
1479create new branches or perform other operations. An implementation
1480of <tt>AnalyzeBranch</tt> requires the helper methods <tt>RemoveBranch</tt>
1481and <tt>InsertBranch</tt> to manage subsequent operations.
1482</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1483
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1484<p>
1485<tt>AnalyzeBranch</tt> should return false indicating success in most circumstances.
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1486<tt>AnalyzeBranch</tt> should only return true when the method is stumped about what to
1487do, for example, if a block has three terminating branches. <tt>AnalyzeBranch</tt> may
1488return true if it encounters a terminator it cannot handle, such as an indirect
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1489branch.
1490</p>
1491
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1492</div>
1493
1494<!-- *********************************************************************** -->
1495<div class="doc_section">
1496 <a name="InstructionSelector">Instruction Selector</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]1497</div>
1498<!-- *********************************************************************** -->
1499
1500<div class="doc_text">
1501
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1502<p>
1503LLVM uses a <tt>SelectionDAG</tt> to represent LLVM IR instructions, and nodes
1504of the <tt>SelectionDAG</tt> ideally represent native target
1505instructions. During code generation, instruction selection passes are performed
1506to convert non-native DAG instructions into native target-specific
1507instructions. The pass described in <tt>XXXISelDAGToDAG.cpp</tt> is used to
1508match patterns and perform DAG-to-DAG instruction selection. Optionally, a pass
1509may be defined (in <tt>XXXBranchSelector.cpp</tt>) to perform similar DAG-to-DAG
1510operations for branch instructions. Later, the code in
1511<tt>XXXISelLowering.cpp</tt> replaces or removes operations and data types not
1512supported natively (legalizes) in a <tt>SelectionDAG</tt>.
1513</p>
1514
1515<p>
1516TableGen generates code for instruction selection using the following target
1517description input files:
1518</p>
1519
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]1520<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1521<li><tt>XXXInstrInfo.td</tt> &mdash; Contains definitions of instructions in a
1522 target-specific instruction set, generates <tt>XXXGenDAGISel.inc</tt>, which
1523 is included in <tt>XXXISelDAGToDAG.cpp</tt>.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1524
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1525<li><tt>XXXCallingConv.td</tt> &mdash; Contains the calling and return value
1526 conventions for the target architecture, and it generates
1527 <tt>XXXGenCallingConv.inc</tt>, which is included in
1528 <tt>XXXISelLowering.cpp</tt>.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]1529</ul>
1530
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1531<p>
1532The implementation of an instruction selection pass must include a header that
1533declares the <tt>FunctionPass</tt> class or a subclass of <tt>FunctionPass</tt>. In
1534<tt>XXXTargetMachine.cpp</tt>, a Pass Manager (PM) should add each instruction
1535selection pass into the queue of passes to run.
1536</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1537
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1538<p>
1539The LLVM static compiler (<tt>llc</tt>) is an excellent tool for visualizing the
1540contents of DAGs. To display the <tt>SelectionDAG</tt> before or after specific
1541processing phases, use the command line options for <tt>llc</tt>, described
1542at <a href="http://llvm.org/docs/CodeGenerator.html#selectiondag_process">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1543SelectionDAG Instruction Selection Process</a>.
1544</p>
1545
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1546<p>
1547To describe instruction selector behavior, you should add patterns for lowering
1548LLVM code into a <tt>SelectionDAG</tt> as the last parameter of the instruction
1549definitions in <tt>XXXInstrInfo.td</tt>. For example, in
1550<tt>SparcInstrInfo.td</tt>, this entry defines a register store operation, and
1551the last parameter describes a pattern with the store DAG operator.
1552</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1553
1554<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1555<pre>
1556def STrr : F3_1&lt; 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
1557 "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1558</pre>
1559</div>
1560
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1561<p>
1562<tt>ADDRrr</tt> is a memory mode that is also defined in
1563<tt>SparcInstrInfo.td</tt>:
1564</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1565
1566<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1567<pre>
1568def ADDRrr : ComplexPattern&lt;i32, 2, "SelectADDRrr", [], []&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1569</pre>
1570</div>
1571
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1572<p>
1573The definition of <tt>ADDRrr</tt> refers to <tt>SelectADDRrr</tt>, which is a
1574function defined in an implementation of the Instructor Selector (such
1575as <tt>SparcISelDAGToDAG.cpp</tt>).
1576</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1577
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1578<p>
1579In <tt>lib/Target/TargetSelectionDAG.td</tt>, the DAG operator for store is
1580defined below:
1581</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1582
1583<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1584<pre>
1585def store : PatFrag&lt;(ops node:$val, node:$ptr),
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1586 (st node:$val, node:$ptr), [{
1587 if (StoreSDNode *ST = dyn_cast&lt;StoreSDNode&gt;(N))
1588 return !ST-&gt;isTruncatingStore() &amp;&amp;
1589 ST-&gt;getAddressingMode() == ISD::UNINDEXED;
1590 return false;
1591}]&gt;;
1592</pre>
1593</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1594
1595<p>
1596<tt>XXXInstrInfo.td</tt> also generates (in <tt>XXXGenDAGISel.inc</tt>) the
1597<tt>SelectCode</tt> method that is used to call the appropriate processing
1598method for an instruction. In this example, <tt>SelectCode</tt>
1599calls <tt>Select_ISD_STORE</tt> for the <tt>ISD::STORE</tt> opcode.
1600</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1601
1602<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1603<pre>
1604SDNode *SelectCode(SDValue N) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1605 ...
Dan Gohman50ef90d2009-01-28 21:36:46 +0000[diff] [blame]1606 MVT::ValueType NVT = N.getNode()-&gt;getValueType(0);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1607 switch (N.getOpcode()) {
1608 case ISD::STORE: {
1609 switch (NVT) {
1610 default:
1611 return Select_ISD_STORE(N);
1612 break;
1613 }
1614 break;
1615 }
1616 ...
1617</pre>
1618</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1619
1620<p>
1621The pattern for <tt>STrr</tt> is matched, so elsewhere in
1622<tt>XXXGenDAGISel.inc</tt>, code for <tt>STrr</tt> is created for
1623<tt>Select_ISD_STORE</tt>. The <tt>Emit_22</tt> method is also generated
1624in <tt>XXXGenDAGISel.inc</tt> to complete the processing of this
1625instruction.
1626</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1627
1628<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1629<pre>
1630SDNode *Select_ISD_STORE(const SDValue &amp;N) {
Dan Gohman50ef90d2009-01-28 21:36:46 +0000[diff] [blame]1631 SDValue Chain = N.getOperand(0);
1632 if (Predicate_store(N.getNode())) {
1633 SDValue N1 = N.getOperand(1);
1634 SDValue N2 = N.getOperand(2);
1635 SDValue CPTmp0;
1636 SDValue CPTmp1;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1637
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1638 // Pattern: (st:void IntRegs:i32:$src,
1639 // ADDRrr:i32:$addr)&lt;&lt;P:Predicate_store&gt;&gt;
1640 // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
1641 // Pattern complexity = 13 cost = 1 size = 0
1642 if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &amp;&amp;
Dan Gohman50ef90d2009-01-28 21:36:46 +0000[diff] [blame]1643 N1.getNode()-&gt;getValueType(0) == MVT::i32 &amp;&amp;
1644 N2.getNode()-&gt;getValueType(0) == MVT::i32) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1645 return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
1646 }
1647...
1648</pre>
1649</div>
1650
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1651</div>
1652
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1653<!-- ======================================================================= -->
1654<div class="doc_subsection">
1655 <a name="LegalizePhase">The SelectionDAG Legalize Phase</a>
1656</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1657
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1658<div class="doc_text">
1659
1660<p>
1661The Legalize phase converts a DAG to use types and operations that are natively
1662supported by the target. For natively unsupported types and operations, you need
1663to add code to the target-specific XXXTargetLowering implementation to convert
1664unsupported types and operations to supported ones.
1665</p>
1666
1667<p>
1668In the constructor for the <tt>XXXTargetLowering</tt> class, first use the
1669<tt>addRegisterClass</tt> method to specify which types are supports and which
1670register classes are associated with them. The code for the register classes are
1671generated by TableGen from <tt>XXXRegisterInfo.td</tt> and placed
1672in <tt>XXXGenRegisterInfo.h.inc</tt>. For example, the implementation of the
1673constructor for the SparcTargetLowering class (in
1674<tt>SparcISelLowering.cpp</tt>) starts with the following code:
1675</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1676
1677<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1678<pre>
1679addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1680addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
1681addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
1682</pre>
1683</div>
1684
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1685<p>
1686You should examine the node types in the <tt>ISD</tt> namespace
1687(<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>) and determine which
1688operations the target natively supports. For operations that do <b>not</b> have
1689native support, add a callback to the constructor for the XXXTargetLowering
1690class, so the instruction selection process knows what to do. The TargetLowering
1691class callback methods (declared in <tt>llvm/Target/TargetLowering.h</tt>) are:
1692</p>
1693
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1694<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1695<li><tt>setOperationAction</tt> &mdash; General operation.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1696
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1697<li><tt>setLoadExtAction</tt> &mdash; Load with extension.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1698
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1699<li><tt>setTruncStoreAction</tt> &mdash; Truncating store.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1700
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1701<li><tt>setIndexedLoadAction</tt> &mdash; Indexed load.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1702
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1703<li><tt>setIndexedStoreAction</tt> &mdash; Indexed store.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1704
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1705<li><tt>setConvertAction</tt> &mdash; Type conversion.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1706
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1707<li><tt>setCondCodeAction</tt> &mdash; Support for a given condition code.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1708</ul>
1709
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1710<p>
1711Note: on older releases, <tt>setLoadXAction</tt> is used instead
1712of <tt>setLoadExtAction</tt>. Also, on older releases,
1713<tt>setCondCodeAction</tt> may not be supported. Examine your release
1714to see what methods are specifically supported.
1715</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1716
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1717<p>
1718These callbacks are used to determine that an operation does or does not work
1719with a specified type (or types). And in all cases, the third parameter is
1720a <tt>LegalAction</tt> type enum value: <tt>Promote</tt>, <tt>Expand</tt>,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1721<tt>Custom</tt>, or <tt>Legal</tt>. <tt>SparcISelLowering.cpp</tt>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1722contains examples of all four <tt>LegalAction</tt> values.
1723</p>
1724
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1725</div>
1726
1727<!-- _______________________________________________________________________ -->
1728<div class="doc_subsubsection">
1729 <a name="promote">Promote</a>
1730</div>
1731
1732<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1733
1734<p>
1735For an operation without native support for a given type, the specified type may
1736be promoted to a larger type that is supported. For example, SPARC does not
1737support a sign-extending load for Boolean values (<tt>i1</tt> type), so
1738in <tt>SparcISelLowering.cpp</tt> the third parameter below, <tt>Promote</tt>,
1739changes <tt>i1</tt> type values to a large type before loading.
1740</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1741
1742<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1743<pre>
1744setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1745</pre>
1746</div>
1747
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1748</div>
1749
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1750<!-- _______________________________________________________________________ -->
1751<div class="doc_subsubsection">
1752 <a name="expand">Expand</a>
1753</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1754
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1755<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1756
1757<p>
1758For a type without native support, a value may need to be broken down further,
1759rather than promoted. For an operation without native support, a combination of
1760other operations may be used to similar effect. In SPARC, the floating-point
1761sine and cosine trig operations are supported by expansion to other operations,
1762as indicated by the third parameter, <tt>Expand</tt>, to
1763<tt>setOperationAction</tt>:
1764</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1765
1766<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1767<pre>
1768setOperationAction(ISD::FSIN, MVT::f32, Expand);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1769setOperationAction(ISD::FCOS, MVT::f32, Expand);
1770</pre>
1771</div>
1772
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1773</div>
1774
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1775<!-- _______________________________________________________________________ -->
1776<div class="doc_subsubsection">
1777 <a name="custom">Custom</a>
1778</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1779
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1780<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1781
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1782<p>
1783For some operations, simple type promotion or operation expansion may be
1784insufficient. In some cases, a special intrinsic function must be implemented.
1785</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1786
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1787<p>
1788For example, a constant value may require special treatment, or an operation may
1789require spilling and restoring registers in the stack and working with register
1790allocators.
1791</p>
1792
1793<p>
1794As seen in <tt>SparcISelLowering.cpp</tt> code below, to perform a type
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1795conversion from a floating point value to a signed integer, first the
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1796<tt>setOperationAction</tt> should be called with <tt>Custom</tt> as the third
1797parameter:
1798</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1799
1800<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1801<pre>
1802setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1803</pre>
1804</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1805
1806<p>
1807In the <tt>LowerOperation</tt> method, for each <tt>Custom</tt> operation, a
1808case statement should be added to indicate what function to call. In the
1809following code, an <tt>FP_TO_SINT</tt> opcode will call
1810the <tt>LowerFP_TO_SINT</tt> method:
1811</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1812
1813<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1814<pre>
1815SDValue SparcTargetLowering::LowerOperation(SDValue Op, SelectionDAG &amp;DAG) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1816 switch (Op.getOpcode()) {
1817 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1818 ...
1819 }
1820}
1821</pre>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1822</div>
1823
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1824<p>
1825Finally, the <tt>LowerFP_TO_SINT</tt> method is implemented, using an FP
1826register to convert the floating-point value to an integer.
1827</p>
1828
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1829<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1830<pre>
1831static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &amp;DAG) {
1832 assert(Op.getValueType() == MVT::i32);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1833 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
1834 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1835}
1836</pre>
1837</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1838
1839</div>
1840
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1841<!-- _______________________________________________________________________ -->
1842<div class="doc_subsubsection">
1843 <a name="legal">Legal</a>
1844</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1845
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1846<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1847
1848<p>
1849The <tt>Legal</tt> LegalizeAction enum value simply indicates that an
1850operation <b>is</b> natively supported. <tt>Legal</tt> represents the default
1851condition, so it is rarely used. In <tt>SparcISelLowering.cpp</tt>, the action
1852for <tt>CTPOP</tt> (an operation to count the bits set in an integer) is
1853natively supported only for SPARC v9. The following code enables
1854the <tt>Expand</tt> conversion technique for non-v9 SPARC implementations.
1855</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1856
1857<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1858<pre>
1859setOperationAction(ISD::CTPOP, MVT::i32, Expand);
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1860...
1861if (TM.getSubtarget&lt;SparcSubtarget&gt;().isV9())
1862 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1863 case ISD::SETULT: return SPCC::ICC_CS;
1864 case ISD::SETULE: return SPCC::ICC_LEU;
1865 case ISD::SETUGT: return SPCC::ICC_GU;
1866 case ISD::SETUGE: return SPCC::ICC_CC;
1867 }
1868}
1869</pre>
1870</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1871
1872</div>
1873
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1874<!-- ======================================================================= -->
1875<div class="doc_subsection">
1876 <a name="callingConventions">Calling Conventions</a>
1877</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1878
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1879<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1880
1881<p>
1882To support target-specific calling conventions, <tt>XXXGenCallingConv.td</tt>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1883uses interfaces (such as CCIfType and CCAssignToReg) that are defined in
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1884<tt>lib/Target/TargetCallingConv.td</tt>. TableGen can take the target
1885descriptor file <tt>XXXGenCallingConv.td</tt> and generate the header
1886file <tt>XXXGenCallingConv.inc</tt>, which is typically included
1887in <tt>XXXISelLowering.cpp</tt>. You can use the interfaces in
1888<tt>TargetCallingConv.td</tt> to specify:
1889</p>
1890
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1891<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1892<li>The order of parameter allocation.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1893
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1894<li>Where parameters and return values are placed (that is, on the stack or in
1895 registers).</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1896
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1897<li>Which registers may be used.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1898
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1899<li>Whether the caller or callee unwinds the stack.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1900</ul>
1901
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1902<p>
1903The following example demonstrates the use of the <tt>CCIfType</tt> and
1904<tt>CCAssignToReg</tt> interfaces. If the <tt>CCIfType</tt> predicate is true
1905(that is, if the current argument is of type <tt>f32</tt> or <tt>f64</tt>), then
1906the action is performed. In this case, the <tt>CCAssignToReg</tt> action assigns
1907the argument value to the first available register: either <tt>R0</tt>
1908or <tt>R1</tt>.
1909</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1910
1911<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1912<pre>
1913CCIfType&lt;[f32,f64], CCAssignToReg&lt;[R0, R1]&gt;&gt;
1914</pre>
1915</div>
1916
1917<p>
1918<tt>SparcCallingConv.td</tt> contains definitions for a target-specific
1919return-value calling convention (RetCC_Sparc32) and a basic 32-bit C calling
1920convention (<tt>CC_Sparc32</tt>). The definition of <tt>RetCC_Sparc32</tt>
1921(shown below) indicates which registers are used for specified scalar return
1922types. A single-precision float is returned to register <tt>F0</tt>, and a
1923double-precision float goes to register <tt>D0</tt>. A 32-bit integer is
1924returned in register <tt>I0</tt> or <tt>I1</tt>.
1925</p>
1926
1927<div class="doc_code">
1928<pre>
1929def RetCC_Sparc32 : CallingConv&lt;[
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1930 CCIfType&lt;[i32], CCAssignToReg&lt;[I0, I1]&gt;&gt;,
1931 CCIfType&lt;[f32], CCAssignToReg&lt;[F0]&gt;&gt;,
1932 CCIfType&lt;[f64], CCAssignToReg&lt;[D0]&gt;&gt;
1933]&gt;;
1934</pre>
1935</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1936
1937<p>
1938The definition of <tt>CC_Sparc32</tt> in <tt>SparcCallingConv.td</tt> introduces
1939<tt>CCAssignToStack</tt>, which assigns the value to a stack slot with the
1940specified size and alignment. In the example below, the first parameter, 4,
1941indicates the size of the slot, and the second parameter, also 4, indicates the
1942stack alignment along 4-byte units. (Special cases: if size is zero, then the
1943ABI size is used; if alignment is zero, then the ABI alignment is used.)
1944</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1945
1946<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1947<pre>
1948def CC_Sparc32 : CallingConv&lt;[
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1949 // All arguments get passed in integer registers if there is space.
1950 CCIfType&lt;[i32, f32, f64], CCAssignToReg&lt;[I0, I1, I2, I3, I4, I5]&gt;&gt;,
1951 CCAssignToStack&lt;4, 4&gt;
1952]&gt;;
1953</pre>
1954</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1955
1956<p>
1957<tt>CCDelegateTo</tt> is another commonly used interface, which tries to find a
1958specified sub-calling convention, and, if a match is found, it is invoked. In
1959the following example (in <tt>X86CallingConv.td</tt>), the definition of
1960<tt>RetCC_X86_32_C</tt> ends with <tt>CCDelegateTo</tt>. After the current value
1961is assigned to the register <tt>ST0</tt> or <tt>ST1</tt>,
1962the <tt>RetCC_X86Common</tt> is invoked.
1963</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1964
1965<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1966<pre>
1967def RetCC_X86_32_C : CallingConv&lt;[
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1968 CCIfType&lt;[f32], CCAssignToReg&lt;[ST0, ST1]&gt;&gt;,
1969 CCIfType&lt;[f64], CCAssignToReg&lt;[ST0, ST1]&gt;&gt;,
1970 CCDelegateTo&lt;RetCC_X86Common&gt;
1971]&gt;;
1972</pre>
1973</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1974
1975<p>
1976<tt>CCIfCC</tt> is an interface that attempts to match the given name to the
1977current calling convention. If the name identifies the current calling
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1978convention, then a specified action is invoked. In the following example (in
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1979<tt>X86CallingConv.td</tt>), if the <tt>Fast</tt> calling convention is in use,
1980then <tt>RetCC_X86_32_Fast</tt> is invoked. If the <tt>SSECall</tt> calling
1981convention is in use, then <tt>RetCC_X86_32_SSE</tt> is invoked.
1982</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1983
1984<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1985<pre>
1986def RetCC_X86_32 : CallingConv&lt;[
1987 CCIfCC&lt;"CallingConv::Fast", CCDelegateTo&lt;RetCC_X86_32_Fast&gt;&gt;,
1988 CCIfCC&lt;"CallingConv::X86_SSECall", CCDelegateTo&lt;RetCC_X86_32_SSE&gt;&gt;,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1989 CCDelegateTo&lt;RetCC_X86_32_C&gt;
1990]&gt;;
1991</pre>
1992</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1993
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1994<p>Other calling convention interfaces include:</p>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1995
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1996<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]1997<li><tt>CCIf &lt;predicate, action&gt;</tt> &mdash; If the predicate matches,
1998 apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]1999
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2000<li><tt>CCIfInReg &lt;action&gt;</tt> &mdash; If the argument is marked with the
2001 '<tt>inreg</tt>' attribute, then apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2002
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2003<li><tt>CCIfNest &lt;action&gt;</tt> &mdash; Inf the argument is marked with the
2004 '<tt>nest</tt>' attribute, then apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2005
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2006<li><tt>CCIfNotVarArg &lt;action&gt;</tt> &mdash; If the current function does
2007 not take a variable number of arguments, apply the action.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2008
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2009<li><tt>CCAssignToRegWithShadow &lt;registerList, shadowList&gt;</tt> &mdash;
2010 similar to <tt>CCAssignToReg</tt>, but with a shadow list of registers.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2011
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2012<li><tt>CCPassByVal &lt;size, align&gt;</tt> &mdash; Assign value to a stack
2013 slot with the minimum specified size and alignment.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2014
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2015<li><tt>CCPromoteToType &lt;type&gt;</tt> &mdash; Promote the current value to
2016 the specified type.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2017
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2018<li><tt>CallingConv &lt;[actions]&gt;</tt> &mdash; Define each calling
2019 convention that is supported.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2020</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2021
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2022</div>
2023
2024<!-- *********************************************************************** -->
2025<div class="doc_section">
2026 <a name="assemblyPrinter">Assembly Printer</a>
2027</div>
2028<!-- *********************************************************************** -->
2029
2030<div class="doc_text">
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2031
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2032<p>
2033During the code emission stage, the code generator may utilize an LLVM pass to
2034produce assembly output. To do this, you want to implement the code for a
2035printer that converts LLVM IR to a GAS-format assembly language for your target
2036machine, using the following steps:
2037</p>
2038
2039<ul>
2040<li>Define all the assembly strings for your target, adding them to the
2041 instructions defined in the <tt>XXXInstrInfo.td</tt> file.
2042 (See <a href="#InstructionSet">Instruction Set</a>.) TableGen will produce
2043 an output file (<tt>XXXGenAsmWriter.inc</tt>) with an implementation of
2044 the <tt>printInstruction</tt> method for the XXXAsmPrinter class.</li>
2045
2046<li>Write <tt>XXXTargetAsmInfo.h</tt>, which contains the bare-bones declaration
2047 of the <tt>XXXTargetAsmInfo</tt> class (a subclass
2048 of <tt>TargetAsmInfo</tt>).</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2049
2050<li>Write <tt>XXXTargetAsmInfo.cpp</tt>, which contains target-specific values
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2051 for <tt>TargetAsmInfo</tt> properties and sometimes new implementations for
2052 methods.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2053
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2054<li>Write <tt>XXXAsmPrinter.cpp</tt>, which implements the <tt>AsmPrinter</tt>
2055 class that performs the LLVM-to-assembly conversion.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2056</ul>
2057
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2058<p>
2059The code in <tt>XXXTargetAsmInfo.h</tt> is usually a trivial declaration of the
2060<tt>XXXTargetAsmInfo</tt> class for use in <tt>XXXTargetAsmInfo.cpp</tt>.
2061Similarly, <tt>XXXTargetAsmInfo.cpp</tt> usually has a few declarations of
2062<tt>XXXTargetAsmInfo</tt> replacement values that override the default values
2063in <tt>TargetAsmInfo.cpp</tt>. For example in <tt>SparcTargetAsmInfo.cpp</tt>:
2064</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2065
2066<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2067<pre>
2068SparcTargetAsmInfo::SparcTargetAsmInfo(const SparcTargetMachine &amp;TM) {
2069 Data16bitsDirective = "\t.half\t";
2070 Data32bitsDirective = "\t.word\t";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2071 Data64bitsDirective = 0; // .xword is only supported by V9.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2072 ZeroDirective = "\t.skip\t";
2073 CommentString = "!";
2074 ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2075}
2076</pre>
2077</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2078
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2079<p>
2080The X86 assembly printer implementation (<tt>X86TargetAsmInfo</tt>) is an
Chris Lattnerb6d66742009-08-02 04:02:52 +0000[diff] [blame]2081example where the target specific <tt>TargetAsmInfo</tt> class uses an
2082overridden methods: <tt>ExpandInlineAsm</tt>.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2083</p>
2084
2085<p>
2086A target-specific implementation of AsmPrinter is written in
2087<tt>XXXAsmPrinter.cpp</tt>, which implements the <tt>AsmPrinter</tt> class that
2088converts the LLVM to printable assembly. The implementation must include the
2089following headers that have declarations for the <tt>AsmPrinter</tt> and
2090<tt>MachineFunctionPass</tt> classes. The <tt>MachineFunctionPass</tt> is a
2091subclass of <tt>FunctionPass</tt>.
2092</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2093
2094<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2095<pre>
2096#include "llvm/CodeGen/AsmPrinter.h"
2097#include "llvm/CodeGen/MachineFunctionPass.h"
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2098</pre>
2099</div>
2100
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2101<p>
2102As a <tt>FunctionPass</tt>, <tt>AsmPrinter</tt> first
2103calls <tt>doInitialization</tt> to set up the <tt>AsmPrinter</tt>. In
2104<tt>SparcAsmPrinter</tt>, a <tt>Mangler</tt> object is instantiated to process
2105variable names.
2106</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2107
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2108<p>
2109In <tt>XXXAsmPrinter.cpp</tt>, the <tt>runOnMachineFunction</tt> method
2110(declared in <tt>MachineFunctionPass</tt>) must be implemented
2111for <tt>XXXAsmPrinter</tt>. In <tt>MachineFunctionPass</tt>,
2112the <tt>runOnFunction</tt> method invokes <tt>runOnMachineFunction</tt>.
2113Target-specific implementations of <tt>runOnMachineFunction</tt> differ, but
2114generally do the following to process each machine function:
2115</p>
2116
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2117<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2118<li>Call <tt>SetupMachineFunction</tt> to perform initialization.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2119
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2120<li>Call <tt>EmitConstantPool</tt> to print out (to the output stream) constants
2121 which have been spilled to memory.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2122
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2123<li>Call <tt>EmitJumpTableInfo</tt> to print out jump tables used by the current
2124 function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2125
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2126<li>Print out the label for the current function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2127
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2128<li>Print out the code for the function, including basic block labels and the
2129 assembly for the instruction (using <tt>printInstruction</tt>)</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2130</ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2131
2132<p>
2133The <tt>XXXAsmPrinter</tt> implementation must also include the code generated
2134by TableGen that is output in the <tt>XXXGenAsmWriter.inc</tt> file. The code
2135in <tt>XXXGenAsmWriter.inc</tt> contains an implementation of the
2136<tt>printInstruction</tt> method that may call these methods:
2137</p>
2138
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2139<ul>
2140<li><tt>printOperand</tt></li>
2141
2142<li><tt>printMemOperand</tt></li>
2143
2144<li><tt>printCCOperand (for conditional statements)</tt></li>
2145
2146<li><tt>printDataDirective</tt></li>
2147
2148<li><tt>printDeclare</tt></li>
2149
2150<li><tt>printImplicitDef</tt></li>
2151
2152<li><tt>printInlineAsm</tt></li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2153</ul>
2154
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2155<p>
2156The implementations of <tt>printDeclare</tt>, <tt>printImplicitDef</tt>,
2157<tt>printInlineAsm</tt>, and <tt>printLabel</tt> in <tt>AsmPrinter.cpp</tt> are
2158generally adequate for printing assembly and do not need to be
Chris Lattnerdeb8c152009-09-12 22:57:37 +0000[diff] [blame]2159overridden.
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2160</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2161
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2162<p>
2163The <tt>printOperand</tt> method is implemented with a long switch/case
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2164statement for the type of operand: register, immediate, basic block, external
2165symbol, global address, constant pool index, or jump table index. For an
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2166instruction with a memory address operand, the <tt>printMemOperand</tt> method
2167should be implemented to generate the proper output. Similarly,
2168<tt>printCCOperand</tt> should be used to print a conditional operand.
2169</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2170
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2171<p><tt>doFinalization</tt> should be overridden in <tt>XXXAsmPrinter</tt>, and
2172it should be called to shut down the assembly printer. During
2173<tt>doFinalization</tt>, global variables and constants are printed to
2174output.
2175</p>
2176
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2177</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2178
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2179<!-- *********************************************************************** -->
2180<div class="doc_section">
2181 <a name="subtargetSupport">Subtarget Support</a>
2182</div>
2183<!-- *********************************************************************** -->
2184
2185<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2186
2187<p>
2188Subtarget support is used to inform the code generation process of instruction
2189set variations for a given chip set. For example, the LLVM SPARC implementation
2190provided covers three major versions of the SPARC microprocessor architecture:
2191Version 8 (V8, which is a 32-bit architecture), Version 9 (V9, a 64-bit
2192architecture), and the UltraSPARC architecture. V8 has 16 double-precision
2193floating-point registers that are also usable as either 32 single-precision or 8
2194quad-precision registers. V8 is also purely big-endian. V9 has 32
2195double-precision floating-point registers that are also usable as 16
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2196quad-precision registers, but cannot be used as single-precision registers. The
2197UltraSPARC architecture combines V9 with UltraSPARC Visual Instruction Set
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2198extensions.
2199</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2200
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2201<p>
2202If subtarget support is needed, you should implement a target-specific
2203XXXSubtarget class for your architecture. This class should process the
2204command-line options <tt>-mcpu=</tt> and <tt>-mattr=</tt>.
2205</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2206
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2207<p>
2208TableGen uses definitions in the <tt>Target.td</tt> and <tt>Sparc.td</tt> files
2209to generate code in <tt>SparcGenSubtarget.inc</tt>. In <tt>Target.td</tt>, shown
2210below, the <tt>SubtargetFeature</tt> interface is defined. The first 4 string
2211parameters of the <tt>SubtargetFeature</tt> interface are a feature name, an
2212attribute set by the feature, the value of the attribute, and a description of
2213the feature. (The fifth parameter is a list of features whose presence is
2214implied, and its default value is an empty array.)
2215</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2216
2217<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2218<pre>
2219class SubtargetFeature&lt;string n, string a, string v, string d,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2220 list&lt;SubtargetFeature&gt; i = []&gt; {
2221 string Name = n;
2222 string Attribute = a;
2223 string Value = v;
2224 string Desc = d;
2225 list&lt;SubtargetFeature&gt; Implies = i;
2226}
2227</pre>
2228</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2229
2230<p>
2231In the <tt>Sparc.td</tt> file, the SubtargetFeature is used to define the
2232following features.
2233</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2234
2235<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2236<pre>
2237def FeatureV9 : SubtargetFeature&lt;"v9", "IsV9", "true",
2238 "Enable SPARC-V9 instructions"&gt;;
2239def FeatureV8Deprecated : SubtargetFeature&lt;"deprecated-v8",
2240 "V8DeprecatedInsts", "true",
2241 "Enable deprecated V8 instructions in V9 mode"&gt;;
2242def FeatureVIS : SubtargetFeature&lt;"vis", "IsVIS", "true",
2243 "Enable UltraSPARC Visual Instruction Set extensions"&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2244</pre>
2245</div>
2246
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2247<p>
2248Elsewhere in <tt>Sparc.td</tt>, the Proc class is defined and then is used to
2249define particular SPARC processor subtypes that may have the previously
2250described features.
2251</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2252
2253<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2254<pre>
2255class Proc&lt;string Name, list&lt;SubtargetFeature&gt; Features&gt;
2256 : Processor&lt;Name, NoItineraries, Features&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2257&nbsp;
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2258def : Proc&lt;"generic", []&gt;;
2259def : Proc&lt;"v8", []&gt;;
2260def : Proc&lt;"supersparc", []&gt;;
2261def : Proc&lt;"sparclite", []&gt;;
2262def : Proc&lt;"f934", []&gt;;
2263def : Proc&lt;"hypersparc", []&gt;;
2264def : Proc&lt;"sparclite86x", []&gt;;
2265def : Proc&lt;"sparclet", []&gt;;
2266def : Proc&lt;"tsc701", []&gt;;
2267def : Proc&lt;"v9", [FeatureV9]&gt;;
2268def : Proc&lt;"ultrasparc", [FeatureV9, FeatureV8Deprecated]&gt;;
2269def : Proc&lt;"ultrasparc3", [FeatureV9, FeatureV8Deprecated]&gt;;
2270def : Proc&lt;"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]&gt;;
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2271</pre>
2272</div>
2273
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2274<p>
2275From <tt>Target.td</tt> and <tt>Sparc.td</tt> files, the resulting
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2276SparcGenSubtarget.inc specifies enum values to identify the features, arrays of
2277constants to represent the CPU features and CPU subtypes, and the
2278ParseSubtargetFeatures method that parses the features string that sets
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2279specified subtarget options. The generated <tt>SparcGenSubtarget.inc</tt> file
2280should be included in the <tt>SparcSubtarget.cpp</tt>. The target-specific
2281implementation of the XXXSubtarget method should follow this pseudocode:
2282</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2283
2284<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2285<pre>
2286XXXSubtarget::XXXSubtarget(const Module &amp;M, const std::string &amp;FS) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2287 // Set the default features
2288 // Determine default and user specified characteristics of the CPU
2289 // Call ParseSubtargetFeatures(FS, CPU) to parse the features string
2290 // Perform any additional operations
2291}
2292</pre>
2293</div>
2294
Bill Wendlinge9e6fd92009-04-05 00:43:04 +0000[diff] [blame]2295</div>
2296
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2297<!-- *********************************************************************** -->
2298<div class="doc_section">
2299 <a name="jitSupport">JIT Support</a>
2300</div>
2301<!-- *********************************************************************** -->
2302
2303<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2304
2305<p>
2306The implementation of a target machine optionally includes a Just-In-Time (JIT)
2307code generator that emits machine code and auxiliary structures as binary output
2308that can be written directly to memory. To do this, implement JIT code
2309generation by performing the following steps:
2310</p>
2311
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2312<ul>
2313<li>Write an <tt>XXXCodeEmitter.cpp</tt> file that contains a machine function
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2314 pass that transforms target-machine instructions into relocatable machine
2315 code.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2316
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2317<li>Write an <tt>XXXJITInfo.cpp</tt> file that implements the JIT interfaces for
2318 target-specific code-generation activities, such as emitting machine code
2319 and stubs.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2320
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2321<li>Modify <tt>XXXTargetMachine</tt> so that it provides a
2322 <tt>TargetJITInfo</tt> object through its <tt>getJITInfo</tt> method.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2323</ul>
2324
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2325<p>
2326There are several different approaches to writing the JIT support code. For
2327instance, TableGen and target descriptor files may be used for creating a JIT
2328code generator, but are not mandatory. For the Alpha and PowerPC target
2329machines, TableGen is used to generate <tt>XXXGenCodeEmitter.inc</tt>, which
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2330contains the binary coding of machine instructions and the
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2331<tt>getBinaryCodeForInstr</tt> method to access those codes. Other JIT
2332implementations do not.
2333</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2334
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2335<p>
2336Both <tt>XXXJITInfo.cpp</tt> and <tt>XXXCodeEmitter.cpp</tt> must include the
2337<tt>llvm/CodeGen/MachineCodeEmitter.h</tt> header file that defines the
2338<tt>MachineCodeEmitter</tt> class containing code for several callback functions
2339that write data (in bytes, words, strings, etc.) to the output stream.
2340</p>
2341
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2342</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2343
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2344<!-- ======================================================================= -->
2345<div class="doc_subsection">
2346 <a name="mce">Machine Code Emitter</a>
2347</div>
2348
2349<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2350
2351<p>
2352In <tt>XXXCodeEmitter.cpp</tt>, a target-specific of the <tt>Emitter</tt> class
2353is implemented as a function pass (subclass
2354of <tt>MachineFunctionPass</tt>). The target-specific implementation
2355of <tt>runOnMachineFunction</tt> (invoked by
2356<tt>runOnFunction</tt> in <tt>MachineFunctionPass</tt>) iterates through the
2357<tt>MachineBasicBlock</tt> calls <tt>emitInstruction</tt> to process each
2358instruction and emit binary code. <tt>emitInstruction</tt> is largely
2359implemented with case statements on the instruction types defined in
2360<tt>XXXInstrInfo.h</tt>. For example, in <tt>X86CodeEmitter.cpp</tt>,
2361the <tt>emitInstruction</tt> method is built around the following switch/case
2362statements:
2363</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2364
2365<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2366<pre>
2367switch (Desc-&gt;TSFlags &amp; X86::FormMask) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2368case X86II::Pseudo: // for not yet implemented instructions
2369 ... // or pseudo-instructions
2370 break;
2371case X86II::RawFrm: // for instructions with a fixed opcode value
2372 ...
2373 break;
2374case X86II::AddRegFrm: // for instructions that have one register operand
2375 ... // added to their opcode
2376 break;
2377case X86II::MRMDestReg:// for instructions that use the Mod/RM byte
2378 ... // to specify a destination (register)
2379 break;
2380case X86II::MRMDestMem:// for instructions that use the Mod/RM byte
2381 ... // to specify a destination (memory)
2382 break;
2383case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte
2384 ... // to specify a source (register)
2385 break;
2386case X86II::MRMSrcMem: // for instructions that use the Mod/RM byte
2387 ... // to specify a source (memory)
2388 break;
2389case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
2390case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
2391case X86II::MRM4r: case X86II::MRM5r: // use the Mod/RM byte and a field
2392case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
2393 ...
2394 break;
2395case X86II::MRM0m: case X86II::MRM1m: // for instructions that operate on
2396case X86II::MRM2m: case X86II::MRM3m: // a MEMORY r/m operand and
2397case X86II::MRM4m: case X86II::MRM5m: // use the Mod/RM byte and a field
2398case X86II::MRM6m: case X86II::MRM7m: // to hold extended opcode data
2399 ...
2400 break;
2401case X86II::MRMInitReg: // for instructions whose source and
2402 ... // destination are the same register
2403 break;
2404}
2405</pre>
2406</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2407
2408<p>
2409The implementations of these case statements often first emit the opcode and
2410then get the operand(s). Then depending upon the operand, helper methods may be
2411called to process the operand(s). For example, in <tt>X86CodeEmitter.cpp</tt>,
2412for the <tt>X86II::AddRegFrm</tt> case, the first data emitted
2413(by <tt>emitByte</tt>) is the opcode added to the register operand. Then an
2414object representing the machine operand, <tt>MO1</tt>, is extracted. The helper
2415methods such as <tt>isImmediate</tt>,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2416<tt>isGlobalAddress</tt>, <tt>isExternalSymbol</tt>, <tt>isConstantPoolIndex</tt>, and
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2417<tt>isJumpTableIndex</tt> determine the operand
2418type. (<tt>X86CodeEmitter.cpp</tt> also has private methods such
2419as <tt>emitConstant</tt>, <tt>emitGlobalAddress</tt>,
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2420<tt>emitExternalSymbolAddress</tt>, <tt>emitConstPoolAddress</tt>,
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2421and <tt>emitJumpTableAddress</tt> that emit the data into the output stream.)
2422</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2423
2424<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2425<pre>
2426case X86II::AddRegFrm:
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2427 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
2428
2429 if (CurOp != NumOps) {
2430 const MachineOperand &amp;MO1 = MI.getOperand(CurOp++);
2431 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2432 if (MO1.isImmediate())
2433 emitConstant(MO1.getImm(), Size);
2434 else {
2435 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
2436 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
2437 if (Opcode == X86::MOV64ri)
2438 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
2439 if (MO1.isGlobalAddress()) {
2440 bool NeedStub = isa&lt;Function&gt;(MO1.getGlobal());
2441 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
2442 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
2443 NeedStub, isLazy);
2444 } else if (MO1.isExternalSymbol())
2445 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
2446 else if (MO1.isConstantPoolIndex())
2447 emitConstPoolAddress(MO1.getIndex(), rt);
2448 else if (MO1.isJumpTableIndex())
2449 emitJumpTableAddress(MO1.getIndex(), rt);
2450 }
2451 }
2452 break;
2453</pre>
2454</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2455
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2456<p>
2457In the previous example, <tt>XXXCodeEmitter.cpp</tt> uses the
2458variable <tt>rt</tt>, which is a RelocationType enum that may be used to
2459relocate addresses (for example, a global address with a PIC base offset). The
2460<tt>RelocationType</tt> enum for that target is defined in the short
2461target-specific <tt>XXXRelocations.h</tt> file. The <tt>RelocationType</tt> is used by
2462the <tt>relocate</tt> method defined in <tt>XXXJITInfo.cpp</tt> to rewrite
2463addresses for referenced global symbols.
2464</p>
2465
2466<p>
2467For example, <tt>X86Relocations.h</tt> specifies the following relocation types
2468for the X86 addresses. In all four cases, the relocated value is added to the
2469value already in memory. For <tt>reloc_pcrel_word</tt>
2470and <tt>reloc_picrel_word</tt>, there is an additional initial adjustment.
2471</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2472
2473<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2474<pre>
2475enum RelocationType {
2476 reloc_pcrel_word = 0, // add reloc value after adjusting for the PC loc
2477 reloc_picrel_word = 1, // add reloc value after adjusting for the PIC base
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2478 reloc_absolute_word = 2, // absolute relocation; no additional adjustment
2479 reloc_absolute_dword = 3 // absolute relocation; no additional adjustment
2480};
2481</pre>
2482</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2483
2484</div>
2485
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2486<!-- ======================================================================= -->
2487<div class="doc_subsection">
2488 <a name="targetJITInfo">Target JIT Info</a>
2489</div>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2490
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2491<div class="doc_text">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2492
2493<p>
2494<tt>XXXJITInfo.cpp</tt> implements the JIT interfaces for target-specific
2495code-generation activities, such as emitting machine code and stubs. At minimum,
2496a target-specific version of <tt>XXXJITInfo</tt> implements the following:
2497</p>
2498
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2499<ul>
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2500<li><tt>getLazyResolverFunction</tt> &mdash; Initializes the JIT, gives the
2501 target a function that is used for compilation.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2502
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2503<li><tt>emitFunctionStub</tt> &mdash; Returns a native function with a specified
2504 address for a callback function.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2505
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2506<li><tt>relocate</tt> &mdash; Changes the addresses of referenced globals, based
2507 on relocation types.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2508
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2509<li>Callback function that are wrappers to a function stub that is used when the
2510 real target is not initially known.</li>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2511</ul>
2512
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2513<p>
2514<tt>getLazyResolverFunction</tt> is generally trivial to implement. It makes the
2515incoming parameter as the global <tt>JITCompilerFunction</tt> and returns the
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2516callback function that will be used a function wrapper. For the Alpha target
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2517(in <tt>AlphaJITInfo.cpp</tt>), the <tt>getLazyResolverFunction</tt>
2518implementation is simply:
2519</p>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2520
2521<div class="doc_code">
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2522<pre>
2523TargetJITInfo::LazyResolverFn AlphaJITInfo::getLazyResolverFunction(
2524 JITCompilerFn F) {
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2525 JITCompilerFunction = F;
2526 return AlphaCompilationCallback;
2527}
2528</pre>
2529</div>
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2530
Bill Wendling4a2bca82009-04-05 00:41:19 +0000[diff] [blame]2531<p>
2532For the X86 target, the <tt>getLazyResolverFunction</tt> implementation is a
2533little more complication, because it returns a different callback function for
2534processors with SSE instructions and XMM registers.
2535</p>
2536
2537<p>
2538The callback function initially saves and later restores the callee register
2539values, incoming arguments, and frame and return address. The callback function
2540needs low-level access to the registers or stack, so it is typically implemented
2541with assembler.
2542</p>
2543
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2544</div>
2545
2546<!-- *********************************************************************** -->
2547
2548<hr>
2549<address>
2550 <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
Misha Brukman44408702008-12-11 17:34:48 +0000[diff] [blame]2551 src="http://jigsaw.w3.org/css-validator/images/vcss-blue" alt="Valid CSS"></a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2552 <a href="http://validator.w3.org/check/referer"><img
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Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2554
Chris Lattner78975382008-11-11 19:30:41 +0000[diff] [blame]2555 <a href="http://www.woo.com">Mason Woo</a> and <a href="http://misha.brukman.net">Misha Brukman</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]2556 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]2557 <br>
2558 Last modified: $Date$
2559</address>
2560
2561</body>
2562</html>