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4<head>
5 <title>Writing an LLVM backend</title>
6 <link rel="stylesheet" href="llvm.css" type="text/css">
7</head>
8
9<body>
10
11<div class="doc_title">
12 Writing an LLVM backend
13</div>
14
15<ol>
16 <li><a href="#intro">Introduction</a>
17 <li><a href="#backends">Writing a backend</a>
18 <ol>
Chris Lattner7a2fd892004-09-18 06:28:07 +0000[diff] [blame]19 <li><a href="#machine">Machine backends</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]20 <ol>
21 <li><a href="#machineTOC">Outline</a></li>
22 <li><a href="#machineDetails">Implementation details</a></li>
23 </ol></li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]24 <li><a href="#lang">Language backends</a></li>
25 </ol></li>
26 <li><a href="#related">Related reading material</a>
27</ol>
28
29<div class="doc_author">
30 <p>Written by <a href="http://misha.brukman.net">Misha Brukman</a></p>
31</div>
32
33<!-- *********************************************************************** -->
34<div class="doc_section">
35 <a name="intro">Introduction</a>
36</div>
37<!-- *********************************************************************** -->
38
39<div class="doc_text">
40
41<p>This document describes techniques for writing backends for LLVM which
42convert the LLVM representation to machine assembly code or other languages.</p>
43
44</div>
45
46<!-- *********************************************************************** -->
47<div class="doc_section">
48 <a name="backends">Writing a backend</a>
49</div>
50<!-- *********************************************************************** -->
51
52<!-- ======================================================================= -->
53<div class="doc_subsection">
54 <a name="machine">Machine backends</a>
55</div>
56
57<!-- _______________________________________________________________________ -->
58<div class="doc_subsubsection">
59 <a name="machineTOC">Outline</a>
60</div>
61
62<div class="doc_text">
63
Chris Lattner8e9f2ce2006-04-24 16:34:45 +0000[diff] [blame]64<p>In general, you want to follow the format of SPARC, X86 or PowerPC (in
65<tt>lib/Target</tt>). SPARC is the simplest backend, and is RISC, so if
66you're working on a RISC target, it is a good one to start with.</p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]67
68<p>To create a static compiler (one that emits text assembly), you need to
69implement the following:</p>
70
71<ul>
Chris Lattnerc3b05402005-10-16 17:03:22 +0000[diff] [blame]72<li>Describe the register set.
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]73 <ul>
74 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
75 the register set and register classes</li>
76 <li>Implement a subclass of <tt><a
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]77 href="CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a></tt></li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]78 </ul></li>
Chris Lattnerc3b05402005-10-16 17:03:22 +0000[diff] [blame]79<li>Describe the instruction set.
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]80 <ul>
81 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
82 the instruction set</li>
83 <li>Implement a subclass of <tt><a
84 href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a></tt></li>
85 </ul></li>
Chris Lattnerc3b05402005-10-16 17:03:22 +0000[diff] [blame]86<li>Describe the target machine.
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]87 <ul>
88 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
89 the target that describes the pointer size and references the instruction
90 set</li>
91 <li>Implement a subclass of <tt><a
92 href="CodeGenerator.html#targetmachine">TargetMachine</a></tt>, which
93 configures <tt><a href="CodeGenerator.html#targetdata">TargetData</a></tt>
94 correctly</li>
Misha Brukman93d416f2004-12-27 19:05:16 +0000[diff] [blame]95 <li>Register your new target using the <tt>RegisterTarget</tt>
96 template:<br><br>
97<div class="doc_code"><pre>
98RegisterTarget&lt;<em>MyTargetMachine</em>&gt; M("short_name", " Target name");
99</pre></div>
100 <br>Here, <em>MyTargetMachine</em> is the name of your implemented
101 subclass of <tt><a
102 href="CodeGenerator.html#targetmachine">TargetMachine</a></tt>,
103 <em>short_name</em> is the option that will be active following
104 <tt>-march=</tt> to select a target in llc and lli, and the last string
105 is the description of your target to appear in <tt>-help</tt>
106 listing.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]107 </ul></li>
Chris Lattnerc3b05402005-10-16 17:03:22 +0000[diff] [blame]108<li>Implement the assembly printer for the architecture.
109 <ul>
110 <li>Define all of the assembly strings for your target, adding them to the
111 instructions in your *InstrInfo.td file.</li>
112 <li>Implement the <tt>llvm::AsmPrinter</tt> interface.</li>
113 </ul>
114</li>
115<li>Implement an instruction selector for the architecture.
116 <ul>
117 <li>The recommended method is the <a href="CodeGenerator.html#instselect">
118 pattern-matching DAG-to-DAG instruction selector</a> (for example, see
119 the PowerPC backend in PPCISelDAGtoDAG.cpp). Parts of instruction
120 selector creation can be performed by adding patterns to the instructions
121 in your <tt>.td</tt> file.</li>
122 </ul>
123</li>
124<li>Optionally, add subtarget support.
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]125<ul>
Chris Lattnerc3b05402005-10-16 17:03:22 +0000[diff] [blame]126 <li>If your target has multiple subtargets (e.g. variants with different
127 capabilities), implement the <tt>llvm::TargetSubtarget</tt> interface
128 for your architecture. This allows you to add <tt>-mcpu=</tt> and
129 <tt>-mattr=</tt> options.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]130</ul>
Chris Lattnerc3b05402005-10-16 17:03:22 +0000[diff] [blame]131<li>Optionally, add JIT support.
132 <ul>
133 <li>Create a subclass of <tt><a
134 href="CodeGenerator.html#targetjitinfo">TargetJITInfo</a></tt></li>
135 <li>Create a machine code emitter that will be used to emit binary code
136 directly into memory, given <tt>MachineInstr</tt>s</li>
137 </ul>
138</ul>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]139</div>
140
141<!-- _______________________________________________________________________ -->
142<div class="doc_subsubsection">
143 <a name="machineDetails">Implementation details</a>
144</div>
145
146<div class="doc_text">
147
148<ul>
149
150<li><p><b>TableGen register info description</b> - describe a class which
151will store the register's number in the binary encoding of the instruction
152(e.g., for JIT purposes).</p>
153
154<p>You also need to define register classes to contain these registers, such as
155the integer register class and floating-point register class, so that you can
156allocate virtual registers to instructions from these sets, and let the
157target-independent register allocator automatically choose the actual
158architected registers.</p>
159
160<div class="doc_code">
161<pre>
162// class Register is defined in Target.td
Chris Lattner7a2fd892004-09-18 06:28:07 +0000[diff] [blame]163<b>class</b> <em>Target</em>Reg&lt;string name&gt; : Register&lt;name&gt; {
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]164 <b>let</b> Namespace = "<em>Target</em>";
165}
166
Chris Lattner7a2fd892004-09-18 06:28:07 +0000[diff] [blame]167<b>class</b> IntReg&lt;<b>bits</b>&lt;5&gt; num, string name&gt; : <em>Target</em>Reg&lt;name&gt; {
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]168 <b>field</b> <b>bits</b>&lt;5&gt; Num = num;
169}
170
Chris Lattner7a2fd892004-09-18 06:28:07 +0000[diff] [blame]171<b>def</b> R0 : IntReg&lt;0, "%R0"&gt;;
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]172...
173
174// class RegisterClass is defined in Target.td
175<b>def</b> IReg : RegisterClass&lt;i64, 64, [R0, ... ]&gt;;
176</pre>
177</div>
178</li>
179
180<li><p><b>TableGen instruction info description</b> - break up instructions into
181classes, usually that's already done by the manufacturer (see instruction
182manual). Define a class for each instruction category. Define each opcode as a
183subclass of the category, with appropriate parameters such as the fixed binary
184encoding of opcodes and extended opcodes, and map the register bits to the bits
185of the instruction which they are encoded in (for the JIT). Also specify how
186the instruction should be printed so it can use the automatic assembly printer,
187e.g.:</p>
188
189<div class="doc_code">
190<pre>
191// class Instruction is defined in Target.td
192<b>class</b> Form&lt;<b>bits</b>&lt;6&gt; opcode, <b>dag</b> OL, <b>string</b> asmstr&gt; : Instruction {
193 <b>field</b> <b>bits</b>&lt;42&gt; Inst;
194
195 <b>let</b> Namespace = "<em>Target</em>";
196 <b>let</b> Inst{0-6} = opcode;
197 <b>let</b> OperandList = OL;
198 <b>let</b> AsmString = asmstr;
199}
200
201<b>def</b> ADD : Form&lt;42, (ops IReg:$rD, IReg:$rA, IReg:$rB), "add $rD, $rA, $rB"&gt;;
202</pre>
203</div>
204</li>
205
206</ul>
207
208</div>
209
210<!-- ======================================================================= -->
211<div class="doc_subsection">
212 <a name="lang">Language backends</a>
213</div>
214
215<div class="doc_text">
216
217<p>For now, just take a look at <tt>lib/Target/CBackend</tt> for an example of
218how the C backend is written.</p>
219
220</div>
Matthijs Kooijman6aa81272008-09-29 11:52:22 +0000[diff] [blame^]221<!-- ======================================================================= -->
222<div class="doc_subsection">
223 <a name="files">Files to create/modify</a>
224</div>
225
226<div class="doc_text">
227
228<p>To actually create your backend, you need to create and modify a few files.
229Here, the absolute minimum will be discussed. To actually use LLVM's target
230independent codegenerator, you must <a href="CodeGenerator.html">implement extra
231things</a>.</p>
232
233<p>First of all, you should create a subdirectory under <tt>lib/Target</tt>,
234which will hold all the files related to your target. Let's assume that our
235target is called, "Dummy", we would create the directory
236<tt>lib/Target/Dummy</tt>.</p>
237
238<p>In this new directory, you should put a <tt>Makefile</tt>. You can probably
239copy one from another target and modify it. It should at least contain the
240<tt>LEVEL</tt>, <tt>LIBRARYNAME</tt> and <tt>TARGET</tt> variables, and then
241include <tt>$(LEVEL)/Makefile.common</tt>. Be careful to give the library the
242correct name, it must be named <tt>LLVMDummy</tt> (see the MIPS target, for
243example). Alternatively, you can split the library into
244<tt>LLVMDummyCodeGen</tt> and <tt>LLVMDummyAsmPrinter</tt>, the latter of which
245should be implemented in a subdirectory below <tt>lib/Target/Dummy</tt> (see the
246PowerPC target, for example).</p>
247
248<p>Note that these two naming schemes are hardcoded into llvm-config. Using any
249other naming scheme will confuse llvm-config and produce lots of (seemingly
250unrelated) linker errors when linking <tt>llc</tt>.</p>
251
252<p>To make your target actually do something, you need to implement a subclass
253of <tt>TargetMachine</tt>. This implementation should typically be in the file
254<tt>lib/Target/DummyTargetMachine.cpp</tt>, but any file in the
255<tt>lib/Target</tt> directory will be built and should work. To use LLVM's <a
256href="CodeGenerator.html">target independent code generator</a>, you should
257create a subclass of <tt>LLVMTargetMachine</tt>. This is what all current
258machine backends do. To create a target from scratch, create a subclass of
259<tt>TargetMachine</tt>. This is what the current language backends do.</p>
260
261<p>To get LLVM to actually build and link your target, you also need to add it
262to the <tt>TARGETS_TO_BUILD</tt> variable. To do this, you need to modify the
263<tt>configure</tt> script to know about your target when parsing the
264<tt>--enable-targets</tt> option. Search the <tt>configure</tt> script for
265<tt>TARGETS_TO_BUILD</tt>, add your target to the lists there (some creativity
266required) and then reconfigure. Alternatively, you can change
267<tt>autotools/configure.ac</tt> and regenerate <tt>configure</tt> by running
268<tt>./autoconf/AutoRegen.sh</tt>.
269
270</div>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]271
272<!-- *********************************************************************** -->
273<div class="doc_section">
274 <a name="related">Related reading material</a>
275</div>
276<!-- *********************************************************************** -->
277
278<div class="doc_text">
279
280<ul>
281<li><a href="CodeGenerator.html">Code generator</a> -
282 describes some of the classes in code generation at a high level, but
Misha Brukmana3bfc6f2005-05-17 02:12:32 +0000[diff] [blame]283 it is not (yet) complete</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]284<li><a href="TableGenFundamentals.html">TableGen fundamentals</a> -
Misha Brukmana3bfc6f2005-05-17 02:12:32 +0000[diff] [blame]285 describes how to use TableGen to describe your target information
286 succinctly</li>
287<li><a href="HowToSubmitABug.html#codegen">Debugging code generation with
288 bugpoint</a> - shows bugpoint usage scenarios to simplify backend
289 development</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]290</ul>
291
292</div>
293
294<!-- *********************************************************************** -->
295
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