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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / c459bbf0fdef4e9b074de8fee1728c08348c46dc / . / lib / Target / Alpha / AlphaLLRP.cpp
blob: adae36f1cfde1173189e25ad766668b0a8924eae [file] [log] [blame]
Andrew Lenharth2ab804c2006-09-18 19:44:29 +0000[diff] [blame]1//===-- AlphaLLRP.cpp - Alpha Load Load Replay Trap elimination pass. -- --===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by Andrew Lenharth and is distributed under the
6// University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Here we check for potential replay traps introduced by the spiller
11// We also align some branch targets if we can do so for free
12//===----------------------------------------------------------------------===//
13
14
15#include "Alpha.h"
16#include "llvm/CodeGen/MachineFunctionPass.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/ADT/SetOperations.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/Support/CommandLine.h"
21using namespace llvm;
22
23namespace {
24 Statistic<> nopintro("alpha-nops", "Number of nops inserted");
25 Statistic<> nopalign("alpha-nops-align",
26 "Number of nops inserted for alignment");
27
28 cl::opt<bool>
29 AlignAll("alpha-align-all", cl::Hidden,
30 cl::desc("Align all blocks"));
31
32 struct AlphaLLRPPass : public MachineFunctionPass {
33 /// Target machine description which we query for reg. names, data
34 /// layout, etc.
35 ///
36 AlphaTargetMachine &TM;
37
38 AlphaLLRPPass(AlphaTargetMachine &tm) : TM(tm) { }
39
40 virtual const char *getPassName() const {
41 return "Alpha NOP inserter";
42 }
43
44 bool runOnMachineFunction(MachineFunction &F) {
45 bool Changed = false;
46 MachineInstr* prev[3] = {0,0,0};
47 unsigned count = 0;
48 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
49 FI != FE; ++FI) {
50 MachineBasicBlock& MBB = *FI;
51 bool ub = false;
52 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
53 if (count%4 == 0)
54 prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
55 ++count;
56 MachineInstr *MI = I++;
57 switch (MI->getOpcode()) {
58 case Alpha::LDQ: case Alpha::LDL:
59 case Alpha::LDWU: case Alpha::LDBU:
60 case Alpha::LDT: case Alpha::LDS:
Andrew Lenharth2ab804c2006-09-18 19:44:29 +0000[diff] [blame]61 case Alpha::STQ: case Alpha::STL:
62 case Alpha::STW: case Alpha::STB:
63 case Alpha::STT: case Alpha::STS:
64 if (MI->getOperand(2).getReg() == Alpha::R30) {
65 if (prev[0]
66 && prev[0]->getOperand(2).getReg() ==
67 MI->getOperand(2).getReg()
68 && prev[0]->getOperand(1).getImmedValue() ==
69 MI->getOperand(1).getImmedValue()) {
70 prev[0] = prev[1];
71 prev[1] = prev[2];
72 prev[2] = 0;
73 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
74 .addReg(Alpha::R31);
75 Changed = true; nopintro += 1;
76 count += 1;
77 } else if (prev[1]
78 && prev[1]->getOperand(2).getReg() ==
79 MI->getOperand(2).getReg()
80 && prev[1]->getOperand(1).getImmedValue() ==
81 MI->getOperand(1).getImmedValue()) {
82 prev[0] = prev[2];
83 prev[1] = prev[2] = 0;
84 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
85 .addReg(Alpha::R31);
86 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
87 .addReg(Alpha::R31);
88 Changed = true; nopintro += 2;
89 count += 2;
90 } else if (prev[2]
Andrew Lenharthc459bbf2006-09-20 20:08:52 +0000[diff] [blame^]91 && prev[2]->getOperand(2).getReg() ==
92 MI->getOperand(2).getReg()
93 && prev[2]->getOperand(1).getImmedValue() ==
94 MI->getOperand(1).getImmedValue()) {
95 prev[0] = prev[1] = prev[2] = 0;
96 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
97 .addReg(Alpha::R31);
98 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
99 .addReg(Alpha::R31);
100 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
101 .addReg(Alpha::R31);
102 Changed = true; nopintro += 3;
103 count += 3;
104 }
105 prev[0] = prev[1];
106 prev[1] = prev[2];
107 prev[2] = MI;
108 break;
109 }
110 prev[0] = prev[1];
111 prev[1] = prev[2];
112 prev[2] = 0;
113 break;
114 case Alpha::ALTENT:
115 case Alpha::MEMLABEL:
116 case Alpha::PCLABEL:
117 --count;
118 break;
119 case Alpha::BR:
120 case Alpha::JMP:
121 ub = true;
122 //fall through
123 default:
124 prev[0] = prev[1];
125 prev[1] = prev[2];
126 prev[2] = 0;
127 break;
128 }
129 }
130 if (ub || AlignAll) {
131 //we can align stuff for free at this point
132 while (count % 4) {
133 BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31)
134 .addReg(Alpha::R31).addReg(Alpha::R31);
135 ++count;
136 ++nopalign;
137 prev[0] = prev[1];
138 prev[1] = prev[2];
139 prev[2] = 0;
140 }
141 }
Andrew Lenharth2ab804c2006-09-18 19:44:29 +0000[diff] [blame]142 }
143 return Changed;
144 }
145 };
146} // end of anonymous namespace
147
148FunctionPass *llvm::createAlphaLLRPPass(AlphaTargetMachine &tm) {
149 return new AlphaLLRPPass(tm);
150}