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Rafael Espindola7bc59bc2006-05-14 22:18:28 +00001//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the "Instituto Nokia de Tecnologia" and
6// is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===----------------------------------------------------------------------===//
10//
11// This file contains the entry points for global functions defined in the LLVM
12// ARM back-end.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef TARGET_ARM_H
17#define TARGET_ARM_H
18
19#include <iosfwd>
20#include <cassert>
21
22namespace llvm {
Rafael Espindola6f602de2006-08-24 16:13:15 +000023 // Enums corresponding to ARM condition codes
24 namespace ARMCC {
25 enum CondCodes {
Rafael Espindolacdda88c2006-08-24 17:19:08 +000026 NE,
27 EQ
Rafael Espindola6f602de2006-08-24 16:13:15 +000028 };
29 }
30
31 static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
32 switch (CC) {
33 default: assert(0 && "Unknown condition code");
34 case ARMCC::NE: return "ne";
Rafael Espindolacdda88c2006-08-24 17:19:08 +000035 case ARMCC::EQ: return "eq";
Rafael Espindola6f602de2006-08-24 16:13:15 +000036 }
37 }
38
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000039 class FunctionPass;
40 class TargetMachine;
41
42 FunctionPass *createARMISelDag(TargetMachine &TM);
43 FunctionPass *createARMCodePrinterPass(std::ostream &OS, TargetMachine &TM);
44} // end namespace llvm;
45
46// Defines symbolic names for ARM registers. This defines a mapping from
47// register name to register number.
48//
49#include "ARMGenRegisterNames.inc"
50
51// Defines symbolic names for the ARM instructions.
52//
53#include "ARMGenInstrNames.inc"
54
55
56#endif