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Lang Hames87e3bca2009-05-06 02:36:21 +00001//===-- llvm/CodeGen/Rewriter.cpp - Rewriter -----------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE "virtregrewriter"
11#include "VirtRegRewriter.h"
Benjamin Kramercfa6ec92009-08-23 11:37:21 +000012#include "llvm/Function.h"
13#include "llvm/CodeGen/MachineFrameInfo.h"
14#include "llvm/CodeGen/MachineInstrBuilder.h"
15#include "llvm/CodeGen/MachineRegisterInfo.h"
Benjamin Kramercfa6ec92009-08-23 11:37:21 +000016#include "llvm/Support/CommandLine.h"
17#include "llvm/Support/Debug.h"
Torok Edwinc25e7582009-07-11 20:10:48 +000018#include "llvm/Support/ErrorHandling.h"
Daniel Dunbarce63ffb2009-07-25 00:23:56 +000019#include "llvm/Support/raw_ostream.h"
Benjamin Kramercfa6ec92009-08-23 11:37:21 +000020#include "llvm/Target/TargetInstrInfo.h"
David Greene2d4e6d32009-07-28 16:49:24 +000021#include "llvm/Target/TargetLowering.h"
Lang Hames87e3bca2009-05-06 02:36:21 +000022#include "llvm/ADT/DepthFirstIterator.h"
23#include "llvm/ADT/Statistic.h"
Lang Hames87e3bca2009-05-06 02:36:21 +000024#include <algorithm>
25using namespace llvm;
26
27STATISTIC(NumDSE , "Number of dead stores elided");
28STATISTIC(NumDSS , "Number of dead spill slots removed");
29STATISTIC(NumCommutes, "Number of instructions commuted");
30STATISTIC(NumDRM , "Number of re-materializable defs elided");
31STATISTIC(NumStores , "Number of stores added");
32STATISTIC(NumPSpills , "Number of physical register spills");
33STATISTIC(NumOmitted , "Number of reloads omited");
34STATISTIC(NumAvoided , "Number of reloads deemed unnecessary");
35STATISTIC(NumCopified, "Number of available reloads turned into copies");
36STATISTIC(NumReMats , "Number of re-materialization");
37STATISTIC(NumLoads , "Number of loads added");
38STATISTIC(NumReused , "Number of values reused");
39STATISTIC(NumDCE , "Number of copies elided");
40STATISTIC(NumSUnfold , "Number of stores unfolded");
41STATISTIC(NumModRefUnfold, "Number of modref unfolded");
42
43namespace {
Lang Hamesac276402009-06-04 18:45:36 +000044 enum RewriterName { local, trivial };
Lang Hames87e3bca2009-05-06 02:36:21 +000045}
46
47static cl::opt<RewriterName>
48RewriterOpt("rewriter",
49 cl::desc("Rewriter to use: (default: local)"),
50 cl::Prefix,
Lang Hamesac276402009-06-04 18:45:36 +000051 cl::values(clEnumVal(local, "local rewriter"),
Lang Hamesf41538d2009-06-02 16:53:25 +000052 clEnumVal(trivial, "trivial rewriter"),
Lang Hames87e3bca2009-05-06 02:36:21 +000053 clEnumValEnd),
54 cl::init(local));
55
Dan Gohman7db949d2009-08-07 01:32:21 +000056static cl::opt<bool>
David Greene2d4e6d32009-07-28 16:49:24 +000057ScheduleSpills("schedule-spills",
58 cl::desc("Schedule spill code"),
59 cl::init(false));
60
Lang Hames87e3bca2009-05-06 02:36:21 +000061VirtRegRewriter::~VirtRegRewriter() {}
62
Dan Gohman7db949d2009-08-07 01:32:21 +000063namespace {
Lang Hames87e3bca2009-05-06 02:36:21 +000064
Lang Hamesf41538d2009-06-02 16:53:25 +000065/// This class is intended for use with the new spilling framework only. It
66/// rewrites vreg def/uses to use the assigned preg, but does not insert any
67/// spill code.
Nick Lewycky6726b6d2009-10-25 06:33:48 +000068struct TrivialRewriter : public VirtRegRewriter {
Lang Hamesf41538d2009-06-02 16:53:25 +000069
70 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM,
71 LiveIntervals* LIs) {
Chris Lattner6456d382009-08-23 03:20:44 +000072 DEBUG(errs() << "********** REWRITE MACHINE CODE **********\n");
Daniel Dunbarce63ffb2009-07-25 00:23:56 +000073 DEBUG(errs() << "********** Function: "
74 << MF.getFunction()->getName() << '\n');
Chris Lattner6456d382009-08-23 03:20:44 +000075 DEBUG(errs() << "**** Machine Instrs"
76 << "(NOTE! Does not include spills and reloads!) ****\n");
David Greene2d4e6d32009-07-28 16:49:24 +000077 DEBUG(MF.dump());
78
Lang Hamesf41538d2009-06-02 16:53:25 +000079 MachineRegisterInfo *mri = &MF.getRegInfo();
80
81 bool changed = false;
82
83 for (LiveIntervals::iterator liItr = LIs->begin(), liEnd = LIs->end();
84 liItr != liEnd; ++liItr) {
85
86 if (TargetRegisterInfo::isVirtualRegister(liItr->first)) {
87 if (VRM.hasPhys(liItr->first)) {
88 unsigned preg = VRM.getPhys(liItr->first);
89 mri->replaceRegWith(liItr->first, preg);
90 mri->setPhysRegUsed(preg);
91 changed = true;
92 }
93 }
94 else {
95 if (!liItr->second->empty()) {
96 mri->setPhysRegUsed(liItr->first);
97 }
98 }
99 }
David Greene2d4e6d32009-07-28 16:49:24 +0000100
101
Chris Lattner6456d382009-08-23 03:20:44 +0000102 DEBUG(errs() << "**** Post Machine Instrs ****\n");
David Greene2d4e6d32009-07-28 16:49:24 +0000103 DEBUG(MF.dump());
Lang Hamesf41538d2009-06-02 16:53:25 +0000104
105 return changed;
106 }
107
108};
109
Dan Gohman7db949d2009-08-07 01:32:21 +0000110}
111
Lang Hames87e3bca2009-05-06 02:36:21 +0000112// ************************************************************************ //
113
Dan Gohman7db949d2009-08-07 01:32:21 +0000114namespace {
115
Lang Hames87e3bca2009-05-06 02:36:21 +0000116/// AvailableSpills - As the local rewriter is scanning and rewriting an MBB
117/// from top down, keep track of which spill slots or remat are available in
118/// each register.
119///
120/// Note that not all physregs are created equal here. In particular, some
121/// physregs are reloads that we are allowed to clobber or ignore at any time.
122/// Other physregs are values that the register allocated program is using
123/// that we cannot CHANGE, but we can read if we like. We keep track of this
124/// on a per-stack-slot / remat id basis as the low bit in the value of the
125/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
126/// this bit and addAvailable sets it if.
Nick Lewycky6726b6d2009-10-25 06:33:48 +0000127class AvailableSpills {
Lang Hames87e3bca2009-05-06 02:36:21 +0000128 const TargetRegisterInfo *TRI;
129 const TargetInstrInfo *TII;
130
131 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
132 // or remat'ed virtual register values that are still available, due to
133 // being loaded or stored to, but not invalidated yet.
134 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
135
136 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
137 // indicating which stack slot values are currently held by a physreg. This
138 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
139 // physreg is modified.
140 std::multimap<unsigned, int> PhysRegsAvailable;
141
142 void disallowClobberPhysRegOnly(unsigned PhysReg);
143
144 void ClobberPhysRegOnly(unsigned PhysReg);
145public:
146 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
147 : TRI(tri), TII(tii) {
148 }
149
150 /// clear - Reset the state.
151 void clear() {
152 SpillSlotsOrReMatsAvailable.clear();
153 PhysRegsAvailable.clear();
154 }
155
156 const TargetRegisterInfo *getRegInfo() const { return TRI; }
157
158 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
159 /// available in a physical register, return that PhysReg, otherwise
160 /// return 0.
161 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
162 std::map<int, unsigned>::const_iterator I =
163 SpillSlotsOrReMatsAvailable.find(Slot);
164 if (I != SpillSlotsOrReMatsAvailable.end()) {
165 return I->second >> 1; // Remove the CanClobber bit.
166 }
167 return 0;
168 }
169
170 /// addAvailable - Mark that the specified stack slot / remat is available
171 /// in the specified physreg. If CanClobber is true, the physreg can be
172 /// modified at any time without changing the semantics of the program.
173 void addAvailable(int SlotOrReMat, unsigned Reg, bool CanClobber = true) {
174 // If this stack slot is thought to be available in some other physreg,
175 // remove its record.
176 ModifyStackSlotOrReMat(SlotOrReMat);
177
178 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
179 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) |
180 (unsigned)CanClobber;
181
182 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
Chris Lattner6456d382009-08-23 03:20:44 +0000183 DEBUG(errs() << "Remembering RM#"
184 << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1);
Lang Hames87e3bca2009-05-06 02:36:21 +0000185 else
Chris Lattner6456d382009-08-23 03:20:44 +0000186 DEBUG(errs() << "Remembering SS#" << SlotOrReMat);
187 DEBUG(errs() << " in physreg " << TRI->getName(Reg) << "\n");
Lang Hames87e3bca2009-05-06 02:36:21 +0000188 }
189
190 /// canClobberPhysRegForSS - Return true if the spiller is allowed to change
191 /// the value of the specified stackslot register if it desires. The
192 /// specified stack slot must be available in a physreg for this query to
193 /// make sense.
194 bool canClobberPhysRegForSS(int SlotOrReMat) const {
195 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
196 "Value not available!");
197 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
198 }
199
200 /// canClobberPhysReg - Return true if the spiller is allowed to clobber the
201 /// physical register where values for some stack slot(s) might be
202 /// available.
203 bool canClobberPhysReg(unsigned PhysReg) const {
204 std::multimap<unsigned, int>::const_iterator I =
205 PhysRegsAvailable.lower_bound(PhysReg);
206 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
207 int SlotOrReMat = I->second;
208 I++;
209 if (!canClobberPhysRegForSS(SlotOrReMat))
210 return false;
211 }
212 return true;
213 }
214
215 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
216 /// stackslot register. The register is still available but is no longer
217 /// allowed to be modifed.
218 void disallowClobberPhysReg(unsigned PhysReg);
219
220 /// ClobberPhysReg - This is called when the specified physreg changes
221 /// value. We use this to invalidate any info about stuff that lives in
222 /// it and any of its aliases.
223 void ClobberPhysReg(unsigned PhysReg);
224
225 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
226 /// slot changes. This removes information about which register the
227 /// previous value for this slot lives in (as the previous value is dead
228 /// now).
229 void ModifyStackSlotOrReMat(int SlotOrReMat);
230
231 /// AddAvailableRegsToLiveIn - Availability information is being kept coming
232 /// into the specified MBB. Add available physical registers as potential
233 /// live-in's. If they are reused in the MBB, they will be added to the
234 /// live-in set to make register scavenger and post-allocation scheduler.
235 void AddAvailableRegsToLiveIn(MachineBasicBlock &MBB, BitVector &RegKills,
236 std::vector<MachineOperand*> &KillOps);
237};
238
Dan Gohman7db949d2009-08-07 01:32:21 +0000239}
240
Lang Hames87e3bca2009-05-06 02:36:21 +0000241// ************************************************************************ //
242
David Greene2d4e6d32009-07-28 16:49:24 +0000243// Given a location where a reload of a spilled register or a remat of
244// a constant is to be inserted, attempt to find a safe location to
245// insert the load at an earlier point in the basic-block, to hide
246// latency of the load and to avoid address-generation interlock
247// issues.
248static MachineBasicBlock::iterator
249ComputeReloadLoc(MachineBasicBlock::iterator const InsertLoc,
250 MachineBasicBlock::iterator const Begin,
251 unsigned PhysReg,
252 const TargetRegisterInfo *TRI,
253 bool DoReMat,
254 int SSorRMId,
255 const TargetInstrInfo *TII,
256 const MachineFunction &MF)
257{
258 if (!ScheduleSpills)
259 return InsertLoc;
260
261 // Spill backscheduling is of primary interest to addresses, so
262 // don't do anything if the register isn't in the register class
263 // used for pointers.
264
265 const TargetLowering *TL = MF.getTarget().getTargetLowering();
266
267 if (!TL->isTypeLegal(TL->getPointerTy()))
268 // Believe it or not, this is true on PIC16.
269 return InsertLoc;
270
271 const TargetRegisterClass *ptrRegClass =
272 TL->getRegClassFor(TL->getPointerTy());
273 if (!ptrRegClass->contains(PhysReg))
274 return InsertLoc;
275
276 // Scan upwards through the preceding instructions. If an instruction doesn't
277 // reference the stack slot or the register we're loading, we can
278 // backschedule the reload up past it.
279 MachineBasicBlock::iterator NewInsertLoc = InsertLoc;
280 while (NewInsertLoc != Begin) {
281 MachineBasicBlock::iterator Prev = prior(NewInsertLoc);
282 for (unsigned i = 0; i < Prev->getNumOperands(); ++i) {
283 MachineOperand &Op = Prev->getOperand(i);
284 if (!DoReMat && Op.isFI() && Op.getIndex() == SSorRMId)
285 goto stop;
286 }
287 if (Prev->findRegisterUseOperandIdx(PhysReg) != -1 ||
288 Prev->findRegisterDefOperand(PhysReg))
289 goto stop;
290 for (const unsigned *Alias = TRI->getAliasSet(PhysReg); *Alias; ++Alias)
291 if (Prev->findRegisterUseOperandIdx(*Alias) != -1 ||
292 Prev->findRegisterDefOperand(*Alias))
293 goto stop;
294 NewInsertLoc = Prev;
295 }
296stop:;
297
298 // If we made it to the beginning of the block, turn around and move back
299 // down just past any existing reloads. They're likely to be reloads/remats
300 // for instructions earlier than what our current reload/remat is for, so
301 // they should be scheduled earlier.
302 if (NewInsertLoc == Begin) {
303 int FrameIdx;
304 while (InsertLoc != NewInsertLoc &&
305 (TII->isLoadFromStackSlot(NewInsertLoc, FrameIdx) ||
306 TII->isTriviallyReMaterializable(NewInsertLoc)))
307 ++NewInsertLoc;
308 }
309
310 return NewInsertLoc;
311}
Dan Gohman7db949d2009-08-07 01:32:21 +0000312
313namespace {
314
Lang Hames87e3bca2009-05-06 02:36:21 +0000315// ReusedOp - For each reused operand, we keep track of a bit of information,
316// in case we need to rollback upon processing a new operand. See comments
317// below.
318struct ReusedOp {
319 // The MachineInstr operand that reused an available value.
320 unsigned Operand;
321
322 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
323 unsigned StackSlotOrReMat;
324
325 // PhysRegReused - The physical register the value was available in.
326 unsigned PhysRegReused;
327
328 // AssignedPhysReg - The physreg that was assigned for use by the reload.
329 unsigned AssignedPhysReg;
330
331 // VirtReg - The virtual register itself.
332 unsigned VirtReg;
333
334 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
335 unsigned vreg)
336 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
337 AssignedPhysReg(apr), VirtReg(vreg) {}
338};
339
340/// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
341/// is reused instead of reloaded.
Nick Lewycky6726b6d2009-10-25 06:33:48 +0000342class ReuseInfo {
Lang Hames87e3bca2009-05-06 02:36:21 +0000343 MachineInstr &MI;
344 std::vector<ReusedOp> Reuses;
345 BitVector PhysRegsClobbered;
346public:
347 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) {
348 PhysRegsClobbered.resize(tri->getNumRegs());
349 }
350
351 bool hasReuses() const {
352 return !Reuses.empty();
353 }
354
355 /// addReuse - If we choose to reuse a virtual register that is already
356 /// available instead of reloading it, remember that we did so.
357 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
358 unsigned PhysRegReused, unsigned AssignedPhysReg,
359 unsigned VirtReg) {
360 // If the reload is to the assigned register anyway, no undo will be
361 // required.
362 if (PhysRegReused == AssignedPhysReg) return;
363
364 // Otherwise, remember this.
365 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
366 AssignedPhysReg, VirtReg));
367 }
368
369 void markClobbered(unsigned PhysReg) {
370 PhysRegsClobbered.set(PhysReg);
371 }
372
373 bool isClobbered(unsigned PhysReg) const {
374 return PhysRegsClobbered.test(PhysReg);
375 }
376
377 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
378 /// is some other operand that is using the specified register, either pick
379 /// a new register to use, or evict the previous reload and use this reg.
Evan Cheng5d885022009-07-21 09:15:00 +0000380 unsigned GetRegForReload(const TargetRegisterClass *RC, unsigned PhysReg,
381 MachineFunction &MF, MachineInstr *MI,
Lang Hames87e3bca2009-05-06 02:36:21 +0000382 AvailableSpills &Spills,
383 std::vector<MachineInstr*> &MaybeDeadStores,
384 SmallSet<unsigned, 8> &Rejected,
385 BitVector &RegKills,
386 std::vector<MachineOperand*> &KillOps,
387 VirtRegMap &VRM);
388
389 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
390 /// 'Rejected' set to remember which registers have been considered and
391 /// rejected for the reload. This avoids infinite looping in case like
392 /// this:
393 /// t1 := op t2, t3
394 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
395 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
396 /// t1 <- desires r1
397 /// sees r1 is taken by t2, tries t2's reload register r0
398 /// sees r0 is taken by t3, tries t3's reload register r1
399 /// sees r1 is taken by t2, tries t2's reload register r0 ...
Evan Cheng5d885022009-07-21 09:15:00 +0000400 unsigned GetRegForReload(unsigned VirtReg, unsigned PhysReg, MachineInstr *MI,
Lang Hames87e3bca2009-05-06 02:36:21 +0000401 AvailableSpills &Spills,
402 std::vector<MachineInstr*> &MaybeDeadStores,
403 BitVector &RegKills,
404 std::vector<MachineOperand*> &KillOps,
405 VirtRegMap &VRM) {
406 SmallSet<unsigned, 8> Rejected;
Evan Cheng5d885022009-07-21 09:15:00 +0000407 MachineFunction &MF = *MI->getParent()->getParent();
408 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
409 return GetRegForReload(RC, PhysReg, MF, MI, Spills, MaybeDeadStores,
410 Rejected, RegKills, KillOps, VRM);
Lang Hames87e3bca2009-05-06 02:36:21 +0000411 }
412};
413
Dan Gohman7db949d2009-08-07 01:32:21 +0000414}
Lang Hames87e3bca2009-05-06 02:36:21 +0000415
416// ****************** //
417// Utility Functions //
418// ****************** //
419
Lang Hames87e3bca2009-05-06 02:36:21 +0000420/// findSinglePredSuccessor - Return via reference a vector of machine basic
421/// blocks each of which is a successor of the specified BB and has no other
422/// predecessor.
423static void findSinglePredSuccessor(MachineBasicBlock *MBB,
424 SmallVectorImpl<MachineBasicBlock *> &Succs) {
425 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
426 SE = MBB->succ_end(); SI != SE; ++SI) {
427 MachineBasicBlock *SuccMBB = *SI;
428 if (SuccMBB->pred_size() == 1)
429 Succs.push_back(SuccMBB);
430 }
431}
432
Evan Cheng427a6b62009-05-15 06:48:19 +0000433/// InvalidateKill - Invalidate register kill information for a specific
434/// register. This also unsets the kills marker on the last kill operand.
435static void InvalidateKill(unsigned Reg,
436 const TargetRegisterInfo* TRI,
437 BitVector &RegKills,
438 std::vector<MachineOperand*> &KillOps) {
439 if (RegKills[Reg]) {
440 KillOps[Reg]->setIsKill(false);
Evan Cheng2c48fe62009-06-03 09:00:27 +0000441 // KillOps[Reg] might be a def of a super-register.
442 unsigned KReg = KillOps[Reg]->getReg();
443 KillOps[KReg] = NULL;
444 RegKills.reset(KReg);
445 for (const unsigned *SR = TRI->getSubRegisters(KReg); *SR; ++SR) {
Evan Cheng427a6b62009-05-15 06:48:19 +0000446 if (RegKills[*SR]) {
447 KillOps[*SR]->setIsKill(false);
448 KillOps[*SR] = NULL;
449 RegKills.reset(*SR);
450 }
451 }
452 }
453}
454
Lang Hames87e3bca2009-05-06 02:36:21 +0000455/// InvalidateKills - MI is going to be deleted. If any of its operands are
456/// marked kill, then invalidate the information.
Evan Cheng427a6b62009-05-15 06:48:19 +0000457static void InvalidateKills(MachineInstr &MI,
458 const TargetRegisterInfo* TRI,
459 BitVector &RegKills,
Lang Hames87e3bca2009-05-06 02:36:21 +0000460 std::vector<MachineOperand*> &KillOps,
461 SmallVector<unsigned, 2> *KillRegs = NULL) {
462 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
463 MachineOperand &MO = MI.getOperand(i);
Evan Cheng4784f1f2009-06-30 08:49:04 +0000464 if (!MO.isReg() || !MO.isUse() || !MO.isKill() || MO.isUndef())
Lang Hames87e3bca2009-05-06 02:36:21 +0000465 continue;
466 unsigned Reg = MO.getReg();
467 if (TargetRegisterInfo::isVirtualRegister(Reg))
468 continue;
469 if (KillRegs)
470 KillRegs->push_back(Reg);
471 assert(Reg < KillOps.size());
472 if (KillOps[Reg] == &MO) {
Lang Hames87e3bca2009-05-06 02:36:21 +0000473 KillOps[Reg] = NULL;
Evan Cheng427a6b62009-05-15 06:48:19 +0000474 RegKills.reset(Reg);
475 for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
476 if (RegKills[*SR]) {
477 KillOps[*SR] = NULL;
478 RegKills.reset(*SR);
479 }
480 }
Lang Hames87e3bca2009-05-06 02:36:21 +0000481 }
482 }
483}
484
485/// InvalidateRegDef - If the def operand of the specified def MI is now dead
Evan Cheng8fdd84c2009-11-14 02:09:09 +0000486/// (since its spill instruction is removed), mark it isDead. Also checks if
Lang Hames87e3bca2009-05-06 02:36:21 +0000487/// the def MI has other definition operands that are not dead. Returns it by
488/// reference.
489static bool InvalidateRegDef(MachineBasicBlock::iterator I,
490 MachineInstr &NewDef, unsigned Reg,
Evan Cheng8fdd84c2009-11-14 02:09:09 +0000491 bool &HasLiveDef,
492 const TargetRegisterInfo *TRI) {
Lang Hames87e3bca2009-05-06 02:36:21 +0000493 // Due to remat, it's possible this reg isn't being reused. That is,
494 // the def of this reg (by prev MI) is now dead.
495 MachineInstr *DefMI = I;
496 MachineOperand *DefOp = NULL;
497 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
498 MachineOperand &MO = DefMI->getOperand(i);
Evan Cheng8fdd84c2009-11-14 02:09:09 +0000499 if (!MO.isReg() || !MO.isDef() || !MO.isKill() || MO.isUndef())
Evan Cheng4784f1f2009-06-30 08:49:04 +0000500 continue;
501 if (MO.getReg() == Reg)
502 DefOp = &MO;
503 else if (!MO.isDead())
504 HasLiveDef = true;
Lang Hames87e3bca2009-05-06 02:36:21 +0000505 }
506 if (!DefOp)
507 return false;
508
509 bool FoundUse = false, Done = false;
510 MachineBasicBlock::iterator E = &NewDef;
511 ++I; ++E;
512 for (; !Done && I != E; ++I) {
513 MachineInstr *NMI = I;
514 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
515 MachineOperand &MO = NMI->getOperand(j);
Evan Cheng8fdd84c2009-11-14 02:09:09 +0000516 if (!MO.isReg() || MO.getReg() == 0 ||
517 (MO.getReg() != Reg && !TRI->isSubRegister(Reg, MO.getReg())))
Lang Hames87e3bca2009-05-06 02:36:21 +0000518 continue;
519 if (MO.isUse())
520 FoundUse = true;
521 Done = true; // Stop after scanning all the operands of this MI.
522 }
523 }
524 if (!FoundUse) {
525 // Def is dead!
526 DefOp->setIsDead();
527 return true;
528 }
529 return false;
530}
531
532/// UpdateKills - Track and update kill info. If a MI reads a register that is
533/// marked kill, then it must be due to register reuse. Transfer the kill info
534/// over.
Evan Cheng427a6b62009-05-15 06:48:19 +0000535static void UpdateKills(MachineInstr &MI, const TargetRegisterInfo* TRI,
536 BitVector &RegKills,
537 std::vector<MachineOperand*> &KillOps) {
Lang Hames87e3bca2009-05-06 02:36:21 +0000538 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
539 MachineOperand &MO = MI.getOperand(i);
Evan Cheng4784f1f2009-06-30 08:49:04 +0000540 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
Lang Hames87e3bca2009-05-06 02:36:21 +0000541 continue;
542 unsigned Reg = MO.getReg();
543 if (Reg == 0)
544 continue;
545
546 if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) {
547 // That can't be right. Register is killed but not re-defined and it's
548 // being reused. Let's fix that.
549 KillOps[Reg]->setIsKill(false);
Evan Cheng2c48fe62009-06-03 09:00:27 +0000550 // KillOps[Reg] might be a def of a super-register.
551 unsigned KReg = KillOps[Reg]->getReg();
552 KillOps[KReg] = NULL;
553 RegKills.reset(KReg);
554
555 // Must be a def of a super-register. Its other sub-regsters are no
556 // longer killed as well.
557 for (const unsigned *SR = TRI->getSubRegisters(KReg); *SR; ++SR) {
558 KillOps[*SR] = NULL;
559 RegKills.reset(*SR);
560 }
Evan Cheng8fdd84c2009-11-14 02:09:09 +0000561 } else {
562 // Check for subreg kills as well.
563 // d4 =
564 // store d4, fi#0
565 // ...
566 // = s8<kill>
567 // ...
568 // = d4 <avoiding reload>
569 for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
570 unsigned SReg = *SR;
571 if (RegKills[SReg] && KillOps[SReg]->getParent() != &MI) {
572 KillOps[SReg]->setIsKill(false);
573 unsigned KReg = KillOps[SReg]->getReg();
574 KillOps[KReg] = NULL;
575 RegKills.reset(KReg);
Evan Cheng2c48fe62009-06-03 09:00:27 +0000576
Evan Cheng8fdd84c2009-11-14 02:09:09 +0000577 for (const unsigned *SSR = TRI->getSubRegisters(KReg); *SSR; ++SSR) {
578 KillOps[*SSR] = NULL;
579 RegKills.reset(*SSR);
580 }
581 }
582 }
Lang Hames87e3bca2009-05-06 02:36:21 +0000583 }
Evan Cheng8fdd84c2009-11-14 02:09:09 +0000584
Lang Hames87e3bca2009-05-06 02:36:21 +0000585 if (MO.isKill()) {
586 RegKills.set(Reg);
587 KillOps[Reg] = &MO;
Evan Cheng427a6b62009-05-15 06:48:19 +0000588 for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
589 RegKills.set(*SR);
590 KillOps[*SR] = &MO;
591 }
Lang Hames87e3bca2009-05-06 02:36:21 +0000592 }
593 }
594
595 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
596 const MachineOperand &MO = MI.getOperand(i);
597 if (!MO.isReg() || !MO.isDef())
598 continue;
599 unsigned Reg = MO.getReg();
600 RegKills.reset(Reg);
601 KillOps[Reg] = NULL;
602 // It also defines (or partially define) aliases.
Evan Cheng427a6b62009-05-15 06:48:19 +0000603 for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
604 RegKills.reset(*SR);
605 KillOps[*SR] = NULL;
Lang Hames87e3bca2009-05-06 02:36:21 +0000606 }
Evan Cheng1f6a3c82009-11-13 23:16:41 +0000607 for (const unsigned *SR = TRI->getSuperRegisters(Reg); *SR; ++SR) {
608 RegKills.reset(*SR);
609 KillOps[*SR] = NULL;
610 }
Lang Hames87e3bca2009-05-06 02:36:21 +0000611 }
612}
613
614/// ReMaterialize - Re-materialize definition for Reg targetting DestReg.
615///
616static void ReMaterialize(MachineBasicBlock &MBB,
617 MachineBasicBlock::iterator &MII,
618 unsigned DestReg, unsigned Reg,
619 const TargetInstrInfo *TII,
620 const TargetRegisterInfo *TRI,
621 VirtRegMap &VRM) {
Evan Cheng5f159922009-07-16 20:15:00 +0000622 MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
Daniel Dunbar24cd3c42009-07-16 22:08:25 +0000623#ifndef NDEBUG
Evan Cheng5f159922009-07-16 20:15:00 +0000624 const TargetInstrDesc &TID = ReMatDefMI->getDesc();
Evan Chengc1b46f92009-07-17 00:32:06 +0000625 assert(TID.getNumDefs() == 1 &&
Evan Cheng5f159922009-07-16 20:15:00 +0000626 "Don't know how to remat instructions that define > 1 values!");
627#endif
628 TII->reMaterialize(MBB, MII, DestReg,
629 ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI);
Lang Hames87e3bca2009-05-06 02:36:21 +0000630 MachineInstr *NewMI = prior(MII);
631 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
632 MachineOperand &MO = NewMI->getOperand(i);
633 if (!MO.isReg() || MO.getReg() == 0)
634 continue;
635 unsigned VirtReg = MO.getReg();
636 if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
637 continue;
638 assert(MO.isUse());
639 unsigned SubIdx = MO.getSubReg();
640 unsigned Phys = VRM.getPhys(VirtReg);
Evan Cheng427c3ba2009-10-25 07:51:47 +0000641 assert(Phys && "Virtual register is not assigned a register?");
Lang Hames87e3bca2009-05-06 02:36:21 +0000642 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
643 MO.setReg(RReg);
644 MO.setSubReg(0);
645 }
646 ++NumReMats;
647}
648
649/// findSuperReg - Find the SubReg's super-register of given register class
650/// where its SubIdx sub-register is SubReg.
651static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
652 unsigned SubIdx, const TargetRegisterInfo *TRI) {
653 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
654 I != E; ++I) {
655 unsigned Reg = *I;
656 if (TRI->getSubReg(Reg, SubIdx) == SubReg)
657 return Reg;
658 }
659 return 0;
660}
661
662// ******************************** //
663// Available Spills Implementation //
664// ******************************** //
665
666/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
667/// stackslot register. The register is still available but is no longer
668/// allowed to be modifed.
669void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
670 std::multimap<unsigned, int>::iterator I =
671 PhysRegsAvailable.lower_bound(PhysReg);
672 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
673 int SlotOrReMat = I->second;
674 I++;
675 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
676 "Bidirectional map mismatch!");
677 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
Chris Lattner6456d382009-08-23 03:20:44 +0000678 DEBUG(errs() << "PhysReg " << TRI->getName(PhysReg)
679 << " copied, it is available for use but can no longer be modified\n");
Lang Hames87e3bca2009-05-06 02:36:21 +0000680 }
681}
682
683/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
684/// stackslot register and its aliases. The register and its aliases may
685/// still available but is no longer allowed to be modifed.
686void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
687 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
688 disallowClobberPhysRegOnly(*AS);
689 disallowClobberPhysRegOnly(PhysReg);
690}
691
692/// ClobberPhysRegOnly - This is called when the specified physreg changes
693/// value. We use this to invalidate any info about stuff we thing lives in it.
694void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
695 std::multimap<unsigned, int>::iterator I =
696 PhysRegsAvailable.lower_bound(PhysReg);
697 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
698 int SlotOrReMat = I->second;
699 PhysRegsAvailable.erase(I++);
700 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
701 "Bidirectional map mismatch!");
702 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
Chris Lattner6456d382009-08-23 03:20:44 +0000703 DEBUG(errs() << "PhysReg " << TRI->getName(PhysReg)
704 << " clobbered, invalidating ");
Lang Hames87e3bca2009-05-06 02:36:21 +0000705 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
Chris Lattner6456d382009-08-23 03:20:44 +0000706 DEBUG(errs() << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 <<"\n");
Lang Hames87e3bca2009-05-06 02:36:21 +0000707 else
Chris Lattner6456d382009-08-23 03:20:44 +0000708 DEBUG(errs() << "SS#" << SlotOrReMat << "\n");
Lang Hames87e3bca2009-05-06 02:36:21 +0000709 }
710}
711
712/// ClobberPhysReg - This is called when the specified physreg changes
713/// value. We use this to invalidate any info about stuff we thing lives in
714/// it and any of its aliases.
715void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
716 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
717 ClobberPhysRegOnly(*AS);
718 ClobberPhysRegOnly(PhysReg);
719}
720
721/// AddAvailableRegsToLiveIn - Availability information is being kept coming
722/// into the specified MBB. Add available physical registers as potential
723/// live-in's. If they are reused in the MBB, they will be added to the
724/// live-in set to make register scavenger and post-allocation scheduler.
725void AvailableSpills::AddAvailableRegsToLiveIn(MachineBasicBlock &MBB,
726 BitVector &RegKills,
727 std::vector<MachineOperand*> &KillOps) {
728 std::set<unsigned> NotAvailable;
729 for (std::multimap<unsigned, int>::iterator
730 I = PhysRegsAvailable.begin(), E = PhysRegsAvailable.end();
731 I != E; ++I) {
732 unsigned Reg = I->first;
733 const TargetRegisterClass* RC = TRI->getPhysicalRegisterRegClass(Reg);
734 // FIXME: A temporary workaround. We can't reuse available value if it's
735 // not safe to move the def of the virtual register's class. e.g.
736 // X86::RFP* register classes. Do not add it as a live-in.
737 if (!TII->isSafeToMoveRegClassDefs(RC))
738 // This is no longer available.
739 NotAvailable.insert(Reg);
740 else {
741 MBB.addLiveIn(Reg);
Evan Cheng427a6b62009-05-15 06:48:19 +0000742 InvalidateKill(Reg, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +0000743 }
744
745 // Skip over the same register.
746 std::multimap<unsigned, int>::iterator NI = next(I);
747 while (NI != E && NI->first == Reg) {
748 ++I;
749 ++NI;
750 }
751 }
752
753 for (std::set<unsigned>::iterator I = NotAvailable.begin(),
754 E = NotAvailable.end(); I != E; ++I) {
755 ClobberPhysReg(*I);
756 for (const unsigned *SubRegs = TRI->getSubRegisters(*I);
757 *SubRegs; ++SubRegs)
758 ClobberPhysReg(*SubRegs);
759 }
760}
761
762/// ModifyStackSlotOrReMat - This method is called when the value in a stack
763/// slot changes. This removes information about which register the previous
764/// value for this slot lives in (as the previous value is dead now).
765void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
766 std::map<int, unsigned>::iterator It =
767 SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
768 if (It == SpillSlotsOrReMatsAvailable.end()) return;
769 unsigned Reg = It->second >> 1;
770 SpillSlotsOrReMatsAvailable.erase(It);
771
772 // This register may hold the value of multiple stack slots, only remove this
773 // stack slot from the set of values the register contains.
774 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
775 for (; ; ++I) {
776 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
777 "Map inverse broken!");
778 if (I->second == SlotOrReMat) break;
779 }
780 PhysRegsAvailable.erase(I);
781}
782
783// ************************** //
784// Reuse Info Implementation //
785// ************************** //
786
787/// GetRegForReload - We are about to emit a reload into PhysReg. If there
788/// is some other operand that is using the specified register, either pick
789/// a new register to use, or evict the previous reload and use this reg.
Evan Cheng5d885022009-07-21 09:15:00 +0000790unsigned ReuseInfo::GetRegForReload(const TargetRegisterClass *RC,
791 unsigned PhysReg,
792 MachineFunction &MF,
793 MachineInstr *MI, AvailableSpills &Spills,
Lang Hames87e3bca2009-05-06 02:36:21 +0000794 std::vector<MachineInstr*> &MaybeDeadStores,
795 SmallSet<unsigned, 8> &Rejected,
796 BitVector &RegKills,
797 std::vector<MachineOperand*> &KillOps,
798 VirtRegMap &VRM) {
Evan Cheng5d885022009-07-21 09:15:00 +0000799 const TargetInstrInfo* TII = MF.getTarget().getInstrInfo();
800 const TargetRegisterInfo *TRI = Spills.getRegInfo();
Lang Hames87e3bca2009-05-06 02:36:21 +0000801
802 if (Reuses.empty()) return PhysReg; // This is most often empty.
803
804 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
805 ReusedOp &Op = Reuses[ro];
806 // If we find some other reuse that was supposed to use this register
807 // exactly for its reload, we can change this reload to use ITS reload
808 // register. That is, unless its reload register has already been
809 // considered and subsequently rejected because it has also been reused
810 // by another operand.
811 if (Op.PhysRegReused == PhysReg &&
Evan Cheng5d885022009-07-21 09:15:00 +0000812 Rejected.count(Op.AssignedPhysReg) == 0 &&
813 RC->contains(Op.AssignedPhysReg)) {
Lang Hames87e3bca2009-05-06 02:36:21 +0000814 // Yup, use the reload register that we didn't use before.
815 unsigned NewReg = Op.AssignedPhysReg;
816 Rejected.insert(PhysReg);
Evan Cheng5d885022009-07-21 09:15:00 +0000817 return GetRegForReload(RC, NewReg, MF, MI, Spills, MaybeDeadStores, Rejected,
Lang Hames87e3bca2009-05-06 02:36:21 +0000818 RegKills, KillOps, VRM);
819 } else {
820 // Otherwise, we might also have a problem if a previously reused
Evan Cheng5d885022009-07-21 09:15:00 +0000821 // value aliases the new register. If so, codegen the previous reload
Lang Hames87e3bca2009-05-06 02:36:21 +0000822 // and use this one.
823 unsigned PRRU = Op.PhysRegReused;
Lang Hames3f2f3f52009-09-03 02:52:02 +0000824 if (TRI->regsOverlap(PRRU, PhysReg)) {
Lang Hames87e3bca2009-05-06 02:36:21 +0000825 // Okay, we found out that an alias of a reused register
826 // was used. This isn't good because it means we have
827 // to undo a previous reuse.
828 MachineBasicBlock *MBB = MI->getParent();
829 const TargetRegisterClass *AliasRC =
830 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg);
831
832 // Copy Op out of the vector and remove it, we're going to insert an
833 // explicit load for it.
834 ReusedOp NewOp = Op;
835 Reuses.erase(Reuses.begin()+ro);
836
Jakob Stoklund Olesen46ff9692009-08-23 13:01:45 +0000837 // MI may be using only a sub-register of PhysRegUsed.
838 unsigned RealPhysRegUsed = MI->getOperand(NewOp.Operand).getReg();
839 unsigned SubIdx = 0;
840 assert(TargetRegisterInfo::isPhysicalRegister(RealPhysRegUsed) &&
841 "A reuse cannot be a virtual register");
842 if (PRRU != RealPhysRegUsed) {
843 // What was the sub-register index?
844 unsigned SubReg;
845 for (SubIdx = 1; (SubReg = TRI->getSubReg(PRRU, SubIdx)); SubIdx++)
846 if (SubReg == RealPhysRegUsed)
847 break;
848 assert(SubReg == RealPhysRegUsed &&
849 "Operand physreg is not a sub-register of PhysRegUsed");
850 }
851
Lang Hames87e3bca2009-05-06 02:36:21 +0000852 // Ok, we're going to try to reload the assigned physreg into the
853 // slot that we were supposed to in the first place. However, that
854 // register could hold a reuse. Check to see if it conflicts or
855 // would prefer us to use a different register.
Evan Cheng5d885022009-07-21 09:15:00 +0000856 unsigned NewPhysReg = GetRegForReload(RC, NewOp.AssignedPhysReg,
857 MF, MI, Spills, MaybeDeadStores,
858 Rejected, RegKills, KillOps, VRM);
David Greene2d4e6d32009-07-28 16:49:24 +0000859
860 bool DoReMat = NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT;
861 int SSorRMId = DoReMat
862 ? VRM.getReMatId(NewOp.VirtReg) : NewOp.StackSlotOrReMat;
863
864 // Back-schedule reloads and remats.
865 MachineBasicBlock::iterator InsertLoc =
866 ComputeReloadLoc(MI, MBB->begin(), PhysReg, TRI,
867 DoReMat, SSorRMId, TII, MF);
868
869 if (DoReMat) {
870 ReMaterialize(*MBB, InsertLoc, NewPhysReg, NewOp.VirtReg, TII,
871 TRI, VRM);
872 } else {
873 TII->loadRegFromStackSlot(*MBB, InsertLoc, NewPhysReg,
Lang Hames87e3bca2009-05-06 02:36:21 +0000874 NewOp.StackSlotOrReMat, AliasRC);
David Greene2d4e6d32009-07-28 16:49:24 +0000875 MachineInstr *LoadMI = prior(InsertLoc);
Lang Hames87e3bca2009-05-06 02:36:21 +0000876 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI);
877 // Any stores to this stack slot are not dead anymore.
878 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
879 ++NumLoads;
880 }
881 Spills.ClobberPhysReg(NewPhysReg);
882 Spills.ClobberPhysReg(NewOp.PhysRegReused);
883
Evan Cheng427c3ba2009-10-25 07:51:47 +0000884 unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) :NewPhysReg;
Lang Hames87e3bca2009-05-06 02:36:21 +0000885 MI->getOperand(NewOp.Operand).setReg(RReg);
886 MI->getOperand(NewOp.Operand).setSubReg(0);
887
888 Spills.addAvailable(NewOp.StackSlotOrReMat, NewPhysReg);
David Greene2d4e6d32009-07-28 16:49:24 +0000889 UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
Chris Lattner6456d382009-08-23 03:20:44 +0000890 DEBUG(errs() << '\t' << *prior(InsertLoc));
Lang Hames87e3bca2009-05-06 02:36:21 +0000891
Chris Lattner6456d382009-08-23 03:20:44 +0000892 DEBUG(errs() << "Reuse undone!\n");
Lang Hames87e3bca2009-05-06 02:36:21 +0000893 --NumReused;
894
895 // Finally, PhysReg is now available, go ahead and use it.
896 return PhysReg;
897 }
898 }
899 }
900 return PhysReg;
901}
902
903// ************************************************************************ //
904
905/// FoldsStackSlotModRef - Return true if the specified MI folds the specified
906/// stack slot mod/ref. It also checks if it's possible to unfold the
907/// instruction by having it define a specified physical register instead.
908static bool FoldsStackSlotModRef(MachineInstr &MI, int SS, unsigned PhysReg,
909 const TargetInstrInfo *TII,
910 const TargetRegisterInfo *TRI,
911 VirtRegMap &VRM) {
912 if (VRM.hasEmergencySpills(&MI) || VRM.isSpillPt(&MI))
913 return false;
914
915 bool Found = false;
916 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
917 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
918 unsigned VirtReg = I->second.first;
919 VirtRegMap::ModRef MR = I->second.second;
920 if (MR & VirtRegMap::isModRef)
921 if (VRM.getStackSlot(VirtReg) == SS) {
922 Found= TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), true, true) != 0;
923 break;
924 }
925 }
926 if (!Found)
927 return false;
928
929 // Does the instruction uses a register that overlaps the scratch register?
930 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
931 MachineOperand &MO = MI.getOperand(i);
932 if (!MO.isReg() || MO.getReg() == 0)
933 continue;
934 unsigned Reg = MO.getReg();
935 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
936 if (!VRM.hasPhys(Reg))
937 continue;
938 Reg = VRM.getPhys(Reg);
939 }
940 if (TRI->regsOverlap(PhysReg, Reg))
941 return false;
942 }
943 return true;
944}
945
946/// FindFreeRegister - Find a free register of a given register class by looking
947/// at (at most) the last two machine instructions.
948static unsigned FindFreeRegister(MachineBasicBlock::iterator MII,
949 MachineBasicBlock &MBB,
950 const TargetRegisterClass *RC,
951 const TargetRegisterInfo *TRI,
952 BitVector &AllocatableRegs) {
953 BitVector Defs(TRI->getNumRegs());
954 BitVector Uses(TRI->getNumRegs());
955 SmallVector<unsigned, 4> LocalUses;
956 SmallVector<unsigned, 4> Kills;
957
958 // Take a look at 2 instructions at most.
959 for (unsigned Count = 0; Count < 2; ++Count) {
960 if (MII == MBB.begin())
961 break;
962 MachineInstr *PrevMI = prior(MII);
963 for (unsigned i = 0, e = PrevMI->getNumOperands(); i != e; ++i) {
964 MachineOperand &MO = PrevMI->getOperand(i);
965 if (!MO.isReg() || MO.getReg() == 0)
966 continue;
967 unsigned Reg = MO.getReg();
968 if (MO.isDef()) {
969 Defs.set(Reg);
970 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
971 Defs.set(*AS);
972 } else {
973 LocalUses.push_back(Reg);
974 if (MO.isKill() && AllocatableRegs[Reg])
975 Kills.push_back(Reg);
976 }
977 }
978
979 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
980 unsigned Kill = Kills[i];
981 if (!Defs[Kill] && !Uses[Kill] &&
982 TRI->getPhysicalRegisterRegClass(Kill) == RC)
983 return Kill;
984 }
985 for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
986 unsigned Reg = LocalUses[i];
987 Uses.set(Reg);
988 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
989 Uses.set(*AS);
990 }
991
992 MII = PrevMI;
993 }
994
995 return 0;
996}
997
998static
999void AssignPhysToVirtReg(MachineInstr *MI, unsigned VirtReg, unsigned PhysReg) {
1000 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1001 MachineOperand &MO = MI->getOperand(i);
1002 if (MO.isReg() && MO.getReg() == VirtReg)
1003 MO.setReg(PhysReg);
1004 }
1005}
1006
Evan Chengeca24fb2009-05-12 23:07:00 +00001007namespace {
1008 struct RefSorter {
1009 bool operator()(const std::pair<MachineInstr*, int> &A,
1010 const std::pair<MachineInstr*, int> &B) {
1011 return A.second < B.second;
1012 }
1013 };
1014}
Lang Hames87e3bca2009-05-06 02:36:21 +00001015
1016// ***************************** //
1017// Local Spiller Implementation //
1018// ***************************** //
1019
Dan Gohman7db949d2009-08-07 01:32:21 +00001020namespace {
1021
Nick Lewycky6726b6d2009-10-25 06:33:48 +00001022class LocalRewriter : public VirtRegRewriter {
Lang Hames87e3bca2009-05-06 02:36:21 +00001023 MachineRegisterInfo *RegInfo;
1024 const TargetRegisterInfo *TRI;
1025 const TargetInstrInfo *TII;
1026 BitVector AllocatableRegs;
1027 DenseMap<MachineInstr*, unsigned> DistanceMap;
1028public:
1029
1030 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM,
1031 LiveIntervals* LIs) {
1032 RegInfo = &MF.getRegInfo();
1033 TRI = MF.getTarget().getRegisterInfo();
1034 TII = MF.getTarget().getInstrInfo();
1035 AllocatableRegs = TRI->getAllocatableSet(MF);
Daniel Dunbarce63ffb2009-07-25 00:23:56 +00001036 DEBUG(errs() << "\n**** Local spiller rewriting function '"
1037 << MF.getFunction()->getName() << "':\n");
Chris Lattner6456d382009-08-23 03:20:44 +00001038 DEBUG(errs() << "**** Machine Instrs (NOTE! Does not include spills and"
1039 " reloads!) ****\n");
Lang Hames87e3bca2009-05-06 02:36:21 +00001040 DEBUG(MF.dump());
1041
1042 // Spills - Keep track of which spilled values are available in physregs
1043 // so that we can choose to reuse the physregs instead of emitting
1044 // reloads. This is usually refreshed per basic block.
1045 AvailableSpills Spills(TRI, TII);
1046
1047 // Keep track of kill information.
1048 BitVector RegKills(TRI->getNumRegs());
1049 std::vector<MachineOperand*> KillOps;
1050 KillOps.resize(TRI->getNumRegs(), NULL);
1051
1052 // SingleEntrySuccs - Successor blocks which have a single predecessor.
1053 SmallVector<MachineBasicBlock*, 4> SinglePredSuccs;
1054 SmallPtrSet<MachineBasicBlock*,16> EarlyVisited;
1055
1056 // Traverse the basic blocks depth first.
1057 MachineBasicBlock *Entry = MF.begin();
1058 SmallPtrSet<MachineBasicBlock*,16> Visited;
1059 for (df_ext_iterator<MachineBasicBlock*,
1060 SmallPtrSet<MachineBasicBlock*,16> >
1061 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
1062 DFI != E; ++DFI) {
1063 MachineBasicBlock *MBB = *DFI;
1064 if (!EarlyVisited.count(MBB))
1065 RewriteMBB(*MBB, VRM, LIs, Spills, RegKills, KillOps);
1066
1067 // If this MBB is the only predecessor of a successor. Keep the
1068 // availability information and visit it next.
1069 do {
1070 // Keep visiting single predecessor successor as long as possible.
1071 SinglePredSuccs.clear();
1072 findSinglePredSuccessor(MBB, SinglePredSuccs);
1073 if (SinglePredSuccs.empty())
1074 MBB = 0;
1075 else {
1076 // FIXME: More than one successors, each of which has MBB has
1077 // the only predecessor.
1078 MBB = SinglePredSuccs[0];
1079 if (!Visited.count(MBB) && EarlyVisited.insert(MBB)) {
1080 Spills.AddAvailableRegsToLiveIn(*MBB, RegKills, KillOps);
1081 RewriteMBB(*MBB, VRM, LIs, Spills, RegKills, KillOps);
1082 }
1083 }
1084 } while (MBB);
1085
1086 // Clear the availability info.
1087 Spills.clear();
1088 }
1089
Chris Lattner6456d382009-08-23 03:20:44 +00001090 DEBUG(errs() << "**** Post Machine Instrs ****\n");
Lang Hames87e3bca2009-05-06 02:36:21 +00001091 DEBUG(MF.dump());
1092
1093 // Mark unused spill slots.
1094 MachineFrameInfo *MFI = MF.getFrameInfo();
1095 int SS = VRM.getLowSpillSlot();
1096 if (SS != VirtRegMap::NO_STACK_SLOT)
1097 for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS)
1098 if (!VRM.isSpillSlotUsed(SS)) {
1099 MFI->RemoveStackObject(SS);
1100 ++NumDSS;
1101 }
1102
1103 return true;
1104 }
1105
1106private:
1107
1108 /// OptimizeByUnfold2 - Unfold a series of load / store folding instructions if
1109 /// a scratch register is available.
1110 /// xorq %r12<kill>, %r13
1111 /// addq %rax, -184(%rbp)
1112 /// addq %r13, -184(%rbp)
1113 /// ==>
1114 /// xorq %r12<kill>, %r13
1115 /// movq -184(%rbp), %r12
1116 /// addq %rax, %r12
1117 /// addq %r13, %r12
1118 /// movq %r12, -184(%rbp)
1119 bool OptimizeByUnfold2(unsigned VirtReg, int SS,
1120 MachineBasicBlock &MBB,
1121 MachineBasicBlock::iterator &MII,
1122 std::vector<MachineInstr*> &MaybeDeadStores,
1123 AvailableSpills &Spills,
1124 BitVector &RegKills,
1125 std::vector<MachineOperand*> &KillOps,
1126 VirtRegMap &VRM) {
1127
1128 MachineBasicBlock::iterator NextMII = next(MII);
1129 if (NextMII == MBB.end())
1130 return false;
1131
1132 if (TII->getOpcodeAfterMemoryUnfold(MII->getOpcode(), true, true) == 0)
1133 return false;
1134
1135 // Now let's see if the last couple of instructions happens to have freed up
1136 // a register.
1137 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1138 unsigned PhysReg = FindFreeRegister(MII, MBB, RC, TRI, AllocatableRegs);
1139 if (!PhysReg)
1140 return false;
1141
1142 MachineFunction &MF = *MBB.getParent();
1143 TRI = MF.getTarget().getRegisterInfo();
1144 MachineInstr &MI = *MII;
1145 if (!FoldsStackSlotModRef(MI, SS, PhysReg, TII, TRI, VRM))
1146 return false;
1147
1148 // If the next instruction also folds the same SS modref and can be unfoled,
1149 // then it's worthwhile to issue a load from SS into the free register and
1150 // then unfold these instructions.
1151 if (!FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM))
1152 return false;
1153
David Greene2d4e6d32009-07-28 16:49:24 +00001154 // Back-schedule reloads and remats.
Duncan Sandsb7c5bdf2009-09-06 08:33:48 +00001155 ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, false, SS, TII, MF);
David Greene2d4e6d32009-07-28 16:49:24 +00001156
Lang Hames87e3bca2009-05-06 02:36:21 +00001157 // Load from SS to the spare physical register.
1158 TII->loadRegFromStackSlot(MBB, MII, PhysReg, SS, RC);
1159 // This invalidates Phys.
1160 Spills.ClobberPhysReg(PhysReg);
1161 // Remember it's available.
1162 Spills.addAvailable(SS, PhysReg);
1163 MaybeDeadStores[SS] = NULL;
1164
1165 // Unfold current MI.
1166 SmallVector<MachineInstr*, 4> NewMIs;
1167 if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs))
Torok Edwinc23197a2009-07-14 16:55:14 +00001168 llvm_unreachable("Unable unfold the load / store folding instruction!");
Lang Hames87e3bca2009-05-06 02:36:21 +00001169 assert(NewMIs.size() == 1);
1170 AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
1171 VRM.transferRestorePts(&MI, NewMIs[0]);
1172 MII = MBB.insert(MII, NewMIs[0]);
Evan Cheng427a6b62009-05-15 06:48:19 +00001173 InvalidateKills(MI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00001174 VRM.RemoveMachineInstrFromMaps(&MI);
1175 MBB.erase(&MI);
1176 ++NumModRefUnfold;
1177
1178 // Unfold next instructions that fold the same SS.
1179 do {
1180 MachineInstr &NextMI = *NextMII;
1181 NextMII = next(NextMII);
1182 NewMIs.clear();
1183 if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs))
Torok Edwinc23197a2009-07-14 16:55:14 +00001184 llvm_unreachable("Unable unfold the load / store folding instruction!");
Lang Hames87e3bca2009-05-06 02:36:21 +00001185 assert(NewMIs.size() == 1);
1186 AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
1187 VRM.transferRestorePts(&NextMI, NewMIs[0]);
1188 MBB.insert(NextMII, NewMIs[0]);
Evan Cheng427a6b62009-05-15 06:48:19 +00001189 InvalidateKills(NextMI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00001190 VRM.RemoveMachineInstrFromMaps(&NextMI);
1191 MBB.erase(&NextMI);
1192 ++NumModRefUnfold;
Evan Cheng2c48fe62009-06-03 09:00:27 +00001193 if (NextMII == MBB.end())
1194 break;
Lang Hames87e3bca2009-05-06 02:36:21 +00001195 } while (FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM));
1196
1197 // Store the value back into SS.
1198 TII->storeRegToStackSlot(MBB, NextMII, PhysReg, true, SS, RC);
1199 MachineInstr *StoreMI = prior(NextMII);
1200 VRM.addSpillSlotUse(SS, StoreMI);
1201 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1202
1203 return true;
1204 }
1205
1206 /// OptimizeByUnfold - Turn a store folding instruction into a load folding
1207 /// instruction. e.g.
1208 /// xorl %edi, %eax
1209 /// movl %eax, -32(%ebp)
1210 /// movl -36(%ebp), %eax
1211 /// orl %eax, -32(%ebp)
1212 /// ==>
1213 /// xorl %edi, %eax
1214 /// orl -36(%ebp), %eax
1215 /// mov %eax, -32(%ebp)
1216 /// This enables unfolding optimization for a subsequent instruction which will
1217 /// also eliminate the newly introduced store instruction.
1218 bool OptimizeByUnfold(MachineBasicBlock &MBB,
1219 MachineBasicBlock::iterator &MII,
1220 std::vector<MachineInstr*> &MaybeDeadStores,
1221 AvailableSpills &Spills,
1222 BitVector &RegKills,
1223 std::vector<MachineOperand*> &KillOps,
1224 VirtRegMap &VRM) {
1225 MachineFunction &MF = *MBB.getParent();
1226 MachineInstr &MI = *MII;
1227 unsigned UnfoldedOpc = 0;
1228 unsigned UnfoldPR = 0;
1229 unsigned UnfoldVR = 0;
1230 int FoldedSS = VirtRegMap::NO_STACK_SLOT;
1231 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
1232 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
1233 // Only transform a MI that folds a single register.
1234 if (UnfoldedOpc)
1235 return false;
1236 UnfoldVR = I->second.first;
1237 VirtRegMap::ModRef MR = I->second.second;
1238 // MI2VirtMap be can updated which invalidate the iterator.
1239 // Increment the iterator first.
1240 ++I;
1241 if (VRM.isAssignedReg(UnfoldVR))
1242 continue;
1243 // If this reference is not a use, any previous store is now dead.
1244 // Otherwise, the store to this stack slot is not dead anymore.
1245 FoldedSS = VRM.getStackSlot(UnfoldVR);
1246 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
1247 if (DeadStore && (MR & VirtRegMap::isModRef)) {
1248 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
1249 if (!PhysReg || !DeadStore->readsRegister(PhysReg))
1250 continue;
1251 UnfoldPR = PhysReg;
1252 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1253 false, true);
1254 }
1255 }
1256
1257 if (!UnfoldedOpc) {
1258 if (!UnfoldVR)
1259 return false;
1260
1261 // Look for other unfolding opportunities.
1262 return OptimizeByUnfold2(UnfoldVR, FoldedSS, MBB, MII,
1263 MaybeDeadStores, Spills, RegKills, KillOps, VRM);
1264 }
1265
1266 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1267 MachineOperand &MO = MI.getOperand(i);
1268 if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse())
1269 continue;
1270 unsigned VirtReg = MO.getReg();
1271 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
1272 continue;
1273 if (VRM.isAssignedReg(VirtReg)) {
1274 unsigned PhysReg = VRM.getPhys(VirtReg);
1275 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
1276 return false;
1277 } else if (VRM.isReMaterialized(VirtReg))
1278 continue;
1279 int SS = VRM.getStackSlot(VirtReg);
1280 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1281 if (PhysReg) {
1282 if (TRI->regsOverlap(PhysReg, UnfoldPR))
1283 return false;
1284 continue;
1285 }
1286 if (VRM.hasPhys(VirtReg)) {
1287 PhysReg = VRM.getPhys(VirtReg);
1288 if (!TRI->regsOverlap(PhysReg, UnfoldPR))
1289 continue;
1290 }
1291
1292 // Ok, we'll need to reload the value into a register which makes
1293 // it impossible to perform the store unfolding optimization later.
1294 // Let's see if it is possible to fold the load if the store is
1295 // unfolded. This allows us to perform the store unfolding
1296 // optimization.
1297 SmallVector<MachineInstr*, 4> NewMIs;
1298 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
1299 assert(NewMIs.size() == 1);
1300 MachineInstr *NewMI = NewMIs.back();
1301 NewMIs.clear();
1302 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false);
1303 assert(Idx != -1);
1304 SmallVector<unsigned, 1> Ops;
1305 Ops.push_back(Idx);
1306 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS);
1307 if (FoldedMI) {
1308 VRM.addSpillSlotUse(SS, FoldedMI);
1309 if (!VRM.hasPhys(UnfoldVR))
1310 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
1311 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
1312 MII = MBB.insert(MII, FoldedMI);
Evan Cheng427a6b62009-05-15 06:48:19 +00001313 InvalidateKills(MI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00001314 VRM.RemoveMachineInstrFromMaps(&MI);
1315 MBB.erase(&MI);
1316 MF.DeleteMachineInstr(NewMI);
1317 return true;
1318 }
1319 MF.DeleteMachineInstr(NewMI);
1320 }
1321 }
1322
1323 return false;
1324 }
1325
Evan Cheng261ce1d2009-07-10 19:15:51 +00001326 /// CommuteChangesDestination - We are looking for r0 = op r1, r2 and
1327 /// where SrcReg is r1 and it is tied to r0. Return true if after
1328 /// commuting this instruction it will be r0 = op r2, r1.
1329 static bool CommuteChangesDestination(MachineInstr *DefMI,
1330 const TargetInstrDesc &TID,
1331 unsigned SrcReg,
1332 const TargetInstrInfo *TII,
1333 unsigned &DstIdx) {
1334 if (TID.getNumDefs() != 1 && TID.getNumOperands() != 3)
1335 return false;
1336 if (!DefMI->getOperand(1).isReg() ||
1337 DefMI->getOperand(1).getReg() != SrcReg)
1338 return false;
1339 unsigned DefIdx;
1340 if (!DefMI->isRegTiedToDefOperand(1, &DefIdx) || DefIdx != 0)
1341 return false;
1342 unsigned SrcIdx1, SrcIdx2;
1343 if (!TII->findCommutedOpIndices(DefMI, SrcIdx1, SrcIdx2))
1344 return false;
1345 if (SrcIdx1 == 1 && SrcIdx2 == 2) {
1346 DstIdx = 2;
1347 return true;
1348 }
1349 return false;
1350 }
1351
Lang Hames87e3bca2009-05-06 02:36:21 +00001352 /// CommuteToFoldReload -
1353 /// Look for
1354 /// r1 = load fi#1
1355 /// r1 = op r1, r2<kill>
1356 /// store r1, fi#1
1357 ///
1358 /// If op is commutable and r2 is killed, then we can xform these to
1359 /// r2 = op r2, fi#1
1360 /// store r2, fi#1
1361 bool CommuteToFoldReload(MachineBasicBlock &MBB,
1362 MachineBasicBlock::iterator &MII,
1363 unsigned VirtReg, unsigned SrcReg, int SS,
1364 AvailableSpills &Spills,
1365 BitVector &RegKills,
1366 std::vector<MachineOperand*> &KillOps,
1367 const TargetRegisterInfo *TRI,
1368 VirtRegMap &VRM) {
1369 if (MII == MBB.begin() || !MII->killsRegister(SrcReg))
1370 return false;
1371
1372 MachineFunction &MF = *MBB.getParent();
1373 MachineInstr &MI = *MII;
1374 MachineBasicBlock::iterator DefMII = prior(MII);
1375 MachineInstr *DefMI = DefMII;
1376 const TargetInstrDesc &TID = DefMI->getDesc();
1377 unsigned NewDstIdx;
1378 if (DefMII != MBB.begin() &&
1379 TID.isCommutable() &&
Evan Cheng261ce1d2009-07-10 19:15:51 +00001380 CommuteChangesDestination(DefMI, TID, SrcReg, TII, NewDstIdx)) {
Lang Hames87e3bca2009-05-06 02:36:21 +00001381 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
1382 unsigned NewReg = NewDstMO.getReg();
1383 if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg))
1384 return false;
1385 MachineInstr *ReloadMI = prior(DefMII);
1386 int FrameIdx;
1387 unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx);
1388 if (DestReg != SrcReg || FrameIdx != SS)
1389 return false;
1390 int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false);
1391 if (UseIdx == -1)
1392 return false;
1393 unsigned DefIdx;
1394 if (!MI.isRegTiedToDefOperand(UseIdx, &DefIdx))
1395 return false;
1396 assert(DefMI->getOperand(DefIdx).isReg() &&
1397 DefMI->getOperand(DefIdx).getReg() == SrcReg);
1398
1399 // Now commute def instruction.
1400 MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true);
1401 if (!CommutedMI)
1402 return false;
1403 SmallVector<unsigned, 1> Ops;
1404 Ops.push_back(NewDstIdx);
1405 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS);
1406 // Not needed since foldMemoryOperand returns new MI.
1407 MF.DeleteMachineInstr(CommutedMI);
1408 if (!FoldedMI)
1409 return false;
1410
1411 VRM.addSpillSlotUse(SS, FoldedMI);
1412 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
1413 // Insert new def MI and spill MI.
1414 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1415 TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC);
1416 MII = prior(MII);
1417 MachineInstr *StoreMI = MII;
1418 VRM.addSpillSlotUse(SS, StoreMI);
1419 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1420 MII = MBB.insert(MII, FoldedMI); // Update MII to backtrack.
1421
1422 // Delete all 3 old instructions.
Evan Cheng427a6b62009-05-15 06:48:19 +00001423 InvalidateKills(*ReloadMI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00001424 VRM.RemoveMachineInstrFromMaps(ReloadMI);
1425 MBB.erase(ReloadMI);
Evan Cheng427a6b62009-05-15 06:48:19 +00001426 InvalidateKills(*DefMI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00001427 VRM.RemoveMachineInstrFromMaps(DefMI);
1428 MBB.erase(DefMI);
Evan Cheng427a6b62009-05-15 06:48:19 +00001429 InvalidateKills(MI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00001430 VRM.RemoveMachineInstrFromMaps(&MI);
1431 MBB.erase(&MI);
1432
1433 // If NewReg was previously holding value of some SS, it's now clobbered.
1434 // This has to be done now because it's a physical register. When this
1435 // instruction is re-visited, it's ignored.
1436 Spills.ClobberPhysReg(NewReg);
1437
1438 ++NumCommutes;
1439 return true;
1440 }
1441
1442 return false;
1443 }
1444
1445 /// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
1446 /// the last store to the same slot is now dead. If so, remove the last store.
1447 void SpillRegToStackSlot(MachineBasicBlock &MBB,
1448 MachineBasicBlock::iterator &MII,
1449 int Idx, unsigned PhysReg, int StackSlot,
1450 const TargetRegisterClass *RC,
1451 bool isAvailable, MachineInstr *&LastStore,
1452 AvailableSpills &Spills,
1453 SmallSet<MachineInstr*, 4> &ReMatDefs,
1454 BitVector &RegKills,
1455 std::vector<MachineOperand*> &KillOps,
1456 VirtRegMap &VRM) {
1457
Dale Johannesene841d2f2009-10-28 21:56:18 +00001458 MachineBasicBlock::iterator oldNextMII = next(MII);
Lang Hames87e3bca2009-05-06 02:36:21 +00001459 TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
Dale Johannesen78c5cda2009-10-29 01:15:40 +00001460 MachineInstr *StoreMI = prior(oldNextMII);
Lang Hames87e3bca2009-05-06 02:36:21 +00001461 VRM.addSpillSlotUse(StackSlot, StoreMI);
Chris Lattner6456d382009-08-23 03:20:44 +00001462 DEBUG(errs() << "Store:\t" << *StoreMI);
Lang Hames87e3bca2009-05-06 02:36:21 +00001463
1464 // If there is a dead store to this stack slot, nuke it now.
1465 if (LastStore) {
Chris Lattner6456d382009-08-23 03:20:44 +00001466 DEBUG(errs() << "Removed dead store:\t" << *LastStore);
Lang Hames87e3bca2009-05-06 02:36:21 +00001467 ++NumDSE;
1468 SmallVector<unsigned, 2> KillRegs;
Evan Cheng427a6b62009-05-15 06:48:19 +00001469 InvalidateKills(*LastStore, TRI, RegKills, KillOps, &KillRegs);
Lang Hames87e3bca2009-05-06 02:36:21 +00001470 MachineBasicBlock::iterator PrevMII = LastStore;
1471 bool CheckDef = PrevMII != MBB.begin();
1472 if (CheckDef)
1473 --PrevMII;
1474 VRM.RemoveMachineInstrFromMaps(LastStore);
1475 MBB.erase(LastStore);
1476 if (CheckDef) {
1477 // Look at defs of killed registers on the store. Mark the defs
1478 // as dead since the store has been deleted and they aren't
1479 // being reused.
1480 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
1481 bool HasOtherDef = false;
Evan Cheng8fdd84c2009-11-14 02:09:09 +00001482 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef, TRI)) {
Lang Hames87e3bca2009-05-06 02:36:21 +00001483 MachineInstr *DeadDef = PrevMII;
1484 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
Evan Cheng4784f1f2009-06-30 08:49:04 +00001485 // FIXME: This assumes a remat def does not have side effects.
Lang Hames87e3bca2009-05-06 02:36:21 +00001486 VRM.RemoveMachineInstrFromMaps(DeadDef);
1487 MBB.erase(DeadDef);
1488 ++NumDRM;
1489 }
1490 }
1491 }
1492 }
1493 }
1494
Dale Johannesene841d2f2009-10-28 21:56:18 +00001495 // Allow for multi-instruction spill sequences, as on PPC Altivec. Presume
1496 // the last of multiple instructions is the actual store.
1497 LastStore = prior(oldNextMII);
Lang Hames87e3bca2009-05-06 02:36:21 +00001498
1499 // If the stack slot value was previously available in some other
1500 // register, change it now. Otherwise, make the register available,
1501 // in PhysReg.
1502 Spills.ModifyStackSlotOrReMat(StackSlot);
1503 Spills.ClobberPhysReg(PhysReg);
1504 Spills.addAvailable(StackSlot, PhysReg, isAvailable);
1505 ++NumStores;
1506 }
1507
Dale Johannesen3a6b9eb2009-10-12 18:49:00 +00001508 /// isSafeToDelete - Return true if this instruction doesn't produce any side
1509 /// effect and all of its defs are dead.
1510 static bool isSafeToDelete(MachineInstr &MI) {
1511 const TargetInstrDesc &TID = MI.getDesc();
1512 if (TID.mayLoad() || TID.mayStore() || TID.isCall() || TID.isTerminator() ||
1513 TID.isCall() || TID.isBarrier() || TID.isReturn() ||
1514 TID.hasUnmodeledSideEffects())
1515 return false;
1516 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1517 MachineOperand &MO = MI.getOperand(i);
1518 if (!MO.isReg() || !MO.getReg())
1519 continue;
1520 if (MO.isDef() && !MO.isDead())
1521 return false;
1522 if (MO.isUse() && MO.isKill())
1523 // FIXME: We can't remove kill markers or else the scavenger will assert.
1524 // An alternative is to add a ADD pseudo instruction to replace kill
1525 // markers.
1526 return false;
1527 }
1528 return true;
1529 }
1530
Lang Hames87e3bca2009-05-06 02:36:21 +00001531 /// TransferDeadness - A identity copy definition is dead and it's being
1532 /// removed. Find the last def or use and mark it as dead / kill.
1533 void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
1534 unsigned Reg, BitVector &RegKills,
Evan Chengeca24fb2009-05-12 23:07:00 +00001535 std::vector<MachineOperand*> &KillOps,
1536 VirtRegMap &VRM) {
1537 SmallPtrSet<MachineInstr*, 4> Seens;
1538 SmallVector<std::pair<MachineInstr*, int>,8> Refs;
Lang Hames87e3bca2009-05-06 02:36:21 +00001539 for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg),
1540 RE = RegInfo->reg_end(); RI != RE; ++RI) {
1541 MachineInstr *UDMI = &*RI;
1542 if (UDMI->getParent() != MBB)
1543 continue;
1544 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
1545 if (DI == DistanceMap.end() || DI->second > CurDist)
1546 continue;
Evan Chengeca24fb2009-05-12 23:07:00 +00001547 if (Seens.insert(UDMI))
1548 Refs.push_back(std::make_pair(UDMI, DI->second));
Lang Hames87e3bca2009-05-06 02:36:21 +00001549 }
1550
Evan Chengeca24fb2009-05-12 23:07:00 +00001551 if (Refs.empty())
1552 return;
1553 std::sort(Refs.begin(), Refs.end(), RefSorter());
1554
1555 while (!Refs.empty()) {
1556 MachineInstr *LastUDMI = Refs.back().first;
1557 Refs.pop_back();
1558
Lang Hames87e3bca2009-05-06 02:36:21 +00001559 MachineOperand *LastUD = NULL;
1560 for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) {
1561 MachineOperand &MO = LastUDMI->getOperand(i);
1562 if (!MO.isReg() || MO.getReg() != Reg)
1563 continue;
1564 if (!LastUD || (LastUD->isUse() && MO.isDef()))
1565 LastUD = &MO;
1566 if (LastUDMI->isRegTiedToDefOperand(i))
Evan Chengeca24fb2009-05-12 23:07:00 +00001567 break;
Lang Hames87e3bca2009-05-06 02:36:21 +00001568 }
Evan Chengeca24fb2009-05-12 23:07:00 +00001569 if (LastUD->isDef()) {
1570 // If the instruction has no side effect, delete it and propagate
1571 // backward further. Otherwise, mark is dead and we are done.
Dale Johannesen3a6b9eb2009-10-12 18:49:00 +00001572 if (!isSafeToDelete(*LastUDMI)) {
Evan Chengeca24fb2009-05-12 23:07:00 +00001573 LastUD->setIsDead();
1574 break;
1575 }
1576 VRM.RemoveMachineInstrFromMaps(LastUDMI);
1577 MBB->erase(LastUDMI);
1578 } else {
Lang Hames87e3bca2009-05-06 02:36:21 +00001579 LastUD->setIsKill();
1580 RegKills.set(Reg);
1581 KillOps[Reg] = LastUD;
Evan Chengeca24fb2009-05-12 23:07:00 +00001582 break;
Lang Hames87e3bca2009-05-06 02:36:21 +00001583 }
1584 }
1585 }
1586
1587 /// rewriteMBB - Keep track of which spills are available even after the
1588 /// register allocator is done with them. If possible, avid reloading vregs.
1589 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
1590 LiveIntervals *LIs,
1591 AvailableSpills &Spills, BitVector &RegKills,
1592 std::vector<MachineOperand*> &KillOps) {
1593
Daniel Dunbarce63ffb2009-07-25 00:23:56 +00001594 DEBUG(errs() << "\n**** Local spiller rewriting MBB '"
1595 << MBB.getBasicBlock()->getName() << "':\n");
Lang Hames87e3bca2009-05-06 02:36:21 +00001596
1597 MachineFunction &MF = *MBB.getParent();
1598
1599 // MaybeDeadStores - When we need to write a value back into a stack slot,
1600 // keep track of the inserted store. If the stack slot value is never read
1601 // (because the value was used from some available register, for example), and
1602 // subsequently stored to, the original store is dead. This map keeps track
1603 // of inserted stores that are not used. If we see a subsequent store to the
1604 // same stack slot, the original store is deleted.
1605 std::vector<MachineInstr*> MaybeDeadStores;
1606 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
1607
1608 // ReMatDefs - These are rematerializable def MIs which are not deleted.
1609 SmallSet<MachineInstr*, 4> ReMatDefs;
1610
1611 // Clear kill info.
1612 SmallSet<unsigned, 2> KilledMIRegs;
1613 RegKills.reset();
1614 KillOps.clear();
1615 KillOps.resize(TRI->getNumRegs(), NULL);
1616
1617 unsigned Dist = 0;
1618 DistanceMap.clear();
1619 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
1620 MII != E; ) {
1621 MachineBasicBlock::iterator NextMII = next(MII);
1622
1623 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
1624 bool Erased = false;
1625 bool BackTracked = false;
1626 if (OptimizeByUnfold(MBB, MII,
1627 MaybeDeadStores, Spills, RegKills, KillOps, VRM))
1628 NextMII = next(MII);
1629
1630 MachineInstr &MI = *MII;
1631
1632 if (VRM.hasEmergencySpills(&MI)) {
1633 // Spill physical register(s) in the rare case the allocator has run out
1634 // of registers to allocate.
1635 SmallSet<int, 4> UsedSS;
1636 std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI);
1637 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
1638 unsigned PhysReg = EmSpills[i];
1639 const TargetRegisterClass *RC =
1640 TRI->getPhysicalRegisterRegClass(PhysReg);
1641 assert(RC && "Unable to determine register class!");
1642 int SS = VRM.getEmergencySpillSlot(RC);
1643 if (UsedSS.count(SS))
Torok Edwinc23197a2009-07-14 16:55:14 +00001644 llvm_unreachable("Need to spill more than one physical registers!");
Lang Hames87e3bca2009-05-06 02:36:21 +00001645 UsedSS.insert(SS);
1646 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
1647 MachineInstr *StoreMI = prior(MII);
1648 VRM.addSpillSlotUse(SS, StoreMI);
David Greene2d4e6d32009-07-28 16:49:24 +00001649
1650 // Back-schedule reloads and remats.
1651 MachineBasicBlock::iterator InsertLoc =
1652 ComputeReloadLoc(next(MII), MBB.begin(), PhysReg, TRI, false,
1653 SS, TII, MF);
1654
1655 TII->loadRegFromStackSlot(MBB, InsertLoc, PhysReg, SS, RC);
1656
1657 MachineInstr *LoadMI = prior(InsertLoc);
Lang Hames87e3bca2009-05-06 02:36:21 +00001658 VRM.addSpillSlotUse(SS, LoadMI);
1659 ++NumPSpills;
Jakob Stoklund Olesen7a1e8722009-08-15 11:03:03 +00001660 DistanceMap.insert(std::make_pair(LoadMI, Dist++));
Lang Hames87e3bca2009-05-06 02:36:21 +00001661 }
1662 NextMII = next(MII);
1663 }
1664
1665 // Insert restores here if asked to.
1666 if (VRM.isRestorePt(&MI)) {
1667 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
1668 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
1669 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order.
1670 if (!VRM.getPreSplitReg(VirtReg))
1671 continue; // Split interval spilled again.
1672 unsigned Phys = VRM.getPhys(VirtReg);
1673 RegInfo->setPhysRegUsed(Phys);
1674
1675 // Check if the value being restored if available. If so, it must be
1676 // from a predecessor BB that fallthrough into this BB. We do not
1677 // expect:
1678 // BB1:
1679 // r1 = load fi#1
1680 // ...
1681 // = r1<kill>
1682 // ... # r1 not clobbered
1683 // ...
1684 // = load fi#1
1685 bool DoReMat = VRM.isReMaterialized(VirtReg);
1686 int SSorRMId = DoReMat
1687 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
1688 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1689 unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
1690 if (InReg == Phys) {
1691 // If the value is already available in the expected register, save
1692 // a reload / remat.
1693 if (SSorRMId)
Chris Lattner6456d382009-08-23 03:20:44 +00001694 DEBUG(errs() << "Reusing RM#"
1695 << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1);
Lang Hames87e3bca2009-05-06 02:36:21 +00001696 else
Chris Lattner6456d382009-08-23 03:20:44 +00001697 DEBUG(errs() << "Reusing SS#" << SSorRMId);
1698 DEBUG(errs() << " from physreg "
1699 << TRI->getName(InReg) << " for vreg"
1700 << VirtReg <<" instead of reloading into physreg "
1701 << TRI->getName(Phys) << '\n');
Lang Hames87e3bca2009-05-06 02:36:21 +00001702 ++NumOmitted;
1703 continue;
1704 } else if (InReg && InReg != Phys) {
1705 if (SSorRMId)
Chris Lattner6456d382009-08-23 03:20:44 +00001706 DEBUG(errs() << "Reusing RM#"
1707 << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1);
Lang Hames87e3bca2009-05-06 02:36:21 +00001708 else
Chris Lattner6456d382009-08-23 03:20:44 +00001709 DEBUG(errs() << "Reusing SS#" << SSorRMId);
1710 DEBUG(errs() << " from physreg "
1711 << TRI->getName(InReg) << " for vreg"
1712 << VirtReg <<" by copying it into physreg "
1713 << TRI->getName(Phys) << '\n');
Lang Hames87e3bca2009-05-06 02:36:21 +00001714
1715 // If the reloaded / remat value is available in another register,
1716 // copy it to the desired register.
David Greene2d4e6d32009-07-28 16:49:24 +00001717
1718 // Back-schedule reloads and remats.
1719 MachineBasicBlock::iterator InsertLoc =
1720 ComputeReloadLoc(MII, MBB.begin(), Phys, TRI, DoReMat,
1721 SSorRMId, TII, MF);
1722
1723 TII->copyRegToReg(MBB, InsertLoc, Phys, InReg, RC, RC);
Lang Hames87e3bca2009-05-06 02:36:21 +00001724
1725 // This invalidates Phys.
1726 Spills.ClobberPhysReg(Phys);
1727 // Remember it's available.
1728 Spills.addAvailable(SSorRMId, Phys);
1729
1730 // Mark is killed.
David Greene2d4e6d32009-07-28 16:49:24 +00001731 MachineInstr *CopyMI = prior(InsertLoc);
David Greene6bedb302009-11-12 21:07:54 +00001732 CopyMI->setAsmPrinterFlag(AsmPrinter::ReloadReuse);
Lang Hames87e3bca2009-05-06 02:36:21 +00001733 MachineOperand *KillOpnd = CopyMI->findRegisterUseOperand(InReg);
1734 KillOpnd->setIsKill();
Evan Cheng427a6b62009-05-15 06:48:19 +00001735 UpdateKills(*CopyMI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00001736
Chris Lattner6456d382009-08-23 03:20:44 +00001737 DEBUG(errs() << '\t' << *CopyMI);
Lang Hames87e3bca2009-05-06 02:36:21 +00001738 ++NumCopified;
1739 continue;
1740 }
1741
David Greene2d4e6d32009-07-28 16:49:24 +00001742 // Back-schedule reloads and remats.
1743 MachineBasicBlock::iterator InsertLoc =
1744 ComputeReloadLoc(MII, MBB.begin(), Phys, TRI, DoReMat,
1745 SSorRMId, TII, MF);
1746
Lang Hames87e3bca2009-05-06 02:36:21 +00001747 if (VRM.isReMaterialized(VirtReg)) {
David Greene2d4e6d32009-07-28 16:49:24 +00001748 ReMaterialize(MBB, InsertLoc, Phys, VirtReg, TII, TRI, VRM);
Lang Hames87e3bca2009-05-06 02:36:21 +00001749 } else {
1750 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
David Greene2d4e6d32009-07-28 16:49:24 +00001751 TII->loadRegFromStackSlot(MBB, InsertLoc, Phys, SSorRMId, RC);
1752 MachineInstr *LoadMI = prior(InsertLoc);
Lang Hames87e3bca2009-05-06 02:36:21 +00001753 VRM.addSpillSlotUse(SSorRMId, LoadMI);
1754 ++NumLoads;
Jakob Stoklund Olesen7a1e8722009-08-15 11:03:03 +00001755 DistanceMap.insert(std::make_pair(LoadMI, Dist++));
Lang Hames87e3bca2009-05-06 02:36:21 +00001756 }
1757
1758 // This invalidates Phys.
1759 Spills.ClobberPhysReg(Phys);
1760 // Remember it's available.
1761 Spills.addAvailable(SSorRMId, Phys);
1762
David Greene2d4e6d32009-07-28 16:49:24 +00001763 UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
Chris Lattner6456d382009-08-23 03:20:44 +00001764 DEBUG(errs() << '\t' << *prior(MII));
Lang Hames87e3bca2009-05-06 02:36:21 +00001765 }
1766 }
1767
1768 // Insert spills here if asked to.
1769 if (VRM.isSpillPt(&MI)) {
1770 std::vector<std::pair<unsigned,bool> > &SpillRegs =
1771 VRM.getSpillPtSpills(&MI);
1772 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
1773 unsigned VirtReg = SpillRegs[i].first;
1774 bool isKill = SpillRegs[i].second;
1775 if (!VRM.getPreSplitReg(VirtReg))
1776 continue; // Split interval spilled again.
1777 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1778 unsigned Phys = VRM.getPhys(VirtReg);
1779 int StackSlot = VRM.getStackSlot(VirtReg);
Dale Johannesen78c5cda2009-10-29 01:15:40 +00001780 MachineBasicBlock::iterator oldNextMII = next(MII);
Lang Hames87e3bca2009-05-06 02:36:21 +00001781 TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
Dale Johannesen78c5cda2009-10-29 01:15:40 +00001782 MachineInstr *StoreMI = prior(oldNextMII);
Lang Hames87e3bca2009-05-06 02:36:21 +00001783 VRM.addSpillSlotUse(StackSlot, StoreMI);
Chris Lattner6456d382009-08-23 03:20:44 +00001784 DEBUG(errs() << "Store:\t" << *StoreMI);
Lang Hames87e3bca2009-05-06 02:36:21 +00001785 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1786 }
1787 NextMII = next(MII);
1788 }
1789
1790 /// ReusedOperands - Keep track of operand reuse in case we need to undo
1791 /// reuse.
1792 ReuseInfo ReusedOperands(MI, TRI);
1793 SmallVector<unsigned, 4> VirtUseOps;
1794 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1795 MachineOperand &MO = MI.getOperand(i);
1796 if (!MO.isReg() || MO.getReg() == 0)
1797 continue; // Ignore non-register operands.
1798
1799 unsigned VirtReg = MO.getReg();
1800 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
1801 // Ignore physregs for spilling, but remember that it is used by this
1802 // function.
1803 RegInfo->setPhysRegUsed(VirtReg);
1804 continue;
1805 }
1806
1807 // We want to process implicit virtual register uses first.
1808 if (MO.isImplicit())
1809 // If the virtual register is implicitly defined, emit a implicit_def
1810 // before so scavenger knows it's "defined".
Evan Cheng4784f1f2009-06-30 08:49:04 +00001811 // FIXME: This is a horrible hack done the by register allocator to
1812 // remat a definition with virtual register operand.
Lang Hames87e3bca2009-05-06 02:36:21 +00001813 VirtUseOps.insert(VirtUseOps.begin(), i);
1814 else
1815 VirtUseOps.push_back(i);
1816 }
1817
1818 // Process all of the spilled uses and all non spilled reg references.
1819 SmallVector<int, 2> PotentialDeadStoreSlots;
1820 KilledMIRegs.clear();
1821 for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
1822 unsigned i = VirtUseOps[j];
1823 MachineOperand &MO = MI.getOperand(i);
1824 unsigned VirtReg = MO.getReg();
1825 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
1826 "Not a virtual register?");
1827
1828 unsigned SubIdx = MO.getSubReg();
1829 if (VRM.isAssignedReg(VirtReg)) {
1830 // This virtual register was assigned a physreg!
1831 unsigned Phys = VRM.getPhys(VirtReg);
1832 RegInfo->setPhysRegUsed(Phys);
1833 if (MO.isDef())
1834 ReusedOperands.markClobbered(Phys);
1835 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
1836 MI.getOperand(i).setReg(RReg);
1837 MI.getOperand(i).setSubReg(0);
1838 if (VRM.isImplicitlyDefined(VirtReg))
Evan Cheng4784f1f2009-06-30 08:49:04 +00001839 // FIXME: Is this needed?
Lang Hames87e3bca2009-05-06 02:36:21 +00001840 BuildMI(MBB, &MI, MI.getDebugLoc(),
1841 TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg);
1842 continue;
1843 }
1844
1845 // This virtual register is now known to be a spilled value.
1846 if (!MO.isUse())
1847 continue; // Handle defs in the loop below (handle use&def here though)
1848
Evan Cheng4784f1f2009-06-30 08:49:04 +00001849 bool AvoidReload = MO.isUndef();
1850 // Check if it is defined by an implicit def. It should not be spilled.
1851 // Note, this is for correctness reason. e.g.
1852 // 8 %reg1024<def> = IMPLICIT_DEF
1853 // 12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
1854 // The live range [12, 14) are not part of the r1024 live interval since
1855 // it's defined by an implicit def. It will not conflicts with live
1856 // interval of r1025. Now suppose both registers are spilled, you can
1857 // easily see a situation where both registers are reloaded before
1858 // the INSERT_SUBREG and both target registers that would overlap.
Lang Hames87e3bca2009-05-06 02:36:21 +00001859 bool DoReMat = VRM.isReMaterialized(VirtReg);
1860 int SSorRMId = DoReMat
1861 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
1862 int ReuseSlot = SSorRMId;
1863
1864 // Check to see if this stack slot is available.
1865 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
1866
1867 // If this is a sub-register use, make sure the reuse register is in the
1868 // right register class. For example, for x86 not all of the 32-bit
1869 // registers have accessible sub-registers.
1870 // Similarly so for EXTRACT_SUBREG. Consider this:
1871 // EDI = op
1872 // MOV32_mr fi#1, EDI
1873 // ...
1874 // = EXTRACT_SUBREG fi#1
1875 // fi#1 is available in EDI, but it cannot be reused because it's not in
1876 // the right register file.
1877 if (PhysReg && !AvoidReload &&
1878 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
1879 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1880 if (!RC->contains(PhysReg))
1881 PhysReg = 0;
1882 }
1883
1884 if (PhysReg && !AvoidReload) {
1885 // This spilled operand might be part of a two-address operand. If this
1886 // is the case, then changing it will necessarily require changing the
1887 // def part of the instruction as well. However, in some cases, we
1888 // aren't allowed to modify the reused register. If none of these cases
1889 // apply, reuse it.
1890 bool CanReuse = true;
1891 bool isTied = MI.isRegTiedToDefOperand(i);
1892 if (isTied) {
1893 // Okay, we have a two address operand. We can reuse this physreg as
1894 // long as we are allowed to clobber the value and there isn't an
1895 // earlier def that has already clobbered the physreg.
1896 CanReuse = !ReusedOperands.isClobbered(PhysReg) &&
1897 Spills.canClobberPhysReg(PhysReg);
1898 }
1899
1900 if (CanReuse) {
1901 // If this stack slot value is already available, reuse it!
1902 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
Chris Lattner6456d382009-08-23 03:20:44 +00001903 DEBUG(errs() << "Reusing RM#"
1904 << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1);
Lang Hames87e3bca2009-05-06 02:36:21 +00001905 else
Chris Lattner6456d382009-08-23 03:20:44 +00001906 DEBUG(errs() << "Reusing SS#" << ReuseSlot);
1907 DEBUG(errs() << " from physreg "
1908 << TRI->getName(PhysReg) << " for vreg"
1909 << VirtReg <<" instead of reloading into physreg "
1910 << TRI->getName(VRM.getPhys(VirtReg)) << '\n');
Lang Hames87e3bca2009-05-06 02:36:21 +00001911 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1912 MI.getOperand(i).setReg(RReg);
1913 MI.getOperand(i).setSubReg(0);
1914
1915 // The only technical detail we have is that we don't know that
1916 // PhysReg won't be clobbered by a reloaded stack slot that occurs
1917 // later in the instruction. In particular, consider 'op V1, V2'.
1918 // If V1 is available in physreg R0, we would choose to reuse it
1919 // here, instead of reloading it into the register the allocator
1920 // indicated (say R1). However, V2 might have to be reloaded
1921 // later, and it might indicate that it needs to live in R0. When
1922 // this occurs, we need to have information available that
1923 // indicates it is safe to use R1 for the reload instead of R0.
1924 //
1925 // To further complicate matters, we might conflict with an alias,
1926 // or R0 and R1 might not be compatible with each other. In this
1927 // case, we actually insert a reload for V1 in R1, ensuring that
1928 // we can get at R0 or its alias.
1929 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
1930 VRM.getPhys(VirtReg), VirtReg);
1931 if (isTied)
1932 // Only mark it clobbered if this is a use&def operand.
1933 ReusedOperands.markClobbered(PhysReg);
1934 ++NumReused;
1935
1936 if (MI.getOperand(i).isKill() &&
1937 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
1938
1939 // The store of this spilled value is potentially dead, but we
1940 // won't know for certain until we've confirmed that the re-use
1941 // above is valid, which means waiting until the other operands
1942 // are processed. For now we just track the spill slot, we'll
1943 // remove it after the other operands are processed if valid.
1944
1945 PotentialDeadStoreSlots.push_back(ReuseSlot);
1946 }
1947
1948 // Mark is isKill if it's there no other uses of the same virtual
1949 // register and it's not a two-address operand. IsKill will be
1950 // unset if reg is reused.
1951 if (!isTied && KilledMIRegs.count(VirtReg) == 0) {
1952 MI.getOperand(i).setIsKill();
1953 KilledMIRegs.insert(VirtReg);
1954 }
1955
1956 continue;
1957 } // CanReuse
1958
1959 // Otherwise we have a situation where we have a two-address instruction
1960 // whose mod/ref operand needs to be reloaded. This reload is already
1961 // available in some register "PhysReg", but if we used PhysReg as the
1962 // operand to our 2-addr instruction, the instruction would modify
1963 // PhysReg. This isn't cool if something later uses PhysReg and expects
1964 // to get its initial value.
1965 //
1966 // To avoid this problem, and to avoid doing a load right after a store,
1967 // we emit a copy from PhysReg into the designated register for this
1968 // operand.
1969 unsigned DesignatedReg = VRM.getPhys(VirtReg);
1970 assert(DesignatedReg && "Must map virtreg to physreg!");
1971
1972 // Note that, if we reused a register for a previous operand, the
1973 // register we want to reload into might not actually be
1974 // available. If this occurs, use the register indicated by the
1975 // reuser.
1976 if (ReusedOperands.hasReuses())
Evan Cheng5d885022009-07-21 09:15:00 +00001977 DesignatedReg = ReusedOperands.GetRegForReload(VirtReg,
1978 DesignatedReg, &MI,
1979 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Lang Hames87e3bca2009-05-06 02:36:21 +00001980
1981 // If the mapped designated register is actually the physreg we have
1982 // incoming, we don't need to inserted a dead copy.
1983 if (DesignatedReg == PhysReg) {
1984 // If this stack slot value is already available, reuse it!
1985 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
Chris Lattner6456d382009-08-23 03:20:44 +00001986 DEBUG(errs() << "Reusing RM#"
1987 << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1);
Lang Hames87e3bca2009-05-06 02:36:21 +00001988 else
Chris Lattner6456d382009-08-23 03:20:44 +00001989 DEBUG(errs() << "Reusing SS#" << ReuseSlot);
1990 DEBUG(errs() << " from physreg " << TRI->getName(PhysReg)
1991 << " for vreg" << VirtReg
1992 << " instead of reloading into same physreg.\n");
Lang Hames87e3bca2009-05-06 02:36:21 +00001993 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1994 MI.getOperand(i).setReg(RReg);
1995 MI.getOperand(i).setSubReg(0);
1996 ReusedOperands.markClobbered(RReg);
1997 ++NumReused;
1998 continue;
1999 }
2000
2001 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
2002 RegInfo->setPhysRegUsed(DesignatedReg);
2003 ReusedOperands.markClobbered(DesignatedReg);
Lang Hames87e3bca2009-05-06 02:36:21 +00002004
David Greene2d4e6d32009-07-28 16:49:24 +00002005 // Back-schedule reloads and remats.
2006 MachineBasicBlock::iterator InsertLoc =
2007 ComputeReloadLoc(&MI, MBB.begin(), PhysReg, TRI, DoReMat,
2008 SSorRMId, TII, MF);
2009
2010 TII->copyRegToReg(MBB, InsertLoc, DesignatedReg, PhysReg, RC, RC);
2011
2012 MachineInstr *CopyMI = prior(InsertLoc);
David Greene6bedb302009-11-12 21:07:54 +00002013 CopyMI->setAsmPrinterFlag(AsmPrinter::ReloadReuse);
Evan Cheng427a6b62009-05-15 06:48:19 +00002014 UpdateKills(*CopyMI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00002015
2016 // This invalidates DesignatedReg.
2017 Spills.ClobberPhysReg(DesignatedReg);
2018
2019 Spills.addAvailable(ReuseSlot, DesignatedReg);
2020 unsigned RReg =
2021 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
2022 MI.getOperand(i).setReg(RReg);
2023 MI.getOperand(i).setSubReg(0);
Chris Lattner6456d382009-08-23 03:20:44 +00002024 DEBUG(errs() << '\t' << *prior(MII));
Lang Hames87e3bca2009-05-06 02:36:21 +00002025 ++NumReused;
2026 continue;
2027 } // if (PhysReg)
2028
2029 // Otherwise, reload it and remember that we have it.
2030 PhysReg = VRM.getPhys(VirtReg);
2031 assert(PhysReg && "Must map virtreg to physreg!");
2032
2033 // Note that, if we reused a register for a previous operand, the
2034 // register we want to reload into might not actually be
2035 // available. If this occurs, use the register indicated by the
2036 // reuser.
2037 if (ReusedOperands.hasReuses())
Evan Cheng5d885022009-07-21 09:15:00 +00002038 PhysReg = ReusedOperands.GetRegForReload(VirtReg, PhysReg, &MI,
2039 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Lang Hames87e3bca2009-05-06 02:36:21 +00002040
2041 RegInfo->setPhysRegUsed(PhysReg);
2042 ReusedOperands.markClobbered(PhysReg);
2043 if (AvoidReload)
2044 ++NumAvoided;
2045 else {
David Greene2d4e6d32009-07-28 16:49:24 +00002046 // Back-schedule reloads and remats.
2047 MachineBasicBlock::iterator InsertLoc =
2048 ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, DoReMat,
2049 SSorRMId, TII, MF);
2050
Lang Hames87e3bca2009-05-06 02:36:21 +00002051 if (DoReMat) {
David Greene2d4e6d32009-07-28 16:49:24 +00002052 ReMaterialize(MBB, InsertLoc, PhysReg, VirtReg, TII, TRI, VRM);
Lang Hames87e3bca2009-05-06 02:36:21 +00002053 } else {
2054 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
David Greene2d4e6d32009-07-28 16:49:24 +00002055 TII->loadRegFromStackSlot(MBB, InsertLoc, PhysReg, SSorRMId, RC);
2056 MachineInstr *LoadMI = prior(InsertLoc);
Lang Hames87e3bca2009-05-06 02:36:21 +00002057 VRM.addSpillSlotUse(SSorRMId, LoadMI);
2058 ++NumLoads;
Jakob Stoklund Olesen7a1e8722009-08-15 11:03:03 +00002059 DistanceMap.insert(std::make_pair(LoadMI, Dist++));
Lang Hames87e3bca2009-05-06 02:36:21 +00002060 }
2061 // This invalidates PhysReg.
2062 Spills.ClobberPhysReg(PhysReg);
2063
2064 // Any stores to this stack slot are not dead anymore.
2065 if (!DoReMat)
2066 MaybeDeadStores[SSorRMId] = NULL;
2067 Spills.addAvailable(SSorRMId, PhysReg);
2068 // Assumes this is the last use. IsKill will be unset if reg is reused
2069 // unless it's a two-address operand.
2070 if (!MI.isRegTiedToDefOperand(i) &&
2071 KilledMIRegs.count(VirtReg) == 0) {
2072 MI.getOperand(i).setIsKill();
2073 KilledMIRegs.insert(VirtReg);
2074 }
2075
David Greene2d4e6d32009-07-28 16:49:24 +00002076 UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
Chris Lattner6456d382009-08-23 03:20:44 +00002077 DEBUG(errs() << '\t' << *prior(InsertLoc));
Lang Hames87e3bca2009-05-06 02:36:21 +00002078 }
2079 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
2080 MI.getOperand(i).setReg(RReg);
2081 MI.getOperand(i).setSubReg(0);
2082 }
2083
2084 // Ok - now we can remove stores that have been confirmed dead.
2085 for (unsigned j = 0, e = PotentialDeadStoreSlots.size(); j != e; ++j) {
2086 // This was the last use and the spilled value is still available
2087 // for reuse. That means the spill was unnecessary!
2088 int PDSSlot = PotentialDeadStoreSlots[j];
2089 MachineInstr* DeadStore = MaybeDeadStores[PDSSlot];
2090 if (DeadStore) {
Chris Lattner6456d382009-08-23 03:20:44 +00002091 DEBUG(errs() << "Removed dead store:\t" << *DeadStore);
Evan Cheng427a6b62009-05-15 06:48:19 +00002092 InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00002093 VRM.RemoveMachineInstrFromMaps(DeadStore);
2094 MBB.erase(DeadStore);
2095 MaybeDeadStores[PDSSlot] = NULL;
2096 ++NumDSE;
2097 }
2098 }
2099
2100
Chris Lattner6456d382009-08-23 03:20:44 +00002101 DEBUG(errs() << '\t' << MI);
Lang Hames87e3bca2009-05-06 02:36:21 +00002102
2103
2104 // If we have folded references to memory operands, make sure we clear all
2105 // physical registers that may contain the value of the spilled virtual
2106 // register
2107 SmallSet<int, 2> FoldedSS;
2108 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
2109 unsigned VirtReg = I->second.first;
2110 VirtRegMap::ModRef MR = I->second.second;
Chris Lattner6456d382009-08-23 03:20:44 +00002111 DEBUG(errs() << "Folded vreg: " << VirtReg << " MR: " << MR);
Lang Hames87e3bca2009-05-06 02:36:21 +00002112
2113 // MI2VirtMap be can updated which invalidate the iterator.
2114 // Increment the iterator first.
2115 ++I;
2116 int SS = VRM.getStackSlot(VirtReg);
2117 if (SS == VirtRegMap::NO_STACK_SLOT)
2118 continue;
2119 FoldedSS.insert(SS);
Chris Lattner6456d382009-08-23 03:20:44 +00002120 DEBUG(errs() << " - StackSlot: " << SS << "\n");
Lang Hames87e3bca2009-05-06 02:36:21 +00002121
2122 // If this folded instruction is just a use, check to see if it's a
2123 // straight load from the virt reg slot.
2124 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
2125 int FrameIdx;
2126 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
2127 if (DestReg && FrameIdx == SS) {
2128 // If this spill slot is available, turn it into a copy (or nothing)
2129 // instead of leaving it as a load!
2130 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
Chris Lattner6456d382009-08-23 03:20:44 +00002131 DEBUG(errs() << "Promoted Load To Copy: " << MI);
Lang Hames87e3bca2009-05-06 02:36:21 +00002132 if (DestReg != InReg) {
2133 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
2134 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
2135 MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg);
2136 unsigned SubIdx = DefMO->getSubReg();
2137 // Revisit the copy so we make sure to notice the effects of the
2138 // operation on the destreg (either needing to RA it if it's
2139 // virtual or needing to clobber any values if it's physical).
2140 NextMII = &MI;
2141 --NextMII; // backtrack to the copy.
David Greene6bedb302009-11-12 21:07:54 +00002142 NextMII->setAsmPrinterFlag(AsmPrinter::ReloadReuse);
Lang Hames87e3bca2009-05-06 02:36:21 +00002143 // Propagate the sub-register index over.
2144 if (SubIdx) {
2145 DefMO = NextMII->findRegisterDefOperand(DestReg);
2146 DefMO->setSubReg(SubIdx);
2147 }
2148
2149 // Mark is killed.
2150 MachineOperand *KillOpnd = NextMII->findRegisterUseOperand(InReg);
2151 KillOpnd->setIsKill();
2152
2153 BackTracked = true;
2154 } else {
Chris Lattner6456d382009-08-23 03:20:44 +00002155 DEBUG(errs() << "Removing now-noop copy: " << MI);
Lang Hames87e3bca2009-05-06 02:36:21 +00002156 // Unset last kill since it's being reused.
Evan Cheng427a6b62009-05-15 06:48:19 +00002157 InvalidateKill(InReg, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00002158 Spills.disallowClobberPhysReg(InReg);
2159 }
2160
Evan Cheng427a6b62009-05-15 06:48:19 +00002161 InvalidateKills(MI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00002162 VRM.RemoveMachineInstrFromMaps(&MI);
2163 MBB.erase(&MI);
2164 Erased = true;
2165 goto ProcessNextInst;
2166 }
2167 } else {
2168 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
2169 SmallVector<MachineInstr*, 4> NewMIs;
2170 if (PhysReg &&
2171 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
2172 MBB.insert(MII, NewMIs[0]);
Evan Cheng427a6b62009-05-15 06:48:19 +00002173 InvalidateKills(MI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00002174 VRM.RemoveMachineInstrFromMaps(&MI);
2175 MBB.erase(&MI);
2176 Erased = true;
2177 --NextMII; // backtrack to the unfolded instruction.
2178 BackTracked = true;
2179 goto ProcessNextInst;
2180 }
2181 }
2182 }
2183
2184 // If this reference is not a use, any previous store is now dead.
2185 // Otherwise, the store to this stack slot is not dead anymore.
2186 MachineInstr* DeadStore = MaybeDeadStores[SS];
2187 if (DeadStore) {
2188 bool isDead = !(MR & VirtRegMap::isRef);
2189 MachineInstr *NewStore = NULL;
2190 if (MR & VirtRegMap::isModRef) {
2191 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
2192 SmallVector<MachineInstr*, 4> NewMIs;
2193 // We can reuse this physreg as long as we are allowed to clobber
2194 // the value and there isn't an earlier def that has already clobbered
2195 // the physreg.
2196 if (PhysReg &&
2197 !ReusedOperands.isClobbered(PhysReg) &&
2198 Spills.canClobberPhysReg(PhysReg) &&
2199 !TII->isStoreToStackSlot(&MI, SS)) { // Not profitable!
2200 MachineOperand *KillOpnd =
2201 DeadStore->findRegisterUseOperand(PhysReg, true);
2202 // Note, if the store is storing a sub-register, it's possible the
2203 // super-register is needed below.
2204 if (KillOpnd && !KillOpnd->getSubReg() &&
2205 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){
2206 MBB.insert(MII, NewMIs[0]);
2207 NewStore = NewMIs[1];
2208 MBB.insert(MII, NewStore);
2209 VRM.addSpillSlotUse(SS, NewStore);
Evan Cheng427a6b62009-05-15 06:48:19 +00002210 InvalidateKills(MI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00002211 VRM.RemoveMachineInstrFromMaps(&MI);
2212 MBB.erase(&MI);
2213 Erased = true;
2214 --NextMII;
2215 --NextMII; // backtrack to the unfolded instruction.
2216 BackTracked = true;
2217 isDead = true;
2218 ++NumSUnfold;
2219 }
2220 }
2221 }
2222
2223 if (isDead) { // Previous store is dead.
2224 // If we get here, the store is dead, nuke it now.
Chris Lattner6456d382009-08-23 03:20:44 +00002225 DEBUG(errs() << "Removed dead store:\t" << *DeadStore);
Evan Cheng427a6b62009-05-15 06:48:19 +00002226 InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00002227 VRM.RemoveMachineInstrFromMaps(DeadStore);
2228 MBB.erase(DeadStore);
2229 if (!NewStore)
2230 ++NumDSE;
2231 }
2232
2233 MaybeDeadStores[SS] = NULL;
2234 if (NewStore) {
2235 // Treat this store as a spill merged into a copy. That makes the
2236 // stack slot value available.
2237 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
2238 goto ProcessNextInst;
2239 }
2240 }
2241
2242 // If the spill slot value is available, and this is a new definition of
2243 // the value, the value is not available anymore.
2244 if (MR & VirtRegMap::isMod) {
2245 // Notice that the value in this stack slot has been modified.
2246 Spills.ModifyStackSlotOrReMat(SS);
2247
2248 // If this is *just* a mod of the value, check to see if this is just a
2249 // store to the spill slot (i.e. the spill got merged into the copy). If
2250 // so, realize that the vreg is available now, and add the store to the
2251 // MaybeDeadStore info.
2252 int StackSlot;
2253 if (!(MR & VirtRegMap::isRef)) {
2254 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
2255 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
2256 "Src hasn't been allocated yet?");
2257
2258 if (CommuteToFoldReload(MBB, MII, VirtReg, SrcReg, StackSlot,
2259 Spills, RegKills, KillOps, TRI, VRM)) {
2260 NextMII = next(MII);
2261 BackTracked = true;
2262 goto ProcessNextInst;
2263 }
2264
2265 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
2266 // this as a potentially dead store in case there is a subsequent
2267 // store into the stack slot without a read from it.
2268 MaybeDeadStores[StackSlot] = &MI;
2269
2270 // If the stack slot value was previously available in some other
2271 // register, change it now. Otherwise, make the register
2272 // available in PhysReg.
2273 Spills.addAvailable(StackSlot, SrcReg, MI.killsRegister(SrcReg));
2274 }
2275 }
2276 }
2277 }
2278
2279 // Process all of the spilled defs.
2280 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2281 MachineOperand &MO = MI.getOperand(i);
2282 if (!(MO.isReg() && MO.getReg() && MO.isDef()))
2283 continue;
2284
2285 unsigned VirtReg = MO.getReg();
2286 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) {
2287 // Check to see if this is a noop copy. If so, eliminate the
2288 // instruction before considering the dest reg to be changed.
Evan Cheng2578ba22009-07-01 01:59:31 +00002289 // Also check if it's copying from an "undef", if so, we can't
2290 // eliminate this or else the undef marker is lost and it will
2291 // confuses the scavenger. This is extremely rare.
Lang Hames87e3bca2009-05-06 02:36:21 +00002292 unsigned Src, Dst, SrcSR, DstSR;
Evan Chenga5dc45e2009-10-26 04:56:07 +00002293 if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst &&
Evan Cheng2578ba22009-07-01 01:59:31 +00002294 !MI.findRegisterUseOperand(Src)->isUndef()) {
Lang Hames87e3bca2009-05-06 02:36:21 +00002295 ++NumDCE;
Chris Lattner6456d382009-08-23 03:20:44 +00002296 DEBUG(errs() << "Removing now-noop copy: " << MI);
Lang Hames87e3bca2009-05-06 02:36:21 +00002297 SmallVector<unsigned, 2> KillRegs;
Evan Cheng427a6b62009-05-15 06:48:19 +00002298 InvalidateKills(MI, TRI, RegKills, KillOps, &KillRegs);
Lang Hames87e3bca2009-05-06 02:36:21 +00002299 if (MO.isDead() && !KillRegs.empty()) {
2300 // Source register or an implicit super/sub-register use is killed.
2301 assert(KillRegs[0] == Dst ||
2302 TRI->isSubRegister(KillRegs[0], Dst) ||
2303 TRI->isSuperRegister(KillRegs[0], Dst));
2304 // Last def is now dead.
Evan Chengeca24fb2009-05-12 23:07:00 +00002305 TransferDeadness(&MBB, Dist, Src, RegKills, KillOps, VRM);
Lang Hames87e3bca2009-05-06 02:36:21 +00002306 }
2307 VRM.RemoveMachineInstrFromMaps(&MI);
2308 MBB.erase(&MI);
2309 Erased = true;
2310 Spills.disallowClobberPhysReg(VirtReg);
2311 goto ProcessNextInst;
2312 }
Evan Cheng2578ba22009-07-01 01:59:31 +00002313
Lang Hames87e3bca2009-05-06 02:36:21 +00002314 // If it's not a no-op copy, it clobbers the value in the destreg.
2315 Spills.ClobberPhysReg(VirtReg);
2316 ReusedOperands.markClobbered(VirtReg);
2317
2318 // Check to see if this instruction is a load from a stack slot into
2319 // a register. If so, this provides the stack slot value in the reg.
2320 int FrameIdx;
2321 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
2322 assert(DestReg == VirtReg && "Unknown load situation!");
2323
2324 // If it is a folded reference, then it's not safe to clobber.
2325 bool Folded = FoldedSS.count(FrameIdx);
2326 // Otherwise, if it wasn't available, remember that it is now!
2327 Spills.addAvailable(FrameIdx, DestReg, !Folded);
2328 goto ProcessNextInst;
2329 }
2330
2331 continue;
2332 }
2333
2334 unsigned SubIdx = MO.getSubReg();
2335 bool DoReMat = VRM.isReMaterialized(VirtReg);
2336 if (DoReMat)
2337 ReMatDefs.insert(&MI);
2338
2339 // The only vregs left are stack slot definitions.
2340 int StackSlot = VRM.getStackSlot(VirtReg);
2341 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
2342
2343 // If this def is part of a two-address operand, make sure to execute
2344 // the store from the correct physical register.
2345 unsigned PhysReg;
2346 unsigned TiedOp;
2347 if (MI.isRegTiedToUseOperand(i, &TiedOp)) {
2348 PhysReg = MI.getOperand(TiedOp).getReg();
2349 if (SubIdx) {
2350 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
2351 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
2352 "Can't find corresponding super-register!");
2353 PhysReg = SuperReg;
2354 }
2355 } else {
2356 PhysReg = VRM.getPhys(VirtReg);
2357 if (ReusedOperands.isClobbered(PhysReg)) {
2358 // Another def has taken the assigned physreg. It must have been a
2359 // use&def which got it due to reuse. Undo the reuse!
Evan Cheng5d885022009-07-21 09:15:00 +00002360 PhysReg = ReusedOperands.GetRegForReload(VirtReg, PhysReg, &MI,
2361 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Lang Hames87e3bca2009-05-06 02:36:21 +00002362 }
2363 }
2364
2365 assert(PhysReg && "VR not assigned a physical register?");
2366 RegInfo->setPhysRegUsed(PhysReg);
2367 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
2368 ReusedOperands.markClobbered(RReg);
2369 MI.getOperand(i).setReg(RReg);
2370 MI.getOperand(i).setSubReg(0);
2371
2372 if (!MO.isDead()) {
2373 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
2374 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true,
2375 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
2376 NextMII = next(MII);
2377
2378 // Check to see if this is a noop copy. If so, eliminate the
2379 // instruction before considering the dest reg to be changed.
2380 {
2381 unsigned Src, Dst, SrcSR, DstSR;
Evan Chenga5dc45e2009-10-26 04:56:07 +00002382 if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) {
Lang Hames87e3bca2009-05-06 02:36:21 +00002383 ++NumDCE;
Chris Lattner6456d382009-08-23 03:20:44 +00002384 DEBUG(errs() << "Removing now-noop copy: " << MI);
Evan Cheng427a6b62009-05-15 06:48:19 +00002385 InvalidateKills(MI, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00002386 VRM.RemoveMachineInstrFromMaps(&MI);
2387 MBB.erase(&MI);
2388 Erased = true;
Evan Cheng427a6b62009-05-15 06:48:19 +00002389 UpdateKills(*LastStore, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00002390 goto ProcessNextInst;
2391 }
2392 }
2393 }
2394 }
2395 ProcessNextInst:
Evan Cheng52484682009-07-18 02:10:10 +00002396 // Delete dead instructions without side effects.
Dale Johannesen3a6b9eb2009-10-12 18:49:00 +00002397 if (!Erased && !BackTracked && isSafeToDelete(MI)) {
Evan Cheng52484682009-07-18 02:10:10 +00002398 InvalidateKills(MI, TRI, RegKills, KillOps);
2399 VRM.RemoveMachineInstrFromMaps(&MI);
2400 MBB.erase(&MI);
2401 Erased = true;
2402 }
2403 if (!Erased)
2404 DistanceMap.insert(std::make_pair(&MI, Dist++));
Lang Hames87e3bca2009-05-06 02:36:21 +00002405 if (!Erased && !BackTracked) {
2406 for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II)
Evan Cheng427a6b62009-05-15 06:48:19 +00002407 UpdateKills(*II, TRI, RegKills, KillOps);
Lang Hames87e3bca2009-05-06 02:36:21 +00002408 }
2409 MII = NextMII;
2410 }
2411
2412 }
2413
2414};
2415
Dan Gohman7db949d2009-08-07 01:32:21 +00002416}
2417
Lang Hames87e3bca2009-05-06 02:36:21 +00002418llvm::VirtRegRewriter* llvm::createVirtRegRewriter() {
2419 switch (RewriterOpt) {
Torok Edwinc23197a2009-07-14 16:55:14 +00002420 default: llvm_unreachable("Unreachable!");
Lang Hames87e3bca2009-05-06 02:36:21 +00002421 case local:
2422 return new LocalRewriter();
Lang Hamesf41538d2009-06-02 16:53:25 +00002423 case trivial:
2424 return new TrivialRewriter();
Lang Hames87e3bca2009-05-06 02:36:21 +00002425 }
2426}