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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00007//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements a virtual register map. This maps virtual registers to
11// physical registers and virtual registers to stack slots. It is created and
12// updated by a register allocator and then used by a machine code rewriter that
13// adds spill code and rewrites virtual into physical register references.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000014//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_VIRTREGMAP_H
18#define LLVM_CODEGEN_VIRTREGMAP_H
19
Owen Anderson49c8aa02009-03-13 05:55:11 +000020#include "llvm/CodeGen/MachineFunctionPass.h"
Lang Hames86511252009-09-04 20:41:11 +000021#include "llvm/CodeGen/LiveInterval.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000022#include "llvm/Target/TargetRegisterInfo.h"
Evan Cheng4cce6b42008-04-11 17:53:36 +000023#include "llvm/ADT/BitVector.h"
Evan Chengc781a242009-05-03 18:32:42 +000024#include "llvm/ADT/DenseMap.h"
Chris Lattner94c002a2007-02-01 05:32:05 +000025#include "llvm/ADT/IndexedMap.h"
Evan Chengd3653122008-02-27 03:04:06 +000026#include "llvm/ADT/SmallPtrSet.h"
Dan Gohmand68a0762009-01-05 17:59:02 +000027#include "llvm/ADT/SmallVector.h"
Alkis Evlogimenos5f375022004-03-01 20:05:10 +000028#include <map>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000029
30namespace llvm {
Evan Chengc781a242009-05-03 18:32:42 +000031 class LiveIntervals;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000032 class MachineInstr;
David Greene7e231462007-08-07 16:34:05 +000033 class MachineFunction;
Evan Cheng90f95f82009-06-14 20:22:55 +000034 class MachineRegisterInfo;
Chris Lattner29268692006-09-05 02:12:02 +000035 class TargetInstrInfo;
Mike Stumpfe095f32009-05-04 18:40:41 +000036 class TargetRegisterInfo;
Daniel Dunbar1cd1d982009-07-24 10:36:58 +000037 class raw_ostream;
Jakob Stoklund Olesenba05c012011-02-18 22:03:18 +000038 class SlotIndexes;
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000039
Owen Anderson49c8aa02009-03-13 05:55:11 +000040 class VirtRegMap : public MachineFunctionPass {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000041 public:
Evan Cheng2638e1a2007-03-20 08:13:50 +000042 enum {
43 NO_PHYS_REG = 0,
Evan Cheng91935142007-04-04 07:40:01 +000044 NO_STACK_SLOT = (1L << 30)-1,
45 MAX_STACK_SLOT = (1L << 18)-1
Evan Cheng2638e1a2007-03-20 08:13:50 +000046 };
47
Chris Lattner35f27052006-05-01 21:16:03 +000048 enum ModRef { isRef = 1, isMod = 2, isModRef = 3 };
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000049 typedef std::multimap<MachineInstr*,
50 std::pair<unsigned, ModRef> > MI2VirtMapTy;
Alkis Evlogimenos5f375022004-03-01 20:05:10 +000051
Chris Lattner8c4d88d2004-09-30 01:54:45 +000052 private:
Evan Cheng90f95f82009-06-14 20:22:55 +000053 MachineRegisterInfo *MRI;
Owen Anderson49c8aa02009-03-13 05:55:11 +000054 const TargetInstrInfo *TII;
Mike Stumpfe095f32009-05-04 18:40:41 +000055 const TargetRegisterInfo *TRI;
Owen Anderson49c8aa02009-03-13 05:55:11 +000056 MachineFunction *MF;
Mike Stumpfe095f32009-05-04 18:40:41 +000057
58 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs;
59
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +000060 /// Virt2PhysMap - This is a virtual to physical register
61 /// mapping. Each virtual register is required to have an entry in
62 /// it; even spilled virtual registers (the register mapped to a
63 /// spilled register is the temporary used to load it from the
64 /// stack).
Chris Lattner94c002a2007-02-01 05:32:05 +000065 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap;
Evan Cheng81a03822007-11-17 00:40:40 +000066
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +000067 /// Virt2StackSlotMap - This is virtual register to stack slot
68 /// mapping. Each spilled virtual register has an entry in it
69 /// which corresponds to the stack slot this register is spilled
70 /// at.
Chris Lattner94c002a2007-02-01 05:32:05 +000071 IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
Evan Cheng81a03822007-11-17 00:40:40 +000072
Dan Gohman39e33ac2008-03-12 20:50:04 +000073 /// Virt2ReMatIdMap - This is virtual register to rematerialization id
Evan Cheng81a03822007-11-17 00:40:40 +000074 /// mapping. Each spilled virtual register that should be remat'd has an
75 /// entry in it which corresponds to the remat id.
Evan Cheng549f27d32007-08-13 23:45:17 +000076 IndexedMap<int, VirtReg2IndexFunctor> Virt2ReMatIdMap;
Evan Cheng81a03822007-11-17 00:40:40 +000077
78 /// Virt2SplitMap - This is virtual register to splitted virtual register
79 /// mapping.
80 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
81
Evan Chengadf85902007-12-05 09:51:10 +000082 /// Virt2SplitKillMap - This is splitted virtual register to its last use
Evan Chengd120ffd2007-12-05 10:24:35 +000083 /// (kill) index mapping.
Jakob Stoklund Olesen2cfa5b42011-01-09 18:58:33 +000084 IndexedMap<SlotIndex, VirtReg2IndexFunctor> Virt2SplitKillMap;
Evan Chengadf85902007-12-05 09:51:10 +000085
Evan Cheng81a03822007-11-17 00:40:40 +000086 /// ReMatMap - This is virtual register to re-materialized instruction
87 /// mapping. Each virtual register whose definition is going to be
88 /// re-materialized has an entry in it.
89 IndexedMap<MachineInstr*, VirtReg2IndexFunctor> ReMatMap;
90
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +000091 /// MI2VirtMap - This is MachineInstr to virtual register
92 /// mapping. In the case of memory spill code being folded into
93 /// instructions, we need to know which virtual register was
94 /// read/written by this instruction.
Chris Lattner7f690e62004-09-30 02:15:18 +000095 MI2VirtMapTy MI2VirtMap;
Misha Brukmanedf128a2005-04-21 22:36:52 +000096
Evan Cheng81a03822007-11-17 00:40:40 +000097 /// SpillPt2VirtMap - This records the virtual registers which should
98 /// be spilled right after the MachineInstr due to live interval
99 /// splitting.
Evan Chengb50bb8c2007-12-05 08:16:32 +0000100 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >
101 SpillPt2VirtMap;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000102
Evan Cheng0cbb1162007-11-29 01:06:25 +0000103 /// RestorePt2VirtMap - This records the virtual registers which should
104 /// be restored right before the MachineInstr due to live interval
105 /// splitting.
106 std::map<MachineInstr*, std::vector<unsigned> > RestorePt2VirtMap;
107
Evan Cheng676dd7c2008-03-11 07:19:34 +0000108 /// EmergencySpillMap - This records the physical registers that should
109 /// be spilled / restored around the MachineInstr since the register
110 /// allocator has run out of registers.
111 std::map<MachineInstr*, std::vector<unsigned> > EmergencySpillMap;
112
113 /// EmergencySpillSlots - This records emergency spill slots used to
114 /// spill physical registers when the register allocator runs out of
115 /// registers. Ideally only one stack slot is used per function per
116 /// register class.
117 std::map<const TargetRegisterClass*, int> EmergencySpillSlots;
118
Evan Cheng2638e1a2007-03-20 08:13:50 +0000119 /// ReMatId - Instead of assigning a stack slot to a to be rematerialized
Evan Cheng91935142007-04-04 07:40:01 +0000120 /// virtual register, an unique id is being assigned. This keeps track of
Evan Cheng2638e1a2007-03-20 08:13:50 +0000121 /// the highest id used so far. Note, this starts at (1<<18) to avoid
122 /// conflicts with stack slot numbers.
123 int ReMatId;
124
Evan Chengd3653122008-02-27 03:04:06 +0000125 /// LowSpillSlot, HighSpillSlot - Lowest and highest spill slot indexes.
126 int LowSpillSlot, HighSpillSlot;
127
128 /// SpillSlotToUsesMap - Records uses for each register spill slot.
129 SmallVector<SmallPtrSet<MachineInstr*, 4>, 8> SpillSlotToUsesMap;
130
Evan Cheng4cce6b42008-04-11 17:53:36 +0000131 /// ImplicitDefed - One bit for each virtual register. If set it indicates
132 /// the register is implicitly defined.
133 BitVector ImplicitDefed;
134
Evan Chengc781a242009-05-03 18:32:42 +0000135 /// UnusedRegs - A list of physical registers that have not been used.
136 BitVector UnusedRegs;
137
Jakob Stoklund Olesenb55e91e2010-11-16 00:41:01 +0000138 /// createSpillSlot - Allocate a spill slot for RC from MFI.
139 unsigned createSpillSlot(const TargetRegisterClass *RC);
140
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000141 VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT
142 void operator=(const VirtRegMap&); // DO NOT IMPLEMENT
Alkis Evlogimenos79742872004-02-23 23:47:10 +0000143
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000144 public:
Owen Anderson49c8aa02009-03-13 05:55:11 +0000145 static char ID;
Owen Anderson90c579d2010-08-06 18:33:48 +0000146 VirtRegMap() : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG),
Owen Anderson49c8aa02009-03-13 05:55:11 +0000147 Virt2StackSlotMap(NO_STACK_SLOT),
148 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
Lang Hames233a60e2009-11-03 23:52:08 +0000149 Virt2SplitKillMap(SlotIndex()), ReMatMap(NULL),
Owen Anderson49c8aa02009-03-13 05:55:11 +0000150 ReMatId(MAX_STACK_SLOT+1),
151 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { }
152 virtual bool runOnMachineFunction(MachineFunction &MF);
153
154 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
155 AU.setPreservesAll();
156 MachineFunctionPass::getAnalysisUsage(AU);
157 }
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000158
Jakob Stoklund Olesenf0179002010-07-26 23:44:11 +0000159 MachineFunction &getMachineFunction() const {
Jakob Stoklund Olesenc9672cb2010-12-10 18:36:02 +0000160 assert(MF && "getMachineFunction called before runOnMachineFunction");
Jakob Stoklund Olesenf0179002010-07-26 23:44:11 +0000161 return *MF;
162 }
163
Jakob Stoklund Olesenc9672cb2010-12-10 18:36:02 +0000164 MachineRegisterInfo &getRegInfo() const { return *MRI; }
165 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
166
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000167 void grow();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000168
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000169 /// @brief returns true if the specified virtual register is
170 /// mapped to a physical register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000171 bool hasPhys(unsigned virtReg) const {
172 return getPhys(virtReg) != NO_PHYS_REG;
173 }
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000174
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000175 /// @brief returns the physical register mapped to the specified
176 /// virtual register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000177 unsigned getPhys(unsigned virtReg) const {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000178 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000179 return Virt2PhysMap[virtReg];
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000180 }
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000181
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000182 /// @brief creates a mapping for the specified virtual register to
183 /// the specified physical register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000184 void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000185 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
186 TargetRegisterInfo::isPhysicalRegister(physReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000187 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000188 "attempt to assign physical register to already mapped "
189 "virtual register");
Chris Lattner7f690e62004-09-30 02:15:18 +0000190 Virt2PhysMap[virtReg] = physReg;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000191 }
192
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000193 /// @brief clears the specified virtual register's, physical
194 /// register mapping
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000195 void clearVirt(unsigned virtReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000196 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000197 assert(Virt2PhysMap[virtReg] != NO_PHYS_REG &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000198 "attempt to clear a not assigned virtual register");
Chris Lattner7f690e62004-09-30 02:15:18 +0000199 Virt2PhysMap[virtReg] = NO_PHYS_REG;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000200 }
201
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000202 /// @brief clears all virtual to physical register mappings
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000203 void clearAllVirt() {
Chris Lattner7f690e62004-09-30 02:15:18 +0000204 Virt2PhysMap.clear();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000205 grow();
206 }
207
Evan Cheng90f95f82009-06-14 20:22:55 +0000208 /// @brief returns the register allocation preference.
209 unsigned getRegAllocPref(unsigned virtReg);
210
Evan Cheng81a03822007-11-17 00:40:40 +0000211 /// @brief records virtReg is a split live interval from SReg.
212 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
213 Virt2SplitMap[virtReg] = SReg;
214 }
215
216 /// @brief returns the live interval virtReg is split from.
217 unsigned getPreSplitReg(unsigned virtReg) {
218 return Virt2SplitMap[virtReg];
219 }
220
Dan Gohman39e33ac2008-03-12 20:50:04 +0000221 /// @brief returns true if the specified virtual register is not
Evan Cheng549f27d32007-08-13 23:45:17 +0000222 /// mapped to a stack slot or rematerialized.
223 bool isAssignedReg(unsigned virtReg) const {
Evan Cheng81a03822007-11-17 00:40:40 +0000224 if (getStackSlot(virtReg) == NO_STACK_SLOT &&
225 getReMatId(virtReg) == NO_STACK_SLOT)
226 return true;
227 // Split register can be assigned a physical register as well as a
228 // stack slot or remat id.
229 return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] != NO_PHYS_REG);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000230 }
231
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000232 /// @brief returns the stack slot mapped to the specified virtual
233 /// register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000234 int getStackSlot(unsigned virtReg) const {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000235 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000236 return Virt2StackSlotMap[virtReg];
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000237 }
238
Evan Cheng549f27d32007-08-13 23:45:17 +0000239 /// @brief returns the rematerialization id mapped to the specified virtual
240 /// register
241 int getReMatId(unsigned virtReg) const {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000242 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000243 return Virt2ReMatIdMap[virtReg];
244 }
245
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000246 /// @brief create a mapping for the specifed virtual register to
247 /// the next available stack slot
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000248 int assignVirt2StackSlot(unsigned virtReg);
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000249 /// @brief create a mapping for the specified virtual register to
250 /// the specified stack slot
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000251 void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
252
Evan Cheng2638e1a2007-03-20 08:13:50 +0000253 /// @brief assign an unique re-materialization id to the specified
254 /// virtual register.
255 int assignVirtReMatId(unsigned virtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000256 /// @brief assign an unique re-materialization id to the specified
257 /// virtual register.
258 void assignVirtReMatId(unsigned virtReg, int id);
Evan Cheng2638e1a2007-03-20 08:13:50 +0000259
260 /// @brief returns true if the specified virtual register is being
261 /// re-materialized.
262 bool isReMaterialized(unsigned virtReg) const {
Evan Cheng549f27d32007-08-13 23:45:17 +0000263 return ReMatMap[virtReg] != NULL;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000264 }
265
266 /// @brief returns the original machine instruction being re-issued
267 /// to re-materialize the specified virtual register.
Evan Cheng549f27d32007-08-13 23:45:17 +0000268 MachineInstr *getReMaterializedMI(unsigned virtReg) const {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000269 return ReMatMap[virtReg];
270 }
271
272 /// @brief records the specified virtual register will be
273 /// re-materialized and the original instruction which will be re-issed
Evan Cheng549f27d32007-08-13 23:45:17 +0000274 /// for this purpose. If parameter all is true, then all uses of the
275 /// registers are rematerialized and it's safe to delete the definition.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000276 void setVirtIsReMaterialized(unsigned virtReg, MachineInstr *def) {
277 ReMatMap[virtReg] = def;
278 }
279
Evan Chengadf85902007-12-05 09:51:10 +0000280 /// @brief record the last use (kill) of a split virtual register.
Lang Hames233a60e2009-11-03 23:52:08 +0000281 void addKillPoint(unsigned virtReg, SlotIndex index) {
Evan Chengd120ffd2007-12-05 10:24:35 +0000282 Virt2SplitKillMap[virtReg] = index;
Evan Chengadf85902007-12-05 09:51:10 +0000283 }
284
Lang Hames233a60e2009-11-03 23:52:08 +0000285 SlotIndex getKillPoint(unsigned virtReg) const {
Evan Chengd120ffd2007-12-05 10:24:35 +0000286 return Virt2SplitKillMap[virtReg];
287 }
288
289 /// @brief remove the last use (kill) of a split virtual register.
Evan Chengadf85902007-12-05 09:51:10 +0000290 void removeKillPoint(unsigned virtReg) {
Lang Hames233a60e2009-11-03 23:52:08 +0000291 Virt2SplitKillMap[virtReg] = SlotIndex();
Evan Chengadf85902007-12-05 09:51:10 +0000292 }
293
Evan Chengcada2452007-11-28 01:28:46 +0000294 /// @brief returns true if the specified MachineInstr is a spill point.
295 bool isSpillPt(MachineInstr *Pt) const {
296 return SpillPt2VirtMap.find(Pt) != SpillPt2VirtMap.end();
297 }
298
Evan Cheng81a03822007-11-17 00:40:40 +0000299 /// @brief returns the virtual registers that should be spilled due to
300 /// splitting right after the specified MachineInstr.
Evan Chengb50bb8c2007-12-05 08:16:32 +0000301 std::vector<std::pair<unsigned,bool> > &getSpillPtSpills(MachineInstr *Pt) {
Evan Cheng81a03822007-11-17 00:40:40 +0000302 return SpillPt2VirtMap[Pt];
303 }
304
305 /// @brief records the specified MachineInstr as a spill point for virtReg.
Evan Chengb50bb8c2007-12-05 08:16:32 +0000306 void addSpillPoint(unsigned virtReg, bool isKill, MachineInstr *Pt) {
Evan Chengc781a242009-05-03 18:32:42 +0000307 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >::iterator
308 I = SpillPt2VirtMap.find(Pt);
309 if (I != SpillPt2VirtMap.end())
310 I->second.push_back(std::make_pair(virtReg, isKill));
Evan Chengcada2452007-11-28 01:28:46 +0000311 else {
Evan Chengb50bb8c2007-12-05 08:16:32 +0000312 std::vector<std::pair<unsigned,bool> > Virts;
313 Virts.push_back(std::make_pair(virtReg, isKill));
Evan Chengcada2452007-11-28 01:28:46 +0000314 SpillPt2VirtMap.insert(std::make_pair(Pt, Virts));
315 }
Evan Cheng81a03822007-11-17 00:40:40 +0000316 }
317
Evan Chengc1f53c72008-03-11 21:34:46 +0000318 /// @brief - transfer spill point information from one instruction to
319 /// another.
Evan Cheng81a03822007-11-17 00:40:40 +0000320 void transferSpillPts(MachineInstr *Old, MachineInstr *New) {
Evan Chengc781a242009-05-03 18:32:42 +0000321 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >::iterator
Evan Chengb50bb8c2007-12-05 08:16:32 +0000322 I = SpillPt2VirtMap.find(Old);
Evan Chengcada2452007-11-28 01:28:46 +0000323 if (I == SpillPt2VirtMap.end())
324 return;
325 while (!I->second.empty()) {
Evan Chengb50bb8c2007-12-05 08:16:32 +0000326 unsigned virtReg = I->second.back().first;
327 bool isKill = I->second.back().second;
Evan Chengcada2452007-11-28 01:28:46 +0000328 I->second.pop_back();
Evan Chengb50bb8c2007-12-05 08:16:32 +0000329 addSpillPoint(virtReg, isKill, New);
Evan Cheng81a03822007-11-17 00:40:40 +0000330 }
Evan Chengcada2452007-11-28 01:28:46 +0000331 SpillPt2VirtMap.erase(I);
Evan Cheng81a03822007-11-17 00:40:40 +0000332 }
333
Evan Cheng0cbb1162007-11-29 01:06:25 +0000334 /// @brief returns true if the specified MachineInstr is a restore point.
335 bool isRestorePt(MachineInstr *Pt) const {
336 return RestorePt2VirtMap.find(Pt) != RestorePt2VirtMap.end();
337 }
338
339 /// @brief returns the virtual registers that should be restoreed due to
340 /// splitting right after the specified MachineInstr.
341 std::vector<unsigned> &getRestorePtRestores(MachineInstr *Pt) {
342 return RestorePt2VirtMap[Pt];
343 }
344
345 /// @brief records the specified MachineInstr as a restore point for virtReg.
346 void addRestorePoint(unsigned virtReg, MachineInstr *Pt) {
Evan Chengc781a242009-05-03 18:32:42 +0000347 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
348 RestorePt2VirtMap.find(Pt);
349 if (I != RestorePt2VirtMap.end())
350 I->second.push_back(virtReg);
Evan Cheng0cbb1162007-11-29 01:06:25 +0000351 else {
352 std::vector<unsigned> Virts;
353 Virts.push_back(virtReg);
354 RestorePt2VirtMap.insert(std::make_pair(Pt, Virts));
355 }
356 }
357
Evan Cheng676dd7c2008-03-11 07:19:34 +0000358 /// @brief - transfer restore point information from one instruction to
359 /// another.
Evan Cheng0cbb1162007-11-29 01:06:25 +0000360 void transferRestorePts(MachineInstr *Old, MachineInstr *New) {
Evan Chengc781a242009-05-03 18:32:42 +0000361 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
Evan Cheng0cbb1162007-11-29 01:06:25 +0000362 RestorePt2VirtMap.find(Old);
363 if (I == RestorePt2VirtMap.end())
364 return;
365 while (!I->second.empty()) {
366 unsigned virtReg = I->second.back();
367 I->second.pop_back();
368 addRestorePoint(virtReg, New);
369 }
370 RestorePt2VirtMap.erase(I);
371 }
372
Evan Cheng676dd7c2008-03-11 07:19:34 +0000373 /// @brief records that the specified physical register must be spilled
374 /// around the specified machine instr.
375 void addEmergencySpill(unsigned PhysReg, MachineInstr *MI) {
376 if (EmergencySpillMap.find(MI) != EmergencySpillMap.end())
377 EmergencySpillMap[MI].push_back(PhysReg);
378 else {
379 std::vector<unsigned> PhysRegs;
380 PhysRegs.push_back(PhysReg);
381 EmergencySpillMap.insert(std::make_pair(MI, PhysRegs));
382 }
383 }
384
385 /// @brief returns true if one or more physical registers must be spilled
386 /// around the specified instruction.
387 bool hasEmergencySpills(MachineInstr *MI) const {
388 return EmergencySpillMap.find(MI) != EmergencySpillMap.end();
389 }
390
391 /// @brief returns the physical registers to be spilled and restored around
392 /// the instruction.
393 std::vector<unsigned> &getEmergencySpills(MachineInstr *MI) {
394 return EmergencySpillMap[MI];
395 }
396
Evan Chengc1f53c72008-03-11 21:34:46 +0000397 /// @brief - transfer emergency spill information from one instruction to
398 /// another.
399 void transferEmergencySpills(MachineInstr *Old, MachineInstr *New) {
400 std::map<MachineInstr*,std::vector<unsigned> >::iterator I =
401 EmergencySpillMap.find(Old);
402 if (I == EmergencySpillMap.end())
403 return;
404 while (!I->second.empty()) {
405 unsigned virtReg = I->second.back();
406 I->second.pop_back();
407 addEmergencySpill(virtReg, New);
408 }
409 EmergencySpillMap.erase(I);
410 }
411
Evan Cheng676dd7c2008-03-11 07:19:34 +0000412 /// @brief return or get a emergency spill slot for the register class.
413 int getEmergencySpillSlot(const TargetRegisterClass *RC);
414
Evan Chengd3653122008-02-27 03:04:06 +0000415 /// @brief Return lowest spill slot index.
416 int getLowSpillSlot() const {
417 return LowSpillSlot;
418 }
419
420 /// @brief Return highest spill slot index.
421 int getHighSpillSlot() const {
422 return HighSpillSlot;
423 }
424
425 /// @brief Records a spill slot use.
426 void addSpillSlotUse(int FrameIndex, MachineInstr *MI);
427
428 /// @brief Returns true if spill slot has been used.
429 bool isSpillSlotUsed(int FrameIndex) const {
430 assert(FrameIndex >= 0 && "Spill slot index should not be negative!");
431 return !SpillSlotToUsesMap[FrameIndex-LowSpillSlot].empty();
432 }
433
Evan Cheng4cce6b42008-04-11 17:53:36 +0000434 /// @brief Mark the specified register as being implicitly defined.
435 void setIsImplicitlyDefined(unsigned VirtReg) {
Jakob Stoklund Olesenc7d67f92011-01-08 23:11:07 +0000436 ImplicitDefed.set(TargetRegisterInfo::virtReg2Index(VirtReg));
Evan Cheng4cce6b42008-04-11 17:53:36 +0000437 }
438
439 /// @brief Returns true if the virtual register is implicitly defined.
440 bool isImplicitlyDefined(unsigned VirtReg) const {
Jakob Stoklund Olesenc7d67f92011-01-08 23:11:07 +0000441 return ImplicitDefed[TargetRegisterInfo::virtReg2Index(VirtReg)];
Evan Cheng4cce6b42008-04-11 17:53:36 +0000442 }
443
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000444 /// @brief Updates information about the specified virtual register's value
Evan Chengaee4af62007-12-02 08:30:39 +0000445 /// folded into newMI machine instruction.
446 void virtFolded(unsigned VirtReg, MachineInstr *OldMI, MachineInstr *NewMI,
447 ModRef MRInfo);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000448
Evan Cheng7f566252007-10-13 02:50:24 +0000449 /// @brief Updates information about the specified virtual register's value
450 /// folded into the specified machine instruction.
451 void virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo);
452
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000453 /// @brief returns the virtual registers' values folded in memory
454 /// operands of this instruction
Chris Lattner7f690e62004-09-30 02:15:18 +0000455 std::pair<MI2VirtMapTy::const_iterator, MI2VirtMapTy::const_iterator>
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000456 getFoldedVirts(MachineInstr* MI) const {
Chris Lattner7f690e62004-09-30 02:15:18 +0000457 return MI2VirtMap.equal_range(MI);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000458 }
Chris Lattner35f27052006-05-01 21:16:03 +0000459
Evan Chengcada2452007-11-28 01:28:46 +0000460 /// RemoveMachineInstrFromMaps - MI is being erased, remove it from the
461 /// the folded instruction map and spill point map.
Evan Chengd3653122008-02-27 03:04:06 +0000462 void RemoveMachineInstrFromMaps(MachineInstr *MI);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000463
Evan Chengc781a242009-05-03 18:32:42 +0000464 /// FindUnusedRegisters - Gather a list of allocatable registers that
465 /// have not been allocated to any virtual register.
Evan Cheng90f95f82009-06-14 20:22:55 +0000466 bool FindUnusedRegisters(LiveIntervals* LIs);
Evan Chengc781a242009-05-03 18:32:42 +0000467
468 /// HasUnusedRegisters - Return true if there are any allocatable registers
469 /// that have not been allocated to any virtual register.
470 bool HasUnusedRegisters() const {
471 return !UnusedRegs.none();
472 }
473
474 /// setRegisterUsed - Remember the physical register is now used.
475 void setRegisterUsed(unsigned Reg) {
476 UnusedRegs.reset(Reg);
477 }
478
479 /// isRegisterUnused - Return true if the physical register has not been
480 /// used.
481 bool isRegisterUnused(unsigned Reg) const {
482 return UnusedRegs[Reg];
483 }
484
485 /// getFirstUnusedRegister - Return the first physical register that has not
486 /// been used.
487 unsigned getFirstUnusedRegister(const TargetRegisterClass *RC) {
488 int Reg = UnusedRegs.find_first();
489 while (Reg != -1) {
Mike Stumpfe095f32009-05-04 18:40:41 +0000490 if (allocatableRCRegs[RC][Reg])
Evan Chengc781a242009-05-03 18:32:42 +0000491 return (unsigned)Reg;
492 Reg = UnusedRegs.find_next(Reg);
493 }
494 return 0;
495 }
496
Jakob Stoklund Olesenba05c012011-02-18 22:03:18 +0000497 /// rewrite - Rewrite all instructions in MF to use only physical registers
498 /// by mapping all virtual register operands to their assigned physical
499 /// registers.
500 ///
501 /// @param Indexes Optionally remove deleted instructions from indexes.
502 void rewrite(SlotIndexes *Indexes);
503
Daniel Dunbar1cd1d982009-07-24 10:36:58 +0000504 void print(raw_ostream &OS, const Module* M = 0) const;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000505 void dump() const;
506 };
507
Daniel Dunbar1cd1d982009-07-24 10:36:58 +0000508 inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
509 VRM.print(OS);
510 return OS;
511 }
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000512} // End llvm namespace
513
514#endif