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Misha Brukman2a8350a2005-02-05 02:24:26 +00001//===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===//
Andrew Lenharth304d0f32005-01-22 23:41:55 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13// Get the target-independent interfaces which we are implementing...
14//
15include "../Target.td"
16
17//Alpha is little endian
18
19//===----------------------------------------------------------------------===//
Chris Lattner5882e402005-10-23 22:08:45 +000020// Subtarget Features
21//===----------------------------------------------------------------------===//
22
23def FeatureCIX : SubtargetFeature<"CIX", "Enable CIX extentions">;
24def FeatureFIX : SubtargetFeature<"FIX", "Enable FIX extentions">;
25
26//===----------------------------------------------------------------------===//
Andrew Lenharth304d0f32005-01-22 23:41:55 +000027// Register File Description
28//===----------------------------------------------------------------------===//
29
30include "AlphaRegisterInfo.td"
31
32//===----------------------------------------------------------------------===//
33// Instruction Descriptions
34//===----------------------------------------------------------------------===//
35
36include "AlphaInstrInfo.td"
37
38def AlphaInstrInfo : InstrInfo {
39 let PHIInst = PHI;
40
41 // Define how we want to layout our target-specific information field.
42 // let TSFlagsFields = [];
43 // let TSFlagsShifts = [];
44}
45
Chris Lattner5882e402005-10-23 22:08:45 +000046//===----------------------------------------------------------------------===//
47// Alpha Processor Definitions
48//===----------------------------------------------------------------------===//
49
50def : Processor<"generic", NoItineraries, []>;
51def : Processor<"pca56" , NoItineraries, []>;
52def : Processor<"ev56" , NoItineraries, []>;
53def : Processor<"ev6" , NoItineraries, [FeatureFIX]>;
54def : Processor<"ev67" , NoItineraries, [FeatureFIX, FeatureCIX]>;
55
56//===----------------------------------------------------------------------===//
57// The Alpha Target
58//===----------------------------------------------------------------------===//
59
60
Andrew Lenharth304d0f32005-01-22 23:41:55 +000061def Alpha : Target {
62 // Pointers on Alpha are 64-bits in size.
63 let PointerType = i64;
64
65 let CalleeSavedRegisters =
66 //saved regs
67 [R9, R10, R11, R12, R13, R14,
68 //Frame pointer
Andrew Lenharth2513ddc2005-04-05 20:51:46 +000069// R15,
Andrew Lenharth304d0f32005-01-22 23:41:55 +000070 //return address
Andrew Lenharth3f5aa1c2005-06-23 23:42:05 +000071// R26,
Andrew Lenharth304d0f32005-01-22 23:41:55 +000072 //Stack Pointer
Andrew Lenharth2513ddc2005-04-05 20:51:46 +000073// R30,
Andrew Lenharth304d0f32005-01-22 23:41:55 +000074 F2, F3, F4, F5, F6, F7, F8, F9];
75
76 // Pull in Instruction Info:
77 let InstructionSet = AlphaInstrInfo;
78}