Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 1 | //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 2 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 7 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 10 | // This file contains the PowerPC implementation of the MRegisterInfo class. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #define DEBUG_TYPE "reginfo" |
Chris Lattner | 2668959 | 2005-10-14 23:51:18 +0000 | [diff] [blame] | 15 | #include "PPC.h" |
Chris Lattner | 26bd0d4 | 2005-10-14 23:45:43 +0000 | [diff] [blame] | 16 | #include "PPCInstrBuilder.h" |
Chris Lattner | 16e71f2 | 2005-10-14 23:59:06 +0000 | [diff] [blame] | 17 | #include "PPCRegisterInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 18 | #include "llvm/Constants.h" |
| 19 | #include "llvm/Type.h" |
| 20 | #include "llvm/CodeGen/ValueTypes.h" |
| 21 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineDebugInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineFunction.h" |
| 24 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineLocation.h" |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/SelectionDAGNodes.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 27 | #include "llvm/Target/TargetFrameInfo.h" |
| 28 | #include "llvm/Target/TargetMachine.h" |
| 29 | #include "llvm/Target/TargetOptions.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 30 | #include "llvm/Support/CommandLine.h" |
| 31 | #include "llvm/Support/Debug.h" |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 32 | #include "llvm/Support/MathExtras.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 33 | #include "llvm/ADT/STLExtras.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 34 | #include <cstdlib> |
| 35 | #include <iostream> |
| 36 | using namespace llvm; |
| 37 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 38 | PPCRegisterInfo::PPCRegisterInfo() |
Chris Lattner | 4c7b43b | 2005-10-14 23:37:35 +0000 | [diff] [blame] | 39 | : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 40 | ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 41 | ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; |
| 42 | ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; |
| 43 | ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; |
| 44 | ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; |
| 45 | ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; |
| 46 | ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 47 | ImmToIdxMap[PPC::ADDI] = PPC::ADD4; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 48 | } |
| 49 | |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 50 | void |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 51 | PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
| 52 | MachineBasicBlock::iterator MI, |
| 53 | unsigned SrcReg, int FrameIdx, |
| 54 | const TargetRegisterClass *RC) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 55 | if (SrcReg == PPC::LR) { |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 56 | // FIXME: this spills LR immediately to memory in one step. To do this, we |
| 57 | // use R11, which we know cannot be used in the prolog/epilog. This is a |
| 58 | // hack. |
Chris Lattner | 3f852b4 | 2005-08-18 23:24:50 +0000 | [diff] [blame] | 59 | BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 60 | addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 61 | } else if (RC == PPC::CRRCRegisterClass) { |
Nate Begeman | 7af0248 | 2005-04-12 07:04:16 +0000 | [diff] [blame] | 62 | BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 63 | addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 64 | } else if (RC == PPC::GPRCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 65 | addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 66 | } else if (RC == PPC::G8RCRegisterClass) { |
| 67 | addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); |
| 68 | } else if (RC == PPC::F8RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 69 | addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 70 | } else if (RC == PPC::F4RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 71 | addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 72 | } else if (RC == PPC::VRRCRegisterClass) { |
| 73 | // We don't have indexed addressing for vector loads. Emit: |
| 74 | // R11 = ADDI FI# |
| 75 | // Dest = LVX R0, R11 |
| 76 | // |
| 77 | // FIXME: We use R0 here, because it isn't available for RA. |
| 78 | addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); |
| 79 | BuildMI(MBB, MI, PPC::STVX, 3) |
| 80 | .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 81 | } else { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 82 | assert(0 && "Unknown regclass!"); |
| 83 | abort(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 84 | } |
| 85 | } |
| 86 | |
| 87 | void |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 88 | PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 89 | MachineBasicBlock::iterator MI, |
Chris Lattner | b48d2cf | 2005-09-30 01:31:52 +0000 | [diff] [blame] | 90 | unsigned DestReg, int FrameIdx, |
| 91 | const TargetRegisterClass *RC) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 92 | if (DestReg == PPC::LR) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 93 | addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 94 | BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 95 | } else if (RC == PPC::CRRCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 96 | addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); |
Nate Begeman | 7af0248 | 2005-04-12 07:04:16 +0000 | [diff] [blame] | 97 | BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 98 | } else if (RC == PPC::GPRCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 99 | addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 100 | } else if (RC == PPC::G8RCRegisterClass) { |
| 101 | addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); |
| 102 | } else if (RC == PPC::F8RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 103 | addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 104 | } else if (RC == PPC::F4RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 105 | addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 106 | } else if (RC == PPC::VRRCRegisterClass) { |
| 107 | // We don't have indexed addressing for vector loads. Emit: |
| 108 | // R11 = ADDI FI# |
| 109 | // Dest = LVX R0, R11 |
| 110 | // |
| 111 | // FIXME: We use R0 here, because it isn't available for RA. |
| 112 | addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); |
| 113 | BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 114 | } else { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 115 | assert(0 && "Unknown regclass!"); |
| 116 | abort(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 117 | } |
| 118 | } |
| 119 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 120 | void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 121 | MachineBasicBlock::iterator MI, |
| 122 | unsigned DestReg, unsigned SrcReg, |
| 123 | const TargetRegisterClass *RC) const { |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 124 | if (RC == PPC::GPRCRegisterClass) { |
| 125 | BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg); |
| 126 | } else if (RC == PPC::G8RCRegisterClass) { |
| 127 | BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); |
| 128 | } else if (RC == PPC::F4RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 129 | BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 130 | } else if (RC == PPC::F8RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 131 | BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 132 | } else if (RC == PPC::CRRCRegisterClass) { |
Nate Begeman | 7af0248 | 2005-04-12 07:04:16 +0000 | [diff] [blame] | 133 | BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); |
Chris Lattner | 335fd3c | 2006-03-16 20:03:58 +0000 | [diff] [blame] | 134 | } else if (RC == PPC::VRRCRegisterClass) { |
| 135 | BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); |
Nate Begeman | 7af0248 | 2005-04-12 07:04:16 +0000 | [diff] [blame] | 136 | } else { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 137 | std::cerr << "Attempt to copy register that is not GPR or FPR"; |
| 138 | abort(); |
| 139 | } |
| 140 | } |
| 141 | |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 142 | /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into |
| 143 | /// copy instructions, turning them into load/store instructions. |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 144 | MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, |
| 145 | unsigned OpNum, |
| 146 | int FrameIndex) const { |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 147 | // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because |
| 148 | // it takes more than one instruction to store it. |
| 149 | unsigned Opc = MI->getOpcode(); |
| 150 | |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 151 | if ((Opc == PPC::OR4 && |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 152 | MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { |
| 153 | if (OpNum == 0) { // move -> store |
| 154 | unsigned InReg = MI->getOperand(1).getReg(); |
| 155 | return addFrameReference(BuildMI(PPC::STW, |
| 156 | 3).addReg(InReg), FrameIndex); |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 157 | } else { // move -> load |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 158 | unsigned OutReg = MI->getOperand(0).getReg(); |
| 159 | return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); |
| 160 | } |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 161 | } else if ((Opc == PPC::OR8 && |
| 162 | MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { |
| 163 | if (OpNum == 0) { // move -> store |
| 164 | unsigned InReg = MI->getOperand(1).getReg(); |
| 165 | return addFrameReference(BuildMI(PPC::STD, |
| 166 | 3).addReg(InReg), FrameIndex); |
| 167 | } else { // move -> load |
| 168 | unsigned OutReg = MI->getOperand(0).getReg(); |
| 169 | return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex); |
| 170 | } |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 171 | } else if (Opc == PPC::FMRD) { |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 172 | if (OpNum == 0) { // move -> store |
| 173 | unsigned InReg = MI->getOperand(1).getReg(); |
| 174 | return addFrameReference(BuildMI(PPC::STFD, |
| 175 | 3).addReg(InReg), FrameIndex); |
| 176 | } else { // move -> load |
| 177 | unsigned OutReg = MI->getOperand(0).getReg(); |
| 178 | return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); |
| 179 | } |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 180 | } else if (Opc == PPC::FMRS) { |
| 181 | if (OpNum == 0) { // move -> store |
| 182 | unsigned InReg = MI->getOperand(1).getReg(); |
| 183 | return addFrameReference(BuildMI(PPC::STFS, |
| 184 | 3).addReg(InReg), FrameIndex); |
| 185 | } else { // move -> load |
| 186 | unsigned OutReg = MI->getOperand(0).getReg(); |
| 187 | return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); |
| 188 | } |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 189 | } |
| 190 | return 0; |
| 191 | } |
| 192 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 193 | //===----------------------------------------------------------------------===// |
| 194 | // Stack Frame Processing methods |
| 195 | //===----------------------------------------------------------------------===// |
| 196 | |
| 197 | // hasFP - Return true if the specified function should have a dedicated frame |
| 198 | // pointer register. This is true if the function has variable sized allocas or |
| 199 | // if frame pointer elimination is disabled. |
| 200 | // |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 201 | static bool hasFP(const MachineFunction &MF) { |
| 202 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 203 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 204 | |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 205 | // If frame pointers are forced, or if there are variable sized stack objects, |
| 206 | // use a frame pointer. |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 207 | // |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 208 | return NoFramePointerElim || MFI->hasVarSizedObjects(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 209 | } |
| 210 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 211 | void PPCRegisterInfo:: |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 212 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 213 | MachineBasicBlock::iterator I) const { |
| 214 | if (hasFP(MF)) { |
| 215 | // If we have a frame pointer, convert as follows: |
| 216 | // ADJCALLSTACKDOWN -> addi, r1, r1, -amount |
| 217 | // ADJCALLSTACKUP -> addi, r1, r1, amount |
| 218 | MachineInstr *Old = I; |
| 219 | unsigned Amount = Old->getOperand(0).getImmedValue(); |
| 220 | if (Amount != 0) { |
| 221 | // We need to keep the stack aligned properly. To do this, we round the |
| 222 | // amount of space needed for the outgoing arguments up to the next |
| 223 | // alignment boundary. |
| 224 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 225 | Amount = (Amount+Align-1)/Align*Align; |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 226 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 227 | // Replace the pseudo instruction with a new instruction... |
| 228 | if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { |
Chris Lattner | c6d48d3 | 2006-01-11 23:07:57 +0000 | [diff] [blame] | 229 | BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 230 | } else { |
| 231 | assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); |
Chris Lattner | c6d48d3 | 2006-01-11 23:07:57 +0000 | [diff] [blame] | 232 | BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 233 | } |
| 234 | } |
| 235 | } |
| 236 | MBB.erase(I); |
| 237 | } |
| 238 | |
| 239 | void |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 240 | PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 241 | unsigned i = 0; |
| 242 | MachineInstr &MI = *II; |
| 243 | MachineBasicBlock &MBB = *MI.getParent(); |
| 244 | MachineFunction &MF = *MBB.getParent(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 245 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 246 | while (!MI.getOperand(i).isFrameIndex()) { |
| 247 | ++i; |
| 248 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 249 | } |
| 250 | |
| 251 | int FrameIndex = MI.getOperand(i).getFrameIndex(); |
| 252 | |
| 253 | // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). |
| 254 | MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); |
| 255 | |
| 256 | // Take into account whether it's an add or mem instruction |
| 257 | unsigned OffIdx = (i == 2) ? 1 : 2; |
| 258 | |
| 259 | // Now add the frame object offset to the offset from r1. |
| 260 | int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + |
| 261 | MI.getOperand(OffIdx).getImmedValue(); |
| 262 | |
| 263 | // If we're not using a Frame Pointer that has been set to the value of the |
| 264 | // SP before having the stack size subtracted from it, then add the stack size |
| 265 | // to Offset to get the correct offset. |
| 266 | Offset += MF.getFrameInfo()->getStackSize(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 267 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 268 | if (Offset > 32767 || Offset < -32768) { |
| 269 | // Insert a set of r0 with the full offset value before the ld, st, or add |
| 270 | MachineBasicBlock *MBB = MI.getParent(); |
Chris Lattner | c6d48d3 | 2006-01-11 23:07:57 +0000 | [diff] [blame] | 271 | BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16); |
| 272 | BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); |
| 273 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 274 | // convert into indexed form of the instruction |
| 275 | // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 |
| 276 | // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 |
Chris Lattner | 1463019 | 2005-09-09 20:51:08 +0000 | [diff] [blame] | 277 | assert(ImmToIdxMap.count(MI.getOpcode()) && |
| 278 | "No indexed form of load or store available!"); |
| 279 | unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 280 | MI.setOpcode(NewOpcode); |
| 281 | MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); |
| 282 | MI.SetMachineOperandReg(2, PPC::R0); |
| 283 | } else { |
Chris Lattner | 841d12d | 2005-10-18 16:51:22 +0000 | [diff] [blame] | 284 | switch (MI.getOpcode()) { |
| 285 | case PPC::LWA: |
| 286 | case PPC::LD: |
| 287 | case PPC::STD: |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 288 | case PPC::STD_32: |
Chris Lattner | 841d12d | 2005-10-18 16:51:22 +0000 | [diff] [blame] | 289 | assert((Offset & 3) == 0 && "Invalid frame offset!"); |
| 290 | Offset >>= 2; // The actual encoded value has the low two bits zero. |
| 291 | break; |
| 292 | } |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 293 | MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, |
| 294 | Offset); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 295 | } |
| 296 | } |
| 297 | |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame^] | 298 | /// VRRegNo - Map from a numbered VR register to its enum value. |
| 299 | /// |
| 300 | static const unsigned short VRRegNo[] = { |
| 301 | PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , |
| 302 | PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, |
| 303 | PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 304 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 |
| 305 | }; |
| 306 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 307 | // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the |
| 308 | // instruction selector. Based on the vector registers that have been used, |
| 309 | // transform this into the appropriate ORI instruction. |
| 310 | static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { |
| 311 | unsigned UsedRegMask = 0; |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame^] | 312 | for (unsigned i = 0; i != 32; ++i) |
| 313 | if (UsedRegs[VRRegNo[i]]) |
| 314 | UsedRegMask |= 1 << (31-i); |
| 315 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 316 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 317 | unsigned DstReg = MI->getOperand(0).getReg(); |
| 318 | // If no registers are used, turn this into a copy. |
| 319 | if (UsedRegMask == 0) { |
| 320 | if (SrcReg != DstReg) |
| 321 | BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg) |
| 322 | .addReg(SrcReg).addReg(SrcReg); |
| 323 | } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { |
| 324 | BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) |
| 325 | .addReg(SrcReg).addImm(UsedRegMask); |
| 326 | } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { |
| 327 | BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) |
| 328 | .addReg(SrcReg).addImm(UsedRegMask >> 16); |
| 329 | } else { |
| 330 | BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) |
| 331 | .addReg(SrcReg).addImm(UsedRegMask >> 16); |
| 332 | BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) |
| 333 | .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); |
| 334 | } |
| 335 | |
| 336 | // Remove the old UPDATE_VRSAVE instruction. |
| 337 | MI->getParent()->erase(MI); |
| 338 | } |
| 339 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 340 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 341 | void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 342 | MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB |
| 343 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 344 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 345 | MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo(); |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 346 | |
| 347 | // Do we have a frame pointer for this function? |
| 348 | bool HasFP = hasFP(MF); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 349 | |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 350 | // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, |
| 351 | // process it. |
Chris Lattner | 8aa777d | 2006-03-16 21:31:45 +0000 | [diff] [blame] | 352 | for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 353 | if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { |
| 354 | HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); |
| 355 | break; |
| 356 | } |
| 357 | } |
| 358 | |
| 359 | // Move MBBI back to the beginning of the function. |
| 360 | MBBI = MBB.begin(); |
| 361 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 362 | // Get the number of bytes to allocate from the FrameInfo |
| 363 | unsigned NumBytes = MFI->getStackSize(); |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 364 | |
| 365 | // Get the alignments provided by the target, and the maximum alignment |
| 366 | // (if any) of the fixed frame objects. |
| 367 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 368 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 369 | |
| 370 | // If we have calls, we cannot use the red zone to store callee save registers |
| 371 | // and we must set up a stack frame, so calculate the necessary size here. |
| 372 | if (MFI->hasCalls()) { |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 373 | // We reserve argument space for call sites in the function immediately on |
| 374 | // entry to the current function. This eliminates the need for add/sub |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 375 | // brackets around call sites. |
| 376 | NumBytes += MFI->getMaxCallFrameSize(); |
| 377 | } |
| 378 | |
Jeff Cohen | d29b6aa | 2005-07-30 18:33:25 +0000 | [diff] [blame] | 379 | // If we are a leaf function, and use up to 224 bytes of stack space, |
Nate Begeman | 54eed36 | 2005-07-27 06:06:29 +0000 | [diff] [blame] | 380 | // and don't have a frame pointer, then we do not need to adjust the stack |
| 381 | // pointer (we fit in the Red Zone). |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 382 | if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() && |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 383 | MaxAlign <= TargetAlign)) { |
Nate Begeman | 54eed36 | 2005-07-27 06:06:29 +0000 | [diff] [blame] | 384 | MFI->setStackSize(0); |
| 385 | return; |
| 386 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 387 | |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 388 | // Add the size of R1 to NumBytes size for the store of R1 to the bottom |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 389 | // of the stack and round the size to a multiple of the alignment. |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 390 | unsigned Align = std::max(TargetAlign, MaxAlign); |
Chris Lattner | 5802be1 | 2005-09-30 17:16:59 +0000 | [diff] [blame] | 391 | unsigned GPRSize = 4; |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 392 | unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 393 | NumBytes = (NumBytes+Size+Align-1)/Align*Align; |
| 394 | |
| 395 | // Update frame info to pretend that this is part of the stack... |
| 396 | MFI->setStackSize(NumBytes); |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 397 | int NegNumbytes = -NumBytes; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 398 | |
Nate Begeman | 3dee175 | 2005-07-27 23:11:27 +0000 | [diff] [blame] | 399 | // Adjust stack pointer: r1 -= numbytes. |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 400 | // If there is a preferred stack alignment, align R1 now |
| 401 | if (MaxAlign > TargetAlign) { |
| 402 | assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); |
Nate Begeman | 2186298 | 2006-04-11 19:44:43 +0000 | [diff] [blame] | 403 | assert(isInt16(MaxAlign-NumBytes) && "Unhandled stack size and alignment!"); |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 404 | BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) |
| 405 | .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); |
Nate Begeman | 2186298 | 2006-04-11 19:44:43 +0000 | [diff] [blame] | 406 | BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0) |
| 407 | .addSImm(MaxAlign-NumBytes); |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 408 | BuildMI(MBB, MBBI, PPC::STWUX, 3) |
| 409 | .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); |
| 410 | } else if (NumBytes <= 32768) { |
| 411 | BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes) |
| 412 | .addReg(PPC::R1); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 413 | } else { |
Chris Lattner | c6d48d3 | 2006-01-11 23:07:57 +0000 | [diff] [blame] | 414 | BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 415 | BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0) |
| 416 | .addImm(NegNumbytes & 0xFFFF); |
| 417 | BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1) |
| 418 | .addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 419 | } |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 420 | |
Jim Laskey | 52fa244 | 2006-04-11 08:11:53 +0000 | [diff] [blame] | 421 | if (DebugInfo && DebugInfo->hasInfo()) { |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 422 | std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves(); |
| 423 | unsigned LabelID = DebugInfo->NextLabelID(); |
| 424 | |
| 425 | // Show update of SP. |
| 426 | MachineLocation Dst(MachineLocation::VirtualFP); |
| 427 | MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes); |
| 428 | Moves.push_back(new MachineMove(LabelID, Dst, Src)); |
| 429 | |
| 430 | BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID); |
| 431 | } |
| 432 | |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 433 | // If there is a frame pointer, copy R1 (SP) into R31 (FP) |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 434 | if (HasFP) { |
Chris Lattner | c6d48d3 | 2006-01-11 23:07:57 +0000 | [diff] [blame] | 435 | BuildMI(MBB, MBBI, PPC::STW, 3) |
| 436 | .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); |
| 437 | BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 438 | } |
| 439 | } |
| 440 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 441 | void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, |
| 442 | MachineBasicBlock &MBB) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 443 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Evan Cheng | 6da8d99 | 2006-01-09 18:28:21 +0000 | [diff] [blame] | 444 | assert(MBBI->getOpcode() == PPC::BLR && |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 445 | "Can only insert epilog into returning blocks"); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 446 | |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 447 | // Get alignment info so we know how to restore r1 |
| 448 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 449 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 450 | |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 451 | // Get the number of bytes allocated from the FrameInfo. |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 452 | unsigned NumBytes = MFI->getStackSize(); |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 453 | unsigned GPRSize = 4; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 454 | |
| 455 | if (NumBytes != 0) { |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 456 | // If this function has a frame pointer, load the saved stack pointer from |
| 457 | // its stack slot. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 458 | if (hasFP(MF)) { |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 459 | BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) |
| 460 | .addSImm(GPRSize).addReg(PPC::R31); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 461 | } |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 462 | |
| 463 | // The loaded (or persistent) stack pointer value is offseted by the 'stwu' |
| 464 | // on entry to the function. Add this offset back now. |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 465 | if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) { |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 466 | BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) |
| 467 | .addReg(PPC::R1).addSImm(NumBytes); |
| 468 | } else { |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 469 | BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1); |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 470 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 471 | } |
| 472 | } |
| 473 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 474 | unsigned PPCRegisterInfo::getRARegister() const { |
| 475 | return PPC::LR; |
| 476 | } |
| 477 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 478 | unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 479 | return hasFP(MF) ? PPC::R31 : PPC::R1; |
| 480 | } |
| 481 | |
| 482 | void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves) |
| 483 | const { |
| 484 | // Initial state is the frame pointer is R1. |
| 485 | MachineLocation Dst(MachineLocation::VirtualFP); |
| 486 | MachineLocation Src(PPC::R1, 0); |
| 487 | Moves.push_back(new MachineMove(0, Dst, Src)); |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 488 | } |
| 489 | |
Chris Lattner | 4c7b43b | 2005-10-14 23:37:35 +0000 | [diff] [blame] | 490 | #include "PPCGenRegisterInfo.inc" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 491 | |