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David Goodwinb50ea5c2009-07-02 22:18:33 +00001//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
Anton Korobeynikovd49ea772009-06-26 21:28:53 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
David Goodwinb50ea5c2009-07-02 22:18:33 +000010// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000011//
12//===----------------------------------------------------------------------===//
13
14#include "ARMInstrInfo.h"
15#include "ARM.h"
16#include "ARMGenInstrInfo.inc"
17#include "ARMMachineFunctionInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
Evan Chenge3ce8aa2009-11-01 22:04:35 +000020#include "llvm/CodeGen/MachineMemOperand.h"
21#include "llvm/CodeGen/PseudoSourceValue.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000022#include "llvm/ADT/SmallVector.h"
David Goodwinb50ea5c2009-07-02 22:18:33 +000023#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000024
25using namespace llvm;
26
Anton Korobeynikovf95215f2009-11-02 00:10:38 +000027Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
28 : ARMBaseInstrInfo(STI), RI(*this, STI) {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000029}
30
Evan Cheng446c4282009-07-11 06:43:01 +000031unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
David Goodwin334c2642009-07-08 16:09:28 +000032 return 0;
33}
34
David Goodwin334c2642009-07-08 16:09:28 +000035bool
36Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
37 if (MBB.empty()) return false;
38
39 switch (MBB.back().getOpcode()) {
40 case ARM::tBX_RET:
41 case ARM::tBX_RET_vararg:
42 case ARM::tPOP_RET:
43 case ARM::tB:
Bob Wilson8d4de5a2009-10-28 18:26:41 +000044 case ARM::tBRIND:
David Goodwin334c2642009-07-08 16:09:28 +000045 case ARM::tBR_JTr:
46 return true;
47 default:
48 break;
49 }
50
51 return false;
52}
53
David Goodwinb50ea5c2009-07-02 22:18:33 +000054bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator I,
56 unsigned DestReg, unsigned SrcReg,
57 const TargetRegisterClass *DestRC,
58 const TargetRegisterClass *SrcRC) const {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000059 DebugLoc DL = DebugLoc::getUnknownLoc();
60 if (I != MBB.end()) DL = I->getDebugLoc();
61
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000062 if (DestRC == ARM::GPRRegisterClass) {
63 if (SrcRC == ARM::GPRRegisterClass) {
Evan Chengd8336062009-07-26 23:59:01 +000064 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000065 return true;
66 } else if (SrcRC == ARM::tGPRRegisterClass) {
Evan Chengd8336062009-07-26 23:59:01 +000067 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000068 return true;
69 }
70 } else if (DestRC == ARM::tGPRRegisterClass) {
71 if (SrcRC == ARM::GPRRegisterClass) {
Evan Chengd8336062009-07-26 23:59:01 +000072 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000073 return true;
74 } else if (SrcRC == ARM::tGPRRegisterClass) {
75 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
76 return true;
77 }
78 }
79
80 return false;
81}
82
David Goodwinb50ea5c2009-07-02 22:18:33 +000083bool Thumb1InstrInfo::
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000084canFoldMemoryOperand(const MachineInstr *MI,
85 const SmallVectorImpl<unsigned> &Ops) const {
86 if (Ops.size() != 1) return false;
87
88 unsigned OpNum = Ops[0];
89 unsigned Opc = MI->getOpcode();
90 switch (Opc) {
91 default: break;
92 case ARM::tMOVr:
Evan Chengd8336062009-07-26 23:59:01 +000093 case ARM::tMOVtgpr2gpr:
94 case ARM::tMOVgpr2tgpr:
95 case ARM::tMOVgpr2gpr: {
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000096 if (OpNum == 0) { // move -> store
97 unsigned SrcReg = MI->getOperand(1).getReg();
Evan Cheng86e5f7b2009-08-13 05:40:51 +000098 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
99 !isARMLowRegister(SrcReg))
Anton Korobeynikova98cbc52009-06-27 12:16:40 +0000100 // tSpill cannot take a high register operand.
101 return false;
102 } else { // move -> load
103 unsigned DstReg = MI->getOperand(0).getReg();
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000104 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
105 !isARMLowRegister(DstReg))
Anton Korobeynikova98cbc52009-06-27 12:16:40 +0000106 // tRestore cannot target a high register operand.
107 return false;
108 }
109 return true;
110 }
111 }
112
113 return false;
114}
115
David Goodwinb50ea5c2009-07-02 22:18:33 +0000116void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000117storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
118 unsigned SrcReg, bool isKill, int FI,
119 const TargetRegisterClass *RC) const {
120 DebugLoc DL = DebugLoc::getUnknownLoc();
121 if (I != MBB.end()) DL = I->getDebugLoc();
122
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000123 assert((RC == ARM::tGPRRegisterClass ||
124 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
125 isARMLowRegister(SrcReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000126
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000127 if (RC == ARM::tGPRRegisterClass) {
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000128 MachineFunction &MF = *MBB.getParent();
129 MachineFrameInfo &MFI = *MF.getFrameInfo();
130 MachineMemOperand *MMO =
131 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
132 MachineMemOperand::MOStore, 0,
133 MFI.getObjectSize(FI),
134 MFI.getObjectAlignment(FI));
Evan Cheng446c4282009-07-11 06:43:01 +0000135 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
136 .addReg(SrcReg, getKillRegState(isKill))
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000137 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000138 }
139}
140
David Goodwinb50ea5c2009-07-02 22:18:33 +0000141void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000142loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
143 unsigned DestReg, int FI,
144 const TargetRegisterClass *RC) const {
145 DebugLoc DL = DebugLoc::getUnknownLoc();
146 if (I != MBB.end()) DL = I->getDebugLoc();
147
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000148 assert((RC == ARM::tGPRRegisterClass ||
149 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
150 isARMLowRegister(DestReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000151
152 if (RC == ARM::tGPRRegisterClass) {
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000153 MachineFunction &MF = *MBB.getParent();
154 MachineFrameInfo &MFI = *MF.getFrameInfo();
155 MachineMemOperand *MMO =
156 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
157 MachineMemOperand::MOLoad, 0,
158 MFI.getObjectSize(FI),
159 MFI.getObjectAlignment(FI));
Evan Cheng446c4282009-07-11 06:43:01 +0000160 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000161 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000162 }
163}
164
David Goodwinb50ea5c2009-07-02 22:18:33 +0000165bool Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000166spillCalleeSavedRegisters(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator MI,
168 const std::vector<CalleeSavedInfo> &CSI) const {
169 if (CSI.empty())
170 return false;
171
172 DebugLoc DL = DebugLoc::getUnknownLoc();
173 if (MI != MBB.end()) DL = MI->getDebugLoc();
174
175 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
Evan Cheng4b322e52009-08-11 21:11:32 +0000176 AddDefaultPred(MIB);
Evan Cheng89259792009-10-02 05:03:07 +0000177 MIB.addReg(0); // No write back.
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000178 for (unsigned i = CSI.size(); i != 0; --i) {
179 unsigned Reg = CSI[i-1].getReg();
180 // Add the callee-saved register as live-in. It's killed at the spill.
181 MBB.addLiveIn(Reg);
182 MIB.addReg(Reg, RegState::Kill);
183 }
184 return true;
185}
186
David Goodwinb50ea5c2009-07-02 22:18:33 +0000187bool Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000188restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
189 MachineBasicBlock::iterator MI,
190 const std::vector<CalleeSavedInfo> &CSI) const {
191 MachineFunction &MF = *MBB.getParent();
192 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
193 if (CSI.empty())
194 return false;
195
196 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
Evan Cheng4b322e52009-08-11 21:11:32 +0000197 DebugLoc DL = MI->getDebugLoc();
198 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
199 AddDefaultPred(MIB);
Evan Cheng10469f82009-10-01 20:54:53 +0000200 MIB.addReg(0); // No write back.
Evan Cheng4b322e52009-08-11 21:11:32 +0000201
202 bool NumRegs = 0;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000203 for (unsigned i = CSI.size(); i != 0; --i) {
204 unsigned Reg = CSI[i-1].getReg();
205 if (Reg == ARM::LR) {
206 // Special epilogue for vararg functions. See emitEpilogue
207 if (isVarArg)
208 continue;
209 Reg = ARM::PC;
Evan Cheng4b322e52009-08-11 21:11:32 +0000210 (*MIB).setDesc(get(ARM::tPOP_RET));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000211 MI = MBB.erase(MI);
212 }
Evan Cheng4b322e52009-08-11 21:11:32 +0000213 MIB.addReg(Reg, getDefRegState(true));
214 ++NumRegs;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000215 }
216
217 // It's illegal to emit pop instruction without operands.
Evan Cheng4b322e52009-08-11 21:11:32 +0000218 if (NumRegs)
219 MBB.insert(MI, &*MIB);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000220
221 return true;
222}
223
David Goodwinb50ea5c2009-07-02 22:18:33 +0000224MachineInstr *Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000225foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
226 const SmallVectorImpl<unsigned> &Ops, int FI) const {
227 if (Ops.size() != 1) return NULL;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000228
229 unsigned OpNum = Ops[0];
230 unsigned Opc = MI->getOpcode();
231 MachineInstr *NewMI = NULL;
232 switch (Opc) {
233 default: break;
234 case ARM::tMOVr:
Evan Chengd8336062009-07-26 23:59:01 +0000235 case ARM::tMOVtgpr2gpr:
236 case ARM::tMOVgpr2tgpr:
237 case ARM::tMOVgpr2gpr: {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000238 if (OpNum == 0) { // move -> store
239 unsigned SrcReg = MI->getOperand(1).getReg();
240 bool isKill = MI->getOperand(1).isKill();
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000241 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
242 !isARMLowRegister(SrcReg))
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000243 // tSpill cannot take a high register operand.
244 break;
Evan Cheng446c4282009-07-11 06:43:01 +0000245 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
246 .addReg(SrcReg, getKillRegState(isKill))
247 .addFrameIndex(FI).addImm(0));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000248 } else { // move -> load
249 unsigned DstReg = MI->getOperand(0).getReg();
Evan Cheng86e5f7b2009-08-13 05:40:51 +0000250 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
251 !isARMLowRegister(DstReg))
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000252 // tRestore cannot target a high register operand.
253 break;
254 bool isDead = MI->getOperand(0).isDead();
Evan Cheng446c4282009-07-11 06:43:01 +0000255 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
256 .addReg(DstReg,
257 RegState::Define | getDeadRegState(isDead))
258 .addFrameIndex(FI).addImm(0));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000259 }
260 break;
261 }
262 }
263
264 return NewMI;
265}