David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 1 | //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===// |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 10 | // This file contains the Thumb-1 implementation of the TargetInstrInfo class. |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "ARMInstrInfo.h" |
| 15 | #include "ARM.h" |
| 16 | #include "ARMGenInstrInfo.inc" |
| 17 | #include "ARMMachineFunctionInfo.h" |
| 18 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 19 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/MachineMemOperand.h" |
| 21 | #include "llvm/CodeGen/PseudoSourceValue.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 22 | #include "llvm/ADT/SmallVector.h" |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 23 | #include "Thumb1InstrInfo.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 24 | |
| 25 | using namespace llvm; |
| 26 | |
Anton Korobeynikov | f95215f | 2009-11-02 00:10:38 +0000 | [diff] [blame^] | 27 | Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) |
| 28 | : ARMBaseInstrInfo(STI), RI(*this, STI) { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 29 | } |
| 30 | |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 31 | unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 32 | return 0; |
| 33 | } |
| 34 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 35 | bool |
| 36 | Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { |
| 37 | if (MBB.empty()) return false; |
| 38 | |
| 39 | switch (MBB.back().getOpcode()) { |
| 40 | case ARM::tBX_RET: |
| 41 | case ARM::tBX_RET_vararg: |
| 42 | case ARM::tPOP_RET: |
| 43 | case ARM::tB: |
Bob Wilson | 8d4de5a | 2009-10-28 18:26:41 +0000 | [diff] [blame] | 44 | case ARM::tBRIND: |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 45 | case ARM::tBR_JTr: |
| 46 | return true; |
| 47 | default: |
| 48 | break; |
| 49 | } |
| 50 | |
| 51 | return false; |
| 52 | } |
| 53 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 54 | bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 55 | MachineBasicBlock::iterator I, |
| 56 | unsigned DestReg, unsigned SrcReg, |
| 57 | const TargetRegisterClass *DestRC, |
| 58 | const TargetRegisterClass *SrcRC) const { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 59 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 60 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 61 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 62 | if (DestRC == ARM::GPRRegisterClass) { |
| 63 | if (SrcRC == ARM::GPRRegisterClass) { |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 64 | BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 65 | return true; |
| 66 | } else if (SrcRC == ARM::tGPRRegisterClass) { |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 67 | BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 68 | return true; |
| 69 | } |
| 70 | } else if (DestRC == ARM::tGPRRegisterClass) { |
| 71 | if (SrcRC == ARM::GPRRegisterClass) { |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 72 | BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 73 | return true; |
| 74 | } else if (SrcRC == ARM::tGPRRegisterClass) { |
| 75 | BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg); |
| 76 | return true; |
| 77 | } |
| 78 | } |
| 79 | |
| 80 | return false; |
| 81 | } |
| 82 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 83 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 84 | canFoldMemoryOperand(const MachineInstr *MI, |
| 85 | const SmallVectorImpl<unsigned> &Ops) const { |
| 86 | if (Ops.size() != 1) return false; |
| 87 | |
| 88 | unsigned OpNum = Ops[0]; |
| 89 | unsigned Opc = MI->getOpcode(); |
| 90 | switch (Opc) { |
| 91 | default: break; |
| 92 | case ARM::tMOVr: |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 93 | case ARM::tMOVtgpr2gpr: |
| 94 | case ARM::tMOVgpr2tgpr: |
| 95 | case ARM::tMOVgpr2gpr: { |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 96 | if (OpNum == 0) { // move -> store |
| 97 | unsigned SrcReg = MI->getOperand(1).getReg(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 98 | if (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| 99 | !isARMLowRegister(SrcReg)) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 100 | // tSpill cannot take a high register operand. |
| 101 | return false; |
| 102 | } else { // move -> load |
| 103 | unsigned DstReg = MI->getOperand(0).getReg(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 104 | if (TargetRegisterInfo::isPhysicalRegister(DstReg) && |
| 105 | !isARMLowRegister(DstReg)) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 106 | // tRestore cannot target a high register operand. |
| 107 | return false; |
| 108 | } |
| 109 | return true; |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | return false; |
| 114 | } |
| 115 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 116 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 117 | storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 118 | unsigned SrcReg, bool isKill, int FI, |
| 119 | const TargetRegisterClass *RC) const { |
| 120 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 121 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 122 | |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 123 | assert((RC == ARM::tGPRRegisterClass || |
| 124 | (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| 125 | isARMLowRegister(SrcReg))) && "Unknown regclass!"); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 126 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 127 | if (RC == ARM::tGPRRegisterClass) { |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 128 | MachineFunction &MF = *MBB.getParent(); |
| 129 | MachineFrameInfo &MFI = *MF.getFrameInfo(); |
| 130 | MachineMemOperand *MMO = |
| 131 | MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), |
| 132 | MachineMemOperand::MOStore, 0, |
| 133 | MFI.getObjectSize(FI), |
| 134 | MFI.getObjectAlignment(FI)); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 135 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill)) |
| 136 | .addReg(SrcReg, getKillRegState(isKill)) |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 137 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 138 | } |
| 139 | } |
| 140 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 141 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 142 | loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 143 | unsigned DestReg, int FI, |
| 144 | const TargetRegisterClass *RC) const { |
| 145 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 146 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 147 | |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 148 | assert((RC == ARM::tGPRRegisterClass || |
| 149 | (TargetRegisterInfo::isPhysicalRegister(DestReg) && |
| 150 | isARMLowRegister(DestReg))) && "Unknown regclass!"); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 151 | |
| 152 | if (RC == ARM::tGPRRegisterClass) { |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 153 | MachineFunction &MF = *MBB.getParent(); |
| 154 | MachineFrameInfo &MFI = *MF.getFrameInfo(); |
| 155 | MachineMemOperand *MMO = |
| 156 | MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), |
| 157 | MachineMemOperand::MOLoad, 0, |
| 158 | MFI.getObjectSize(FI), |
| 159 | MFI.getObjectAlignment(FI)); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 160 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg) |
Evan Cheng | e3ce8aa | 2009-11-01 22:04:35 +0000 | [diff] [blame] | 161 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 162 | } |
| 163 | } |
| 164 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 165 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 166 | spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 167 | MachineBasicBlock::iterator MI, |
| 168 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 169 | if (CSI.empty()) |
| 170 | return false; |
| 171 | |
| 172 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 173 | if (MI != MBB.end()) DL = MI->getDebugLoc(); |
| 174 | |
| 175 | MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 176 | AddDefaultPred(MIB); |
Evan Cheng | 8925979 | 2009-10-02 05:03:07 +0000 | [diff] [blame] | 177 | MIB.addReg(0); // No write back. |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 178 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 179 | unsigned Reg = CSI[i-1].getReg(); |
| 180 | // Add the callee-saved register as live-in. It's killed at the spill. |
| 181 | MBB.addLiveIn(Reg); |
| 182 | MIB.addReg(Reg, RegState::Kill); |
| 183 | } |
| 184 | return true; |
| 185 | } |
| 186 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 187 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 188 | restoreCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 189 | MachineBasicBlock::iterator MI, |
| 190 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 191 | MachineFunction &MF = *MBB.getParent(); |
| 192 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 193 | if (CSI.empty()) |
| 194 | return false; |
| 195 | |
| 196 | bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 197 | DebugLoc DL = MI->getDebugLoc(); |
| 198 | MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP)); |
| 199 | AddDefaultPred(MIB); |
Evan Cheng | 10469f8 | 2009-10-01 20:54:53 +0000 | [diff] [blame] | 200 | MIB.addReg(0); // No write back. |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 201 | |
| 202 | bool NumRegs = 0; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 203 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 204 | unsigned Reg = CSI[i-1].getReg(); |
| 205 | if (Reg == ARM::LR) { |
| 206 | // Special epilogue for vararg functions. See emitEpilogue |
| 207 | if (isVarArg) |
| 208 | continue; |
| 209 | Reg = ARM::PC; |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 210 | (*MIB).setDesc(get(ARM::tPOP_RET)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 211 | MI = MBB.erase(MI); |
| 212 | } |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 213 | MIB.addReg(Reg, getDefRegState(true)); |
| 214 | ++NumRegs; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | // It's illegal to emit pop instruction without operands. |
Evan Cheng | 4b322e5 | 2009-08-11 21:11:32 +0000 | [diff] [blame] | 218 | if (NumRegs) |
| 219 | MBB.insert(MI, &*MIB); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 220 | |
| 221 | return true; |
| 222 | } |
| 223 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 224 | MachineInstr *Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 225 | foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, |
| 226 | const SmallVectorImpl<unsigned> &Ops, int FI) const { |
| 227 | if (Ops.size() != 1) return NULL; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 228 | |
| 229 | unsigned OpNum = Ops[0]; |
| 230 | unsigned Opc = MI->getOpcode(); |
| 231 | MachineInstr *NewMI = NULL; |
| 232 | switch (Opc) { |
| 233 | default: break; |
| 234 | case ARM::tMOVr: |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 235 | case ARM::tMOVtgpr2gpr: |
| 236 | case ARM::tMOVgpr2tgpr: |
| 237 | case ARM::tMOVgpr2gpr: { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 238 | if (OpNum == 0) { // move -> store |
| 239 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 240 | bool isKill = MI->getOperand(1).isKill(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 241 | if (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| 242 | !isARMLowRegister(SrcReg)) |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 243 | // tSpill cannot take a high register operand. |
| 244 | break; |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 245 | NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) |
| 246 | .addReg(SrcReg, getKillRegState(isKill)) |
| 247 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 248 | } else { // move -> load |
| 249 | unsigned DstReg = MI->getOperand(0).getReg(); |
Evan Cheng | 86e5f7b | 2009-08-13 05:40:51 +0000 | [diff] [blame] | 250 | if (TargetRegisterInfo::isPhysicalRegister(DstReg) && |
| 251 | !isARMLowRegister(DstReg)) |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 252 | // tRestore cannot target a high register operand. |
| 253 | break; |
| 254 | bool isDead = MI->getOperand(0).isDead(); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 255 | NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore)) |
| 256 | .addReg(DstReg, |
| 257 | RegState::Define | getDeadRegState(isDead)) |
| 258 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 259 | } |
| 260 | break; |
| 261 | } |
| 262 | } |
| 263 | |
| 264 | return NewMI; |
| 265 | } |