The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 1 | /* |
| 2 | * ARM virtual CPU header |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
David Turner | 6a9ef17 | 2010-09-09 22:54:36 +0200 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 18 | */ |
| 19 | #ifndef CPU_ARM_H |
| 20 | #define CPU_ARM_H |
| 21 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 22 | #include "config.h" |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 23 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 24 | #include "kvm-consts.h" |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 25 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 26 | #if defined(TARGET_AARCH64) |
| 27 | /* AArch64 definitions */ |
| 28 | # define TARGET_LONG_BITS 64 |
| 29 | # define ELF_MACHINE EM_AARCH64 |
| 30 | #else |
| 31 | # define TARGET_LONG_BITS 32 |
| 32 | # define ELF_MACHINE EM_ARM |
| 33 | #endif |
| 34 | |
| 35 | // TODO(digit): Remove this line. |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 36 | #define CPUOldState struct CPUARMState |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 37 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 38 | #define CPUArchState struct CPUARMState |
| 39 | |
David 'Digit' Turner | 45c3be0 | 2011-05-09 14:52:14 +0200 | [diff] [blame] | 40 | #include "qemu-common.h" |
David 'Digit' Turner | 852088c | 2013-12-14 23:04:12 +0100 | [diff] [blame] | 41 | #include "exec/cpu-defs.h" |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 42 | |
David 'Digit' Turner | 5425d40 | 2013-12-15 00:28:46 +0100 | [diff] [blame] | 43 | #include "fpu/softfloat.h" |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 44 | |
| 45 | #define TARGET_HAS_ICE 1 |
| 46 | |
| 47 | #define EXCP_UDEF 1 /* undefined instruction */ |
| 48 | #define EXCP_SWI 2 /* software interrupt */ |
| 49 | #define EXCP_PREFETCH_ABORT 3 |
| 50 | #define EXCP_DATA_ABORT 4 |
| 51 | #define EXCP_IRQ 5 |
| 52 | #define EXCP_FIQ 6 |
| 53 | #define EXCP_BKPT 7 |
| 54 | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
| 55 | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
David Turner | 6a9ef17 | 2010-09-09 22:54:36 +0200 | [diff] [blame] | 56 | #define EXCP_STREX 10 |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 57 | #define EXCP_SMC 11 /* secure monitor call */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 58 | |
| 59 | #define ARMV7M_EXCP_RESET 1 |
| 60 | #define ARMV7M_EXCP_NMI 2 |
| 61 | #define ARMV7M_EXCP_HARD 3 |
| 62 | #define ARMV7M_EXCP_MEM 4 |
| 63 | #define ARMV7M_EXCP_BUS 5 |
| 64 | #define ARMV7M_EXCP_USAGE 6 |
| 65 | #define ARMV7M_EXCP_SVC 11 |
| 66 | #define ARMV7M_EXCP_DEBUG 12 |
| 67 | #define ARMV7M_EXCP_PENDSV 14 |
| 68 | #define ARMV7M_EXCP_SYSTICK 15 |
| 69 | |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 70 | /* ARM-specific interrupt pending bits. */ |
| 71 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 |
| 72 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 73 | /* Meanings of the ARMCPU object's two inbound GPIO lines */ |
| 74 | #define ARM_CPU_IRQ 0 |
| 75 | #define ARM_CPU_FIQ 1 |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 76 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 77 | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 78 | int srcreg, int operand, uint32_t value, |
| 79 | void *retaddr); |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 80 | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 81 | int dstreg, int operand, |
| 82 | void *retaddr); |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 83 | |
| 84 | struct arm_boot_info; |
| 85 | |
| 86 | #define NB_MMU_MODES 2 |
| 87 | |
| 88 | /* We currently assume float and double are IEEE single and double |
| 89 | precision respectively. |
| 90 | Doing runtime conversions is tricky because VFP registers may contain |
| 91 | integer values (eg. as the result of a FTOSI instruction). |
| 92 | s<2n> maps to the least significant half of d<n> |
| 93 | s<2n+1> maps to the most significant half of d<n> |
| 94 | */ |
| 95 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 96 | /* CPU state for each instance of a generic timer (in cp15 c14) */ |
| 97 | typedef struct ARMGenericTimer { |
| 98 | uint64_t cval; /* Timer CompareValue register */ |
| 99 | uint32_t ctl; /* Timer Control register */ |
| 100 | } ARMGenericTimer; |
| 101 | |
| 102 | #define GTIMER_PHYS 0 |
| 103 | #define GTIMER_VIRT 1 |
| 104 | #define NUM_GTIMERS 2 |
| 105 | |
| 106 | /* Scale factor for generic timers, ie number of ns per tick. |
| 107 | * This gives a 62.5MHz timer. |
| 108 | */ |
| 109 | #define GTIMER_SCALE 16 |
| 110 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 111 | typedef struct CPUARMState { |
| 112 | /* Regs for current mode. */ |
| 113 | uint32_t regs[16]; |
| 114 | /* Frequently accessed CPSR bits are stored separately for efficiently. |
| 115 | This contains all the other bits. Use cpsr_{read,write} to access |
| 116 | the whole CPSR. */ |
| 117 | uint32_t uncached_cpsr; |
| 118 | uint32_t spsr; |
| 119 | |
| 120 | /* Banked registers. */ |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 121 | uint32_t banked_spsr[7]; |
| 122 | uint32_t banked_r13[7]; |
| 123 | uint32_t banked_r14[7]; |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 124 | |
| 125 | /* These hold r8-r12. */ |
| 126 | uint32_t usr_regs[5]; |
| 127 | uint32_t fiq_regs[5]; |
| 128 | |
| 129 | /* cpsr flag cache for faster execution */ |
| 130 | uint32_t CF; /* 0 or 1 */ |
| 131 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ |
| 132 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
| 133 | uint32_t ZF; /* Z set if zero. */ |
| 134 | uint32_t QF; /* 0 or 1 */ |
| 135 | uint32_t GE; /* cpsr[19:16] */ |
| 136 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
| 137 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
| 138 | |
| 139 | /* System control coprocessor (cp15) */ |
| 140 | struct { |
| 141 | uint32_t c0_cpuid; |
| 142 | uint32_t c0_cachetype; |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 143 | uint32_t c0_ccsid[16]; /* Cache size. */ |
| 144 | uint32_t c0_clid; /* Cache level. */ |
| 145 | uint32_t c0_cssel; /* Cache size selection. */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 146 | uint32_t c0_c1[8]; /* Feature registers. */ |
| 147 | uint32_t c0_c2[8]; /* Instruction set registers. */ |
| 148 | uint32_t c1_sys; /* System control register. */ |
| 149 | uint32_t c1_coproc; /* Coprocessor access register. */ |
| 150 | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 151 | uint32_t c1_secfg; /* Secure configuration register. */ |
| 152 | uint32_t c1_sedbg; /* Secure debug enable register. */ |
| 153 | uint32_t c1_nseac; /* Non-secure access control register. */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 154 | uint32_t c2_base0; /* MMU translation table base 0. */ |
| 155 | uint32_t c2_base1; /* MMU translation table base 1. */ |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 156 | uint32_t c2_control; /* MMU translation table base control. */ |
| 157 | uint32_t c2_mask; /* MMU translation table base selection mask. */ |
| 158 | uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 159 | uint32_t c2_data; /* MPU data cachable bits. */ |
| 160 | uint32_t c2_insn; /* MPU instruction cachable bits. */ |
| 161 | uint32_t c3; /* MMU domain access control register |
| 162 | MPU write buffer control. */ |
| 163 | uint32_t c5_insn; /* Fault status registers. */ |
| 164 | uint32_t c5_data; |
| 165 | uint32_t c6_region[8]; /* MPU base/size registers. */ |
| 166 | uint32_t c6_insn; /* Fault address registers. */ |
| 167 | uint32_t c6_data; |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 168 | uint32_t c7_par; /* Translation result. */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 169 | uint32_t c9_insn; /* Cache lockdown registers. */ |
| 170 | uint32_t c9_data; |
David 'Digit' Turner | d9ac10a | 2014-03-19 11:01:43 +0100 | [diff] [blame] | 171 | uint32_t c9_pmcr; /* performance monitor control register */ |
| 172 | uint32_t c9_pmcnten; /* perf monitor counter enables */ |
| 173 | uint32_t c9_pmovsr; /* perf monitor overflow status */ |
| 174 | uint32_t c9_pmxevtyper; /* perf monitor event type */ |
| 175 | uint32_t c9_pmuserenr; /* perf monitor user enable */ |
| 176 | uint32_t c9_pminten; /* perf monitor interrupt enables */ |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 177 | uint32_t c12_vbar; /* secure/nonsecure vector base address register. */ |
| 178 | uint32_t c12_mvbar; /* monitor vector base address register. */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 179 | uint32_t c13_fcse; /* FCSE PID. */ |
| 180 | uint32_t c13_context; /* Context ID. */ |
| 181 | uint32_t c13_tls1; /* User RW Thread register. */ |
| 182 | uint32_t c13_tls2; /* User RO Thread register. */ |
| 183 | uint32_t c13_tls3; /* Privileged Thread register. */ |
| 184 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
| 185 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
| 186 | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ |
| 187 | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ |
| 188 | uint32_t c15_threadid; /* TI debugger thread-ID. */ |
| 189 | } cp15; |
| 190 | |
| 191 | struct { |
| 192 | uint32_t other_sp; |
| 193 | uint32_t vecbase; |
| 194 | uint32_t basepri; |
| 195 | uint32_t control; |
| 196 | int current_sp; |
| 197 | int exception; |
| 198 | int pending_exception; |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 199 | } v7m; |
| 200 | |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 201 | /* Minimal set of debug coprocessor state (cp14) */ |
| 202 | uint32_t cp14_dbgdidr; |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 203 | |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 204 | /* Thumb-2 EE state. */ |
| 205 | uint32_t teecr; |
| 206 | uint32_t teehbr; |
| 207 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 208 | /* Internal CPU feature flags. */ |
| 209 | uint32_t features; |
| 210 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 211 | /* VFP coprocessor state. */ |
| 212 | struct { |
| 213 | float64 regs[32]; |
| 214 | |
| 215 | uint32_t xregs[16]; |
| 216 | /* We store these fpcsr fields separately for convenience. */ |
| 217 | int vec_len; |
| 218 | int vec_stride; |
| 219 | |
| 220 | /* scratch space when Tn are not sufficient. */ |
| 221 | uint32_t scratch[8]; |
| 222 | |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 223 | /* fp_status is the "normal" fp status. standard_fp_status retains |
| 224 | * values corresponding to the ARM "Standard FPSCR Value", ie |
| 225 | * default-NaN, flush-to-zero, round-to-nearest and is used by |
| 226 | * any operations (generally Neon) which the architecture defines |
| 227 | * as controlled by the standard FPSCR value rather than the FPSCR. |
| 228 | * |
| 229 | * To avoid having to transfer exception bits around, we simply |
| 230 | * say that the FPSCR cumulative exception flags are the logical |
| 231 | * OR of the flags in the two fp statuses. This relies on the |
| 232 | * only thing which needs to read the exception flags being |
| 233 | * an explicit FPSCR read. |
| 234 | */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 235 | float_status fp_status; |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 236 | float_status standard_fp_status; |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 237 | } vfp; |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 238 | uint32_t exclusive_addr; |
| 239 | uint32_t exclusive_val; |
| 240 | uint32_t exclusive_high; |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 241 | #if defined(CONFIG_USER_ONLY) |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 242 | uint32_t exclusive_test; |
| 243 | uint32_t exclusive_info; |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 244 | #endif |
| 245 | |
| 246 | /* iwMMXt coprocessor state. */ |
| 247 | struct { |
| 248 | uint64_t regs[16]; |
| 249 | uint64_t val; |
| 250 | |
| 251 | uint32_t cregs[16]; |
| 252 | } iwmmxt; |
| 253 | |
| 254 | #if defined(CONFIG_USER_ONLY) |
| 255 | /* For usermode syscall translation. */ |
| 256 | int eabi; |
| 257 | #endif |
| 258 | |
| 259 | CPU_COMMON |
| 260 | |
| 261 | /* These fields after the common ones so they are preserved on reset. */ |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 262 | |
| 263 | /* Coprocessor IO used by peripherals */ |
| 264 | struct { |
| 265 | ARMReadCPFunc *cp_read; |
| 266 | ARMWriteCPFunc *cp_write; |
| 267 | void *opaque; |
| 268 | } cp[15]; |
| 269 | void *nvic; |
David 'Digit' Turner | 44f815d | 2014-03-18 16:34:41 +0100 | [diff] [blame] | 270 | const struct arm_boot_info *boot_info; |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 271 | } CPUARMState; |
| 272 | |
David 'Digit' Turner | 6657678 | 2014-03-24 16:57:57 +0100 | [diff] [blame] | 273 | #include "cpu-qom.h" |
| 274 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 275 | CPUARMState *cpu_arm_init(const char *cpu_model); |
| 276 | void arm_translate_init(void); |
| 277 | int cpu_arm_exec(CPUARMState *s); |
| 278 | void cpu_arm_close(CPUARMState *s); |
| 279 | void do_interrupt(CPUARMState *); |
| 280 | void switch_mode(CPUARMState *, int); |
| 281 | uint32_t do_arm_semihosting(CPUARMState *env); |
| 282 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 283 | static inline bool is_a64(CPUARMState *env) |
| 284 | { |
| 285 | #ifdef CONFIG_ANDROID // TODO(digit) |
| 286 | return 0; |
| 287 | #else |
| 288 | return env->aarch64; |
| 289 | #endif |
| 290 | } |
| 291 | |
| 292 | #define PSTATE_N_SHIFT 3 |
| 293 | #define PSTATE_N (1 << PSTATE_N_SHIFT) |
| 294 | #define PSTATE_Z_SHIFT 2 |
| 295 | #define PSTATE_Z (1 << PSTATE_Z_SHIFT) |
| 296 | #define PSTATE_C_SHIFT 1 |
| 297 | #define PSTATE_C (1 << PSTATE_C_SHIFT) |
| 298 | #define PSTATE_V_SHIFT 0 |
| 299 | #define PSTATE_V (1 << PSTATE_V_SHIFT) |
| 300 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 301 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
| 302 | signal handlers to inform the virtual CPU of exceptions. non zero |
| 303 | is returned if the signal was handled by the virtual CPU. */ |
| 304 | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
| 305 | void *puc); |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 306 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
David 'Digit' Turner | 0d8b235 | 2014-03-20 17:13:13 +0100 | [diff] [blame] | 307 | int mmu_idx); |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 308 | #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 309 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 310 | static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) |
| 311 | { |
| 312 | env->cp15.c13_tls2 = newtls; |
| 313 | } |
| 314 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 315 | #define CPSR_M (0x1fU) |
| 316 | #define CPSR_T (1U << 5) |
| 317 | #define CPSR_F (1U << 6) |
| 318 | #define CPSR_I (1U << 7) |
| 319 | #define CPSR_A (1U << 8) |
| 320 | #define CPSR_E (1U << 9) |
| 321 | #define CPSR_IT_2_7 (0xfc00U) |
| 322 | #define CPSR_GE (0xfU << 16) |
| 323 | #define CPSR_RESERVED (0xfU << 20) |
| 324 | #define CPSR_J (1U << 24) |
| 325 | #define CPSR_IT_0_1 (3U << 25) |
| 326 | #define CPSR_Q (1U << 27) |
| 327 | #define CPSR_V (1U << 28) |
| 328 | #define CPSR_C (1U << 29) |
| 329 | #define CPSR_Z (1U << 30) |
| 330 | #define CPSR_N (1U << 31) |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 331 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) |
| 332 | |
| 333 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) |
| 334 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) |
| 335 | /* Bits writable in user mode. */ |
| 336 | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) |
| 337 | /* Execution state bits. MRS read as zero, MSR writes ignored. */ |
| 338 | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) |
| 339 | |
| 340 | /* Return the current CPSR value. */ |
| 341 | uint32_t cpsr_read(CPUARMState *env); |
| 342 | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ |
| 343 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); |
| 344 | |
| 345 | /* Return the current xPSR value. */ |
| 346 | static inline uint32_t xpsr_read(CPUARMState *env) |
| 347 | { |
| 348 | int ZF; |
| 349 | ZF = (env->ZF == 0); |
| 350 | return (env->NF & 0x80000000) | (ZF << 30) |
| 351 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
| 352 | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) |
| 353 | | ((env->condexec_bits & 0xfc) << 8) |
| 354 | | env->v7m.exception; |
| 355 | } |
| 356 | |
| 357 | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
| 358 | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
| 359 | { |
| 360 | if (mask & CPSR_NZCV) { |
| 361 | env->ZF = (~val) & CPSR_Z; |
| 362 | env->NF = val; |
| 363 | env->CF = (val >> 29) & 1; |
| 364 | env->VF = (val << 3) & 0x80000000; |
| 365 | } |
| 366 | if (mask & CPSR_Q) |
| 367 | env->QF = ((val & CPSR_Q) != 0); |
| 368 | if (mask & (1 << 24)) |
| 369 | env->thumb = ((val & (1 << 24)) != 0); |
| 370 | if (mask & CPSR_IT_0_1) { |
| 371 | env->condexec_bits &= ~3; |
| 372 | env->condexec_bits |= (val >> 25) & 3; |
| 373 | } |
| 374 | if (mask & CPSR_IT_2_7) { |
| 375 | env->condexec_bits &= 3; |
| 376 | env->condexec_bits |= (val >> 8) & 0xfc; |
| 377 | } |
| 378 | if (mask & 0x1ff) { |
| 379 | env->v7m.exception = val & 0x1ff; |
| 380 | } |
| 381 | } |
| 382 | |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 383 | /* Return the current FPSCR value. */ |
| 384 | uint32_t vfp_get_fpscr(CPUARMState *env); |
| 385 | void vfp_set_fpscr(CPUARMState *env, uint32_t val); |
| 386 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 387 | enum arm_cpu_mode { |
| 388 | ARM_CPU_MODE_USR = 0x10, |
| 389 | ARM_CPU_MODE_FIQ = 0x11, |
| 390 | ARM_CPU_MODE_IRQ = 0x12, |
| 391 | ARM_CPU_MODE_SVC = 0x13, |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 392 | ARM_CPU_MODE_SMC = 0x16, |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 393 | ARM_CPU_MODE_ABT = 0x17, |
| 394 | ARM_CPU_MODE_UND = 0x1b, |
| 395 | ARM_CPU_MODE_SYS = 0x1f |
| 396 | }; |
| 397 | |
| 398 | /* VFP system registers. */ |
| 399 | #define ARM_VFP_FPSID 0 |
| 400 | #define ARM_VFP_FPSCR 1 |
| 401 | #define ARM_VFP_MVFR1 6 |
| 402 | #define ARM_VFP_MVFR0 7 |
| 403 | #define ARM_VFP_FPEXC 8 |
| 404 | #define ARM_VFP_FPINST 9 |
| 405 | #define ARM_VFP_FPINST2 10 |
| 406 | |
| 407 | /* iwMMXt coprocessor control registers. */ |
| 408 | #define ARM_IWMMXT_wCID 0 |
| 409 | #define ARM_IWMMXT_wCon 1 |
| 410 | #define ARM_IWMMXT_wCSSF 2 |
| 411 | #define ARM_IWMMXT_wCASF 3 |
| 412 | #define ARM_IWMMXT_wCGR0 8 |
| 413 | #define ARM_IWMMXT_wCGR1 9 |
| 414 | #define ARM_IWMMXT_wCGR2 10 |
| 415 | #define ARM_IWMMXT_wCGR3 11 |
| 416 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 417 | /* If adding a feature bit which corresponds to a Linux ELF |
| 418 | * HWCAP bit, remember to update the feature-bit-to-hwcap |
| 419 | * mapping in linux-user/elfload.c:get_elf_hwcap(). |
| 420 | */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 421 | enum arm_features { |
| 422 | ARM_FEATURE_VFP, |
| 423 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
| 424 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ |
| 425 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
| 426 | ARM_FEATURE_V6, |
| 427 | ARM_FEATURE_V6K, |
| 428 | ARM_FEATURE_V7, |
| 429 | ARM_FEATURE_THUMB2, |
| 430 | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ |
| 431 | ARM_FEATURE_VFP3, |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 432 | ARM_FEATURE_VFP_FP16, |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 433 | ARM_FEATURE_NEON, |
| 434 | ARM_FEATURE_DIV, |
| 435 | ARM_FEATURE_M, /* Microcontroller profile. */ |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 436 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 437 | ARM_FEATURE_THUMB2EE, |
| 438 | ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ |
| 439 | ARM_FEATURE_V4T, |
| 440 | ARM_FEATURE_V5, |
| 441 | ARM_FEATURE_STRONGARM, |
David 'Digit' Turner | 1811e78 | 2014-03-19 11:38:51 +0100 | [diff] [blame] | 442 | ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 443 | ARM_FEATURE_TRUSTZONE, /* TrustZone Security Extensions. */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 444 | }; |
| 445 | |
| 446 | static inline int arm_feature(CPUARMState *env, int feature) |
| 447 | { |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 448 | return (env->features & (1ULL << feature)) != 0; |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 449 | } |
| 450 | |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 451 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 452 | |
| 453 | /* Interface between CPU and Interrupt controller. */ |
| 454 | void armv7m_nvic_set_pending(void *opaque, int irq); |
| 455 | int armv7m_nvic_acknowledge_irq(void *opaque); |
| 456 | void armv7m_nvic_complete_irq(void *opaque, int irq); |
| 457 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 458 | /* Interface for defining coprocessor registers. |
| 459 | * Registers are defined in tables of arm_cp_reginfo structs |
| 460 | * which are passed to define_arm_cp_regs(). |
| 461 | */ |
| 462 | |
| 463 | /* When looking up a coprocessor register we look for it |
| 464 | * via an integer which encodes all of: |
| 465 | * coprocessor number |
| 466 | * Crn, Crm, opc1, opc2 fields |
| 467 | * 32 or 64 bit register (ie is it accessed via MRC/MCR |
| 468 | * or via MRRC/MCRR?) |
| 469 | * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. |
| 470 | * (In this case crn and opc2 should be zero.) |
| 471 | */ |
| 472 | #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ |
| 473 | (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ |
| 474 | ((crm) << 7) | ((opc1) << 3) | (opc2)) |
| 475 | |
| 476 | /* Convert a full 64 bit KVM register ID to the truncated 32 bit |
| 477 | * version used as a key for the coprocessor register hashtable |
| 478 | */ |
| 479 | static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) |
| 480 | { |
| 481 | uint32_t cpregid = kvmid; |
| 482 | if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { |
| 483 | cpregid |= (1 << 15); |
| 484 | } |
| 485 | return cpregid; |
| 486 | } |
| 487 | |
| 488 | /* Convert a truncated 32 bit hashtable key into the full |
| 489 | * 64 bit KVM register ID. |
| 490 | */ |
| 491 | static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) |
| 492 | { |
| 493 | uint64_t kvmid = cpregid & ~(1 << 15); |
| 494 | if (cpregid & (1 << 15)) { |
| 495 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; |
| 496 | } else { |
| 497 | kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; |
| 498 | } |
| 499 | return kvmid; |
| 500 | } |
| 501 | |
| 502 | /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a |
| 503 | * special-behaviour cp reg and bits [15..8] indicate what behaviour |
| 504 | * it has. Otherwise it is a simple cp reg, where CONST indicates that |
| 505 | * TCG can assume the value to be constant (ie load at translate time) |
| 506 | * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END |
| 507 | * indicates that the TB should not be ended after a write to this register |
| 508 | * (the default is that the TB ends after cp writes). OVERRIDE permits |
| 509 | * a register definition to override a previous definition for the |
| 510 | * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the |
| 511 | * old must have the OVERRIDE bit set. |
| 512 | * NO_MIGRATE indicates that this register should be ignored for migration; |
| 513 | * (eg because any state is accessed via some other coprocessor register). |
| 514 | * IO indicates that this register does I/O and therefore its accesses |
| 515 | * need to be surrounded by gen_io_start()/gen_io_end(). In particular, |
| 516 | * registers which implement clocks or timers require this. |
| 517 | */ |
| 518 | #define ARM_CP_SPECIAL 1 |
| 519 | #define ARM_CP_CONST 2 |
| 520 | #define ARM_CP_64BIT 4 |
| 521 | #define ARM_CP_SUPPRESS_TB_END 8 |
| 522 | #define ARM_CP_OVERRIDE 16 |
| 523 | #define ARM_CP_NO_MIGRATE 32 |
| 524 | #define ARM_CP_IO 64 |
| 525 | #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) |
| 526 | #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) |
| 527 | #define ARM_LAST_SPECIAL ARM_CP_WFI |
| 528 | /* Used only as a terminator for ARMCPRegInfo lists */ |
| 529 | #define ARM_CP_SENTINEL 0xffff |
| 530 | /* Mask of only the flag bits in a type field */ |
| 531 | #define ARM_CP_FLAG_MASK 0x7f |
| 532 | |
| 533 | /* Return true if cptype is a valid type field. This is used to try to |
| 534 | * catch errors where the sentinel has been accidentally left off the end |
| 535 | * of a list of registers. |
| 536 | */ |
| 537 | static inline bool cptype_valid(int cptype) |
| 538 | { |
| 539 | return ((cptype & ~ARM_CP_FLAG_MASK) == 0) |
| 540 | || ((cptype & ARM_CP_SPECIAL) && |
| 541 | ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); |
| 542 | } |
| 543 | |
| 544 | /* Access rights: |
| 545 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM |
| 546 | * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and |
| 547 | * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 |
| 548 | * (ie any of the privileged modes in Secure state, or Monitor mode). |
| 549 | * If a register is accessible in one privilege level it's always accessible |
| 550 | * in higher privilege levels too. Since "Secure PL1" also follows this rule |
| 551 | * (ie anything visible in PL2 is visible in S-PL1, some things are only |
| 552 | * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the |
| 553 | * terminology a little and call this PL3. |
| 554 | * |
| 555 | * If access permissions for a register are more complex than can be |
| 556 | * described with these bits, then use a laxer set of restrictions, and |
| 557 | * do the more restrictive/complex check inside a helper function. |
| 558 | */ |
| 559 | #define PL3_R 0x80 |
| 560 | #define PL3_W 0x40 |
| 561 | #define PL2_R (0x20 | PL3_R) |
| 562 | #define PL2_W (0x10 | PL3_W) |
| 563 | #define PL1_R (0x08 | PL2_R) |
| 564 | #define PL1_W (0x04 | PL2_W) |
| 565 | #define PL0_R (0x02 | PL1_R) |
| 566 | #define PL0_W (0x01 | PL1_W) |
| 567 | |
| 568 | #define PL3_RW (PL3_R | PL3_W) |
| 569 | #define PL2_RW (PL2_R | PL2_W) |
| 570 | #define PL1_RW (PL1_R | PL1_W) |
| 571 | #define PL0_RW (PL0_R | PL0_W) |
| 572 | |
| 573 | static inline int arm_current_pl(CPUARMState *env) |
| 574 | { |
| 575 | if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { |
| 576 | return 0; |
| 577 | } |
| 578 | /* We don't currently implement the Virtualization or TrustZone |
| 579 | * extensions, so PL2 and PL3 don't exist for us. |
| 580 | */ |
| 581 | return 1; |
| 582 | } |
| 583 | |
| 584 | typedef struct ARMCPRegInfo ARMCPRegInfo; |
| 585 | |
| 586 | /* Access functions for coprocessor registers. These should return |
| 587 | * 0 on success, or one of the EXCP_* constants if access should cause |
| 588 | * an exception (in which case *value is not written). |
| 589 | */ |
| 590 | typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque, |
| 591 | uint64_t *value); |
| 592 | typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, |
| 593 | uint64_t value); |
| 594 | /* Hook function for register reset */ |
| 595 | typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); |
| 596 | |
| 597 | #define CP_ANY 0xff |
| 598 | |
| 599 | /* Definition of an ARM coprocessor register */ |
| 600 | struct ARMCPRegInfo { |
| 601 | /* Name of register (useful mainly for debugging, need not be unique) */ |
| 602 | const char *name; |
| 603 | /* Location of register: coprocessor number and (crn,crm,opc1,opc2) |
| 604 | * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a |
| 605 | * 'wildcard' field -- any value of that field in the MRC/MCR insn |
| 606 | * will be decoded to this register. The register read and write |
| 607 | * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 |
| 608 | * used by the program, so it is possible to register a wildcard and |
| 609 | * then behave differently on read/write if necessary. |
| 610 | * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 |
| 611 | * must both be zero. |
| 612 | */ |
| 613 | uint8_t cp; |
| 614 | uint8_t crn; |
| 615 | uint8_t crm; |
| 616 | uint8_t opc1; |
| 617 | uint8_t opc2; |
| 618 | /* Register type: ARM_CP_* bits/values */ |
| 619 | int type; |
| 620 | /* Access rights: PL*_[RW] */ |
| 621 | int access; |
| 622 | /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when |
| 623 | * this register was defined: can be used to hand data through to the |
| 624 | * register read/write functions, since they are passed the ARMCPRegInfo*. |
| 625 | */ |
| 626 | void *opaque; |
| 627 | /* Value of this register, if it is ARM_CP_CONST. Otherwise, if |
| 628 | * fieldoffset is non-zero, the reset value of the register. |
| 629 | */ |
| 630 | uint64_t resetvalue; |
| 631 | /* Offset of the field in CPUARMState for this register. This is not |
| 632 | * needed if either: |
| 633 | * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs |
| 634 | * 2. both readfn and writefn are specified |
| 635 | */ |
| 636 | ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ |
| 637 | /* Function for handling reads of this register. If NULL, then reads |
| 638 | * will be done by loading from the offset into CPUARMState specified |
| 639 | * by fieldoffset. |
| 640 | */ |
| 641 | CPReadFn *readfn; |
| 642 | /* Function for handling writes of this register. If NULL, then writes |
| 643 | * will be done by writing to the offset into CPUARMState specified |
| 644 | * by fieldoffset. |
| 645 | */ |
| 646 | CPWriteFn *writefn; |
| 647 | /* Function for doing a "raw" read; used when we need to copy |
| 648 | * coprocessor state to the kernel for KVM or out for |
| 649 | * migration. This only needs to be provided if there is also a |
| 650 | * readfn and it makes an access permission check. |
| 651 | */ |
| 652 | CPReadFn *raw_readfn; |
| 653 | /* Function for doing a "raw" write; used when we need to copy KVM |
| 654 | * kernel coprocessor state into userspace, or for inbound |
| 655 | * migration. This only needs to be provided if there is also a |
| 656 | * writefn and it makes an access permission check or masks out |
| 657 | * "unwritable" bits or has write-one-to-clear or similar behaviour. |
| 658 | */ |
| 659 | CPWriteFn *raw_writefn; |
| 660 | /* Function for resetting the register. If NULL, then reset will be done |
| 661 | * by writing resetvalue to the field specified in fieldoffset. If |
| 662 | * fieldoffset is 0 then no reset will be done. |
| 663 | */ |
| 664 | CPResetFn *resetfn; |
| 665 | }; |
| 666 | |
| 667 | /* Macros which are lvalues for the field in CPUARMState for the |
| 668 | * ARMCPRegInfo *ri. |
| 669 | */ |
| 670 | #define CPREG_FIELD32(env, ri) \ |
| 671 | (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) |
| 672 | #define CPREG_FIELD64(env, ri) \ |
| 673 | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) |
| 674 | |
| 675 | #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } |
| 676 | |
| 677 | #ifndef CONFIG_ANDROID // TODO(digit): Implement ARMCPU |
| 678 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, |
| 679 | const ARMCPRegInfo *regs, void *opaque); |
| 680 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
| 681 | const ARMCPRegInfo *regs, void *opaque); |
| 682 | static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) |
| 683 | { |
| 684 | define_arm_cp_regs_with_opaque(cpu, regs, 0); |
| 685 | } |
| 686 | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) |
| 687 | { |
| 688 | define_one_arm_cp_reg_with_opaque(cpu, regs, 0); |
| 689 | } |
| 690 | const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp); |
| 691 | #endif // !CONFIG_ANDROID |
| 692 | |
| 693 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ |
| 694 | int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
| 695 | uint64_t value); |
| 696 | /* CPReadFn that can be used for read-as-zero behaviour */ |
| 697 | int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value); |
| 698 | |
| 699 | static inline bool cp_access_ok(CPUARMState *env, |
| 700 | const ARMCPRegInfo *ri, int isread) |
| 701 | { |
| 702 | return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1; |
| 703 | } |
| 704 | |
| 705 | #ifndef CONFIG_ANDROID // TODO(digit): Implement ARMCPU |
| 706 | /** |
| 707 | * write_list_to_cpustate |
| 708 | * @cpu: ARMCPU |
| 709 | * |
| 710 | * For each register listed in the ARMCPU cpreg_indexes list, write |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 711 | * its value from the cpreg_values list into the ARMCPUARMState structure. |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 712 | * This updates TCG's working data structures from KVM data or |
| 713 | * from incoming migration state. |
| 714 | * |
| 715 | * Returns: true if all register values were updated correctly, |
| 716 | * false if some register was unknown or could not be written. |
| 717 | * Note that we do not stop early on failure -- we will attempt |
| 718 | * writing all registers in the list. |
| 719 | */ |
| 720 | bool write_list_to_cpustate(ARMCPU *cpu); |
| 721 | |
| 722 | /** |
| 723 | * write_cpustate_to_list: |
| 724 | * @cpu: ARMCPU |
| 725 | * |
| 726 | * For each register listed in the ARMCPU cpreg_indexes list, write |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 727 | * its value from the ARMCPUARMState structure into the cpreg_values list. |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 728 | * This is used to copy info from TCG's working data structures into |
| 729 | * KVM or for outbound migration. |
| 730 | * |
| 731 | * Returns: true if all register values were read correctly, |
| 732 | * false if some register was unknown or could not be read. |
| 733 | * Note that we do not stop early on failure -- we will attempt |
| 734 | * reading all registers in the list. |
| 735 | */ |
| 736 | bool write_cpustate_to_list(ARMCPU *cpu); |
| 737 | #endif // !CONFIG_ANDROID |
| 738 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 739 | void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
| 740 | ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
| 741 | void *opaque); |
| 742 | |
| 743 | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. |
| 744 | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are |
| 745 | conventional cores (ie. Application or Realtime profile). */ |
| 746 | |
| 747 | #define IS_M(env) arm_feature(env, ARM_FEATURE_M) |
| 748 | #define ARM_CPUID(env) (env->cp15.c0_cpuid) |
| 749 | |
| 750 | #define ARM_CPUID_ARM1026 0x4106a262 |
| 751 | #define ARM_CPUID_ARM926 0x41069265 |
| 752 | #define ARM_CPUID_ARM946 0x41059461 |
| 753 | #define ARM_CPUID_TI915T 0x54029152 |
| 754 | #define ARM_CPUID_TI925T 0x54029252 |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 755 | #define ARM_CPUID_SA1100 0x4401A11B |
| 756 | #define ARM_CPUID_SA1110 0x6901B119 |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 757 | #define ARM_CPUID_PXA250 0x69052100 |
| 758 | #define ARM_CPUID_PXA255 0x69052d00 |
| 759 | #define ARM_CPUID_PXA260 0x69052903 |
| 760 | #define ARM_CPUID_PXA261 0x69052d05 |
| 761 | #define ARM_CPUID_PXA262 0x69052d06 |
| 762 | #define ARM_CPUID_PXA270 0x69054110 |
| 763 | #define ARM_CPUID_PXA270_A0 0x69054110 |
| 764 | #define ARM_CPUID_PXA270_A1 0x69054111 |
| 765 | #define ARM_CPUID_PXA270_B0 0x69054112 |
| 766 | #define ARM_CPUID_PXA270_B1 0x69054113 |
| 767 | #define ARM_CPUID_PXA270_C0 0x69054114 |
| 768 | #define ARM_CPUID_PXA270_C5 0x69054117 |
| 769 | #define ARM_CPUID_ARM1136 0x4117b363 |
| 770 | #define ARM_CPUID_ARM1136_R2 0x4107b362 |
David 'Digit' Turner | beefcee | 2014-03-20 17:48:20 +0100 | [diff] [blame] | 771 | #define ARM_CPUID_ARM1176 0x410fb767 |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 772 | #define ARM_CPUID_ARM11MPCORE 0x410fb022 |
| 773 | #define ARM_CPUID_CORTEXA8 0x410fc080 |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 774 | #define ARM_CPUID_CORTEXA8_R2 0x412fc083 |
David Turner | 6a9ef17 | 2010-09-09 22:54:36 +0200 | [diff] [blame] | 775 | #define ARM_CPUID_CORTEXA9 0x410fc090 |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 776 | #define ARM_CPUID_CORTEXM3 0x410fc231 |
| 777 | #define ARM_CPUID_ANY 0xffffffff |
| 778 | |
| 779 | #if defined(CONFIG_USER_ONLY) |
| 780 | #define TARGET_PAGE_BITS 12 |
| 781 | #else |
| 782 | /* The ARM MMU allows 1k pages. */ |
| 783 | /* ??? Linux doesn't actually use these, and they're deprecated in recent |
| 784 | architecture revisions. Maybe a configure option to disable them. */ |
| 785 | #define TARGET_PAGE_BITS 10 |
| 786 | #endif |
| 787 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 788 | #if defined(TARGET_AARCH64) |
| 789 | # define TARGET_PHYS_ADDR_SPACE_BITS 48 |
| 790 | # define TARGET_VIRT_ADDR_SPACE_BITS 64 |
| 791 | #else |
| 792 | # define TARGET_PHYS_ADDR_SPACE_BITS 40 |
| 793 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 |
| 794 | #endif |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 795 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 796 | #define cpu_init cpu_arm_init |
| 797 | #define cpu_exec cpu_arm_exec |
| 798 | #define cpu_gen_code cpu_arm_gen_code |
| 799 | #define cpu_signal_handler cpu_arm_signal_handler |
| 800 | #define cpu_list arm_cpu_list |
| 801 | |
David 'Digit' Turner | d9ac10a | 2014-03-19 11:01:43 +0100 | [diff] [blame] | 802 | #define CPU_SAVE_VERSION 4 |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 803 | |
| 804 | /* MMU modes definitions */ |
| 805 | #define MMU_MODE0_SUFFIX _kernel |
| 806 | #define MMU_MODE1_SUFFIX _user |
| 807 | #define MMU_USER_IDX 1 |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 808 | static inline int cpu_mmu_index (CPUARMState *env) |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 809 | { |
| 810 | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; |
| 811 | } |
| 812 | |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 813 | static inline int is_cpu_user (CPUARMState *env) |
Vladimir Chtchetkine | 5389aa1 | 2010-02-16 10:38:35 -0800 | [diff] [blame] | 814 | { |
| 815 | #ifdef CONFIG_USER_ONLY |
| 816 | return 1; |
| 817 | #else |
| 818 | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR; |
| 819 | #endif // CONFIG_USER_ONLY |
| 820 | } |
| 821 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 822 | #if defined(CONFIG_USER_ONLY) |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 823 | static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp) |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 824 | { |
| 825 | if (newsp) |
| 826 | env->regs[13] = newsp; |
| 827 | env->regs[0] = 0; |
| 828 | } |
| 829 | #endif |
| 830 | |
David 'Digit' Turner | 852088c | 2013-12-14 23:04:12 +0100 | [diff] [blame] | 831 | #include "exec/cpu-all.h" |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 832 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 833 | /* Bit usage in the TB flags field: bit 31 indicates whether we are |
| 834 | * in 32 or 64 bit mode. The meaning of the other bits depends on that. |
| 835 | */ |
| 836 | #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 |
| 837 | #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) |
| 838 | |
| 839 | /* Bit usage when in AArch32 state: */ |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 840 | #define ARM_TBFLAG_THUMB_SHIFT 0 |
| 841 | #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) |
| 842 | #define ARM_TBFLAG_VECLEN_SHIFT 1 |
| 843 | #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) |
| 844 | #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 |
| 845 | #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) |
| 846 | #define ARM_TBFLAG_PRIV_SHIFT 6 |
| 847 | #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) |
| 848 | #define ARM_TBFLAG_VFPEN_SHIFT 7 |
| 849 | #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) |
| 850 | #define ARM_TBFLAG_CONDEXEC_SHIFT 8 |
| 851 | #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 852 | #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 |
| 853 | #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) |
| 854 | |
| 855 | /* Bit usage when in AArch64 state: currently no bits defined */ |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 856 | |
| 857 | /* some convenience accessor macros */ |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 858 | #define ARM_TBFLAG_AARCH64_STATE(F) \ |
| 859 | (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 860 | #define ARM_TBFLAG_THUMB(F) \ |
| 861 | (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) |
| 862 | #define ARM_TBFLAG_VECLEN(F) \ |
| 863 | (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) |
| 864 | #define ARM_TBFLAG_VECSTRIDE(F) \ |
| 865 | (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) |
| 866 | #define ARM_TBFLAG_PRIV(F) \ |
| 867 | (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) |
| 868 | #define ARM_TBFLAG_VFPEN(F) \ |
| 869 | (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) |
| 870 | #define ARM_TBFLAG_CONDEXEC(F) \ |
| 871 | (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 872 | #define ARM_TBFLAG_BSWAP_CODE(F) \ |
| 873 | (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 874 | |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 875 | static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 876 | target_ulong *cs_base, int *flags) |
| 877 | { |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 878 | if (is_a64(env)) { |
| 879 | *pc = env->regs[15]; |
| 880 | *flags = ARM_TBFLAG_AARCH64_STATE_MASK; |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 881 | } else { |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 882 | int privmode; |
| 883 | *pc = env->regs[15]; |
| 884 | *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) |
| 885 | | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) |
| 886 | | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) |
| 887 | | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT); |
| 888 | // | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT); |
| 889 | if (arm_feature(env, ARM_FEATURE_M)) { |
| 890 | privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); |
| 891 | } else { |
| 892 | privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; |
| 893 | } |
| 894 | if (privmode) { |
| 895 | *flags |= ARM_TBFLAG_PRIV_MASK; |
| 896 | } |
| 897 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
| 898 | *flags |= ARM_TBFLAG_VFPEN_MASK; |
| 899 | } |
David 'Digit' Turner | 5285864 | 2011-06-03 13:41:05 +0200 | [diff] [blame] | 900 | } |
David 'Digit' Turner | 8512548 | 2014-01-14 14:08:54 +0100 | [diff] [blame] | 901 | |
| 902 | *cs_base = 0; |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 903 | } |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 904 | |
David 'Digit' Turner | 6657678 | 2014-03-24 16:57:57 +0100 | [diff] [blame] | 905 | static inline bool cpu_has_work(CPUState *cpu) |
David 'Digit' Turner | 93949dc | 2014-03-18 15:00:37 +0100 | [diff] [blame] | 906 | { |
David 'Digit' Turner | 6657678 | 2014-03-24 16:57:57 +0100 | [diff] [blame] | 907 | return (cpu->interrupt_request & |
David 'Digit' Turner | 93949dc | 2014-03-18 15:00:37 +0100 | [diff] [blame] | 908 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)); |
| 909 | } |
| 910 | |
| 911 | #include "exec/exec-all.h" |
| 912 | |
| 913 | static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) |
| 914 | { |
| 915 | env->regs[15] = tb->pc; |
| 916 | } |
| 917 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 918 | #endif |