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gerrit-public.fairphone.software / fp2-dev / platform / external / v8 / 4a90d5fbbb6802c59093b866f3478a814bf02b95 / . / src / compiler / ia32 / instruction-codes-ia32.h
blob: 816487db8c4688ebe5f4fad6a7541bb09acb3a4a [file] [log] [blame]
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]1// Copyright 2014 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
6#define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
7
8namespace v8 {
9namespace internal {
10namespace compiler {
11
12// IA32-specific opcodes that specify which assembly sequence to emit.
13// Most opcodes specify a single instruction.
14#define TARGET_ARCH_OPCODE_LIST(V) \
15 V(IA32Add) \
16 V(IA32And) \
17 V(IA32Cmp) \
18 V(IA32Test) \
19 V(IA32Or) \
20 V(IA32Xor) \
21 V(IA32Sub) \
22 V(IA32Imul) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]23 V(IA32ImulHigh) \
24 V(IA32UmulHigh) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]25 V(IA32Idiv) \
26 V(IA32Udiv) \
27 V(IA32Not) \
28 V(IA32Neg) \
29 V(IA32Shl) \
30 V(IA32Shr) \
31 V(IA32Sar) \
32 V(IA32Ror) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]33 V(IA32Lzcnt) \
34 V(IA32Tzcnt) \
35 V(IA32Popcnt) \
36 V(SSEFloat32Cmp) \
37 V(SSEFloat32Add) \
38 V(SSEFloat32Sub) \
39 V(SSEFloat32Mul) \
40 V(SSEFloat32Div) \
41 V(SSEFloat32Max) \
42 V(SSEFloat32Min) \
43 V(SSEFloat32Abs) \
44 V(SSEFloat32Neg) \
45 V(SSEFloat32Sqrt) \
46 V(SSEFloat32Round) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]47 V(SSEFloat64Cmp) \
48 V(SSEFloat64Add) \
49 V(SSEFloat64Sub) \
50 V(SSEFloat64Mul) \
51 V(SSEFloat64Div) \
52 V(SSEFloat64Mod) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]53 V(SSEFloat64Max) \
54 V(SSEFloat64Min) \
55 V(SSEFloat64Abs) \
56 V(SSEFloat64Neg) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]57 V(SSEFloat64Sqrt) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]58 V(SSEFloat64Round) \
59 V(SSEFloat32ToFloat64) \
60 V(SSEFloat64ToFloat32) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]61 V(SSEFloat64ToInt32) \
62 V(SSEFloat64ToUint32) \
63 V(SSEInt32ToFloat64) \
64 V(SSEUint32ToFloat64) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]65 V(SSEFloat64ExtractLowWord32) \
66 V(SSEFloat64ExtractHighWord32) \
67 V(SSEFloat64InsertLowWord32) \
68 V(SSEFloat64InsertHighWord32) \
69 V(SSEFloat64LoadLowWord32) \
70 V(AVXFloat32Add) \
71 V(AVXFloat32Sub) \
72 V(AVXFloat32Mul) \
73 V(AVXFloat32Div) \
74 V(AVXFloat32Max) \
75 V(AVXFloat32Min) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]76 V(AVXFloat64Add) \
77 V(AVXFloat64Sub) \
78 V(AVXFloat64Mul) \
79 V(AVXFloat64Div) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]80 V(AVXFloat64Max) \
81 V(AVXFloat64Min) \
82 V(AVXFloat64Abs) \
83 V(AVXFloat64Neg) \
84 V(AVXFloat32Abs) \
85 V(AVXFloat32Neg) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]86 V(IA32Movsxbl) \
87 V(IA32Movzxbl) \
88 V(IA32Movb) \
89 V(IA32Movsxwl) \
90 V(IA32Movzxwl) \
91 V(IA32Movw) \
92 V(IA32Movl) \
93 V(IA32Movss) \
94 V(IA32Movsd) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]95 V(IA32BitcastFI) \
96 V(IA32BitcastIF) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]97 V(IA32Lea) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]98 V(IA32Push) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]99 V(IA32PushFloat32) \
100 V(IA32PushFloat64) \
101 V(IA32Poke) \
102 V(IA32StackCheck)
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]103
104
105// Addressing modes represent the "shape" of inputs to an instruction.
106// Many instructions support multiple addressing modes. Addressing modes
107// are encoded into the InstructionCode of the instruction and tell the
108// code generator after register allocation which assembler method to call.
109//
110// We use the following local notation for addressing modes:
111//
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]112// M = memory operand
113// R = base register
114// N = index register * N for N in {1, 2, 4, 8}
115// I = immediate displacement (int32_t)
116
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]117#define TARGET_ADDRESSING_MODE_LIST(V) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]118 V(MR) /* [%r1 ] */ \
119 V(MRI) /* [%r1 + K] */ \
120 V(MR1) /* [%r1 + %r2*1 ] */ \
121 V(MR2) /* [%r1 + %r2*2 ] */ \
122 V(MR4) /* [%r1 + %r2*4 ] */ \
123 V(MR8) /* [%r1 + %r2*8 ] */ \
124 V(MR1I) /* [%r1 + %r2*1 + K] */ \
125 V(MR2I) /* [%r1 + %r2*2 + K] */ \
126 V(MR4I) /* [%r1 + %r2*3 + K] */ \
127 V(MR8I) /* [%r1 + %r2*4 + K] */ \
128 V(M1) /* [ %r2*1 ] */ \
129 V(M2) /* [ %r2*2 ] */ \
130 V(M4) /* [ %r2*4 ] */ \
131 V(M8) /* [ %r2*8 ] */ \
132 V(M1I) /* [ %r2*1 + K] */ \
133 V(M2I) /* [ %r2*2 + K] */ \
134 V(M4I) /* [ %r2*4 + K] */ \
135 V(M8I) /* [ %r2*8 + K] */ \
136 V(MI) /* [ K] */
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]137
138} // namespace compiler
139} // namespace internal
140} // namespace v8
141
142#endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_