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Steve Blocka7e24c12009-10-30 11:49:00 +00001// Copyright (c) 1994-2006 Sun Microsystems Inc.
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3//
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32
Leon Clarked91b9f72010-01-27 17:25:45 +000033// The original source code covered by the above license above has been
34// modified significantly by Google Inc.
35// Copyright 2010 the V8 project authors. All rights reserved.
Steve Blocka7e24c12009-10-30 11:49:00 +000036
37// A light-weight ARM Assembler
38// Generates user mode instructions for the ARM architecture up to version 5
39
40#ifndef V8_ARM_ASSEMBLER_ARM_H_
41#define V8_ARM_ASSEMBLER_ARM_H_
42#include <stdio.h>
43#include "assembler.h"
Steve Blockd0582a62009-12-15 09:54:21 +000044#include "serialize.h"
Steve Blocka7e24c12009-10-30 11:49:00 +000045
46namespace v8 {
47namespace internal {
48
49// CPU Registers.
50//
51// 1) We would prefer to use an enum, but enum values are assignment-
52// compatible with int, which has caused code-generation bugs.
53//
54// 2) We would prefer to use a class instead of a struct but we don't like
55// the register initialization to depend on the particular initialization
56// order (which appears to be different on OS X, Linux, and Windows for the
57// installed versions of C++ we tried). Using a struct permits C-style
58// "initialization". Also, the Register objects cannot be const as this
59// forces initialization stubs in MSVC, making us dependent on initialization
60// order.
61//
62// 3) By not using an enum, we are possibly preventing the compiler from
63// doing certain constant folds, which may significantly reduce the
64// code generated for some assembly instructions (because they boil down
65// to a few constants). If this is a problem, we could change the code
66// such that we use an enum in optimized mode, and the struct in debug
67// mode. This way we get the compile-time error checking in debug mode
68// and best performance in optimized code.
69//
70// Core register
71struct Register {
72 bool is_valid() const { return 0 <= code_ && code_ < 16; }
73 bool is(Register reg) const { return code_ == reg.code_; }
74 int code() const {
75 ASSERT(is_valid());
76 return code_;
77 }
78 int bit() const {
79 ASSERT(is_valid());
80 return 1 << code_;
81 }
82
Leon Clarkef7060e22010-06-03 12:02:55 +010083 void set_code(int code) {
84 code_ = code;
85 ASSERT(is_valid());
86 }
87
Andrei Popescu31002712010-02-23 13:46:05 +000088 // Unfortunately we can't make this private in a struct.
Steve Blocka7e24c12009-10-30 11:49:00 +000089 int code_;
90};
91
Steve Block6ded16b2010-05-10 14:33:55 +010092const Register no_reg = { -1 };
Steve Blocka7e24c12009-10-30 11:49:00 +000093
Steve Block6ded16b2010-05-10 14:33:55 +010094const Register r0 = { 0 };
95const Register r1 = { 1 };
96const Register r2 = { 2 };
97const Register r3 = { 3 };
98const Register r4 = { 4 };
99const Register r5 = { 5 };
100const Register r6 = { 6 };
101const Register r7 = { 7 };
102const Register r8 = { 8 }; // Used as context register.
103const Register r9 = { 9 };
104const Register r10 = { 10 }; // Used as roots register.
105const Register fp = { 11 };
106const Register ip = { 12 };
107const Register sp = { 13 };
108const Register lr = { 14 };
109const Register pc = { 15 };
Steve Blockd0582a62009-12-15 09:54:21 +0000110
Leon Clarkee46be812010-01-19 14:06:41 +0000111// Single word VFP register.
112struct SwVfpRegister {
113 bool is_valid() const { return 0 <= code_ && code_ < 32; }
114 bool is(SwVfpRegister reg) const { return code_ == reg.code_; }
115 int code() const {
116 ASSERT(is_valid());
117 return code_;
118 }
119 int bit() const {
120 ASSERT(is_valid());
121 return 1 << code_;
122 }
123
124 int code_;
125};
126
127
128// Double word VFP register.
129struct DwVfpRegister {
130 // Supporting d0 to d15, can be later extended to d31.
131 bool is_valid() const { return 0 <= code_ && code_ < 16; }
132 bool is(DwVfpRegister reg) const { return code_ == reg.code_; }
Ben Murdoch3bec4d22010-07-22 14:51:16 +0100133 SwVfpRegister low() const {
134 SwVfpRegister reg;
135 reg.code_ = code_ * 2;
136
137 ASSERT(reg.is_valid());
138 return reg;
139 }
140 SwVfpRegister high() const {
141 SwVfpRegister reg;
142 reg.code_ = (code_ * 2) + 1;
143
144 ASSERT(reg.is_valid());
145 return reg;
146 }
Leon Clarkee46be812010-01-19 14:06:41 +0000147 int code() const {
148 ASSERT(is_valid());
149 return code_;
150 }
151 int bit() const {
152 ASSERT(is_valid());
153 return 1 << code_;
154 }
155
156 int code_;
157};
158
159
Steve Block6ded16b2010-05-10 14:33:55 +0100160// Support for the VFP registers s0 to s31 (d0 to d15).
Leon Clarkee46be812010-01-19 14:06:41 +0000161// Note that "s(N):s(N+1)" is the same as "d(N/2)".
Steve Block6ded16b2010-05-10 14:33:55 +0100162const SwVfpRegister s0 = { 0 };
163const SwVfpRegister s1 = { 1 };
164const SwVfpRegister s2 = { 2 };
165const SwVfpRegister s3 = { 3 };
166const SwVfpRegister s4 = { 4 };
167const SwVfpRegister s5 = { 5 };
168const SwVfpRegister s6 = { 6 };
169const SwVfpRegister s7 = { 7 };
170const SwVfpRegister s8 = { 8 };
171const SwVfpRegister s9 = { 9 };
172const SwVfpRegister s10 = { 10 };
173const SwVfpRegister s11 = { 11 };
174const SwVfpRegister s12 = { 12 };
175const SwVfpRegister s13 = { 13 };
176const SwVfpRegister s14 = { 14 };
177const SwVfpRegister s15 = { 15 };
178const SwVfpRegister s16 = { 16 };
179const SwVfpRegister s17 = { 17 };
180const SwVfpRegister s18 = { 18 };
181const SwVfpRegister s19 = { 19 };
182const SwVfpRegister s20 = { 20 };
183const SwVfpRegister s21 = { 21 };
184const SwVfpRegister s22 = { 22 };
185const SwVfpRegister s23 = { 23 };
186const SwVfpRegister s24 = { 24 };
187const SwVfpRegister s25 = { 25 };
188const SwVfpRegister s26 = { 26 };
189const SwVfpRegister s27 = { 27 };
190const SwVfpRegister s28 = { 28 };
191const SwVfpRegister s29 = { 29 };
192const SwVfpRegister s30 = { 30 };
193const SwVfpRegister s31 = { 31 };
Leon Clarkee46be812010-01-19 14:06:41 +0000194
Steve Block6ded16b2010-05-10 14:33:55 +0100195const DwVfpRegister d0 = { 0 };
196const DwVfpRegister d1 = { 1 };
197const DwVfpRegister d2 = { 2 };
198const DwVfpRegister d3 = { 3 };
199const DwVfpRegister d4 = { 4 };
200const DwVfpRegister d5 = { 5 };
201const DwVfpRegister d6 = { 6 };
202const DwVfpRegister d7 = { 7 };
203const DwVfpRegister d8 = { 8 };
204const DwVfpRegister d9 = { 9 };
205const DwVfpRegister d10 = { 10 };
206const DwVfpRegister d11 = { 11 };
207const DwVfpRegister d12 = { 12 };
208const DwVfpRegister d13 = { 13 };
209const DwVfpRegister d14 = { 14 };
210const DwVfpRegister d15 = { 15 };
Leon Clarkee46be812010-01-19 14:06:41 +0000211
Steve Blocka7e24c12009-10-30 11:49:00 +0000212
213// Coprocessor register
214struct CRegister {
215 bool is_valid() const { return 0 <= code_ && code_ < 16; }
216 bool is(CRegister creg) const { return code_ == creg.code_; }
217 int code() const {
218 ASSERT(is_valid());
219 return code_;
220 }
221 int bit() const {
222 ASSERT(is_valid());
223 return 1 << code_;
224 }
225
Andrei Popescu31002712010-02-23 13:46:05 +0000226 // Unfortunately we can't make this private in a struct.
Steve Blocka7e24c12009-10-30 11:49:00 +0000227 int code_;
228};
229
230
Steve Block6ded16b2010-05-10 14:33:55 +0100231const CRegister no_creg = { -1 };
232
233const CRegister cr0 = { 0 };
234const CRegister cr1 = { 1 };
235const CRegister cr2 = { 2 };
236const CRegister cr3 = { 3 };
237const CRegister cr4 = { 4 };
238const CRegister cr5 = { 5 };
239const CRegister cr6 = { 6 };
240const CRegister cr7 = { 7 };
241const CRegister cr8 = { 8 };
242const CRegister cr9 = { 9 };
243const CRegister cr10 = { 10 };
244const CRegister cr11 = { 11 };
245const CRegister cr12 = { 12 };
246const CRegister cr13 = { 13 };
247const CRegister cr14 = { 14 };
248const CRegister cr15 = { 15 };
Steve Blocka7e24c12009-10-30 11:49:00 +0000249
250
251// Coprocessor number
252enum Coprocessor {
253 p0 = 0,
254 p1 = 1,
255 p2 = 2,
256 p3 = 3,
257 p4 = 4,
258 p5 = 5,
259 p6 = 6,
260 p7 = 7,
261 p8 = 8,
262 p9 = 9,
263 p10 = 10,
264 p11 = 11,
265 p12 = 12,
266 p13 = 13,
267 p14 = 14,
268 p15 = 15
269};
270
271
Andrei Popescu31002712010-02-23 13:46:05 +0000272// Condition field in instructions.
Steve Blocka7e24c12009-10-30 11:49:00 +0000273enum Condition {
274 eq = 0 << 28, // Z set equal.
275 ne = 1 << 28, // Z clear not equal.
276 nz = 1 << 28, // Z clear not zero.
277 cs = 2 << 28, // C set carry set.
278 hs = 2 << 28, // C set unsigned higher or same.
279 cc = 3 << 28, // C clear carry clear.
280 lo = 3 << 28, // C clear unsigned lower.
281 mi = 4 << 28, // N set negative.
282 pl = 5 << 28, // N clear positive or zero.
283 vs = 6 << 28, // V set overflow.
284 vc = 7 << 28, // V clear no overflow.
285 hi = 8 << 28, // C set, Z clear unsigned higher.
286 ls = 9 << 28, // C clear or Z set unsigned lower or same.
287 ge = 10 << 28, // N == V greater or equal.
288 lt = 11 << 28, // N != V less than.
289 gt = 12 << 28, // Z clear, N == V greater than.
290 le = 13 << 28, // Z set or N != V less then or equal
291 al = 14 << 28 // always.
292};
293
294
295// Returns the equivalent of !cc.
Kristian Monsen9dcf7e22010-06-28 14:14:28 +0100296inline Condition NegateCondition(Condition cc) {
297 ASSERT(cc != al);
298 return static_cast<Condition>(cc ^ ne);
299}
Steve Blocka7e24c12009-10-30 11:49:00 +0000300
301
302// Corresponds to transposing the operands of a comparison.
303inline Condition ReverseCondition(Condition cc) {
304 switch (cc) {
305 case lo:
306 return hi;
307 case hi:
308 return lo;
309 case hs:
310 return ls;
311 case ls:
312 return hs;
313 case lt:
314 return gt;
315 case gt:
316 return lt;
317 case ge:
318 return le;
319 case le:
320 return ge;
321 default:
322 return cc;
323 };
324}
325
326
327// Branch hints are not used on the ARM. They are defined so that they can
328// appear in shared function signatures, but will be ignored in ARM
329// implementations.
330enum Hint { no_hint };
331
332// Hints are not used on the arm. Negating is trivial.
333inline Hint NegateHint(Hint ignored) { return no_hint; }
334
335
336// -----------------------------------------------------------------------------
337// Addressing modes and instruction variants
338
339// Shifter operand shift operation
340enum ShiftOp {
341 LSL = 0 << 5,
342 LSR = 1 << 5,
343 ASR = 2 << 5,
344 ROR = 3 << 5,
345 RRX = -1
346};
347
348
349// Condition code updating mode
350enum SBit {
351 SetCC = 1 << 20, // set condition code
352 LeaveCC = 0 << 20 // leave condition code unchanged
353};
354
355
356// Status register selection
357enum SRegister {
358 CPSR = 0 << 22,
359 SPSR = 1 << 22
360};
361
362
363// Status register fields
364enum SRegisterField {
365 CPSR_c = CPSR | 1 << 16,
366 CPSR_x = CPSR | 1 << 17,
367 CPSR_s = CPSR | 1 << 18,
368 CPSR_f = CPSR | 1 << 19,
369 SPSR_c = SPSR | 1 << 16,
370 SPSR_x = SPSR | 1 << 17,
371 SPSR_s = SPSR | 1 << 18,
372 SPSR_f = SPSR | 1 << 19
373};
374
375// Status register field mask (or'ed SRegisterField enum values)
376typedef uint32_t SRegisterFieldMask;
377
378
379// Memory operand addressing mode
380enum AddrMode {
381 // bit encoding P U W
382 Offset = (8|4|0) << 21, // offset (without writeback to base)
383 PreIndex = (8|4|1) << 21, // pre-indexed addressing with writeback
384 PostIndex = (0|4|0) << 21, // post-indexed addressing with writeback
385 NegOffset = (8|0|0) << 21, // negative offset (without writeback to base)
386 NegPreIndex = (8|0|1) << 21, // negative pre-indexed with writeback
387 NegPostIndex = (0|0|0) << 21 // negative post-indexed with writeback
388};
389
390
391// Load/store multiple addressing mode
392enum BlockAddrMode {
393 // bit encoding P U W
394 da = (0|0|0) << 21, // decrement after
395 ia = (0|4|0) << 21, // increment after
396 db = (8|0|0) << 21, // decrement before
397 ib = (8|4|0) << 21, // increment before
398 da_w = (0|0|1) << 21, // decrement after with writeback to base
399 ia_w = (0|4|1) << 21, // increment after with writeback to base
400 db_w = (8|0|1) << 21, // decrement before with writeback to base
401 ib_w = (8|4|1) << 21 // increment before with writeback to base
402};
403
404
405// Coprocessor load/store operand size
406enum LFlag {
407 Long = 1 << 22, // long load/store coprocessor
408 Short = 0 << 22 // short load/store coprocessor
409};
410
411
412// -----------------------------------------------------------------------------
413// Machine instruction Operands
414
415// Class Operand represents a shifter operand in data processing instructions
416class Operand BASE_EMBEDDED {
417 public:
418 // immediate
419 INLINE(explicit Operand(int32_t immediate,
420 RelocInfo::Mode rmode = RelocInfo::NONE));
421 INLINE(explicit Operand(const ExternalReference& f));
422 INLINE(explicit Operand(const char* s));
Steve Blocka7e24c12009-10-30 11:49:00 +0000423 explicit Operand(Handle<Object> handle);
424 INLINE(explicit Operand(Smi* value));
425
426 // rm
427 INLINE(explicit Operand(Register rm));
428
429 // rm <shift_op> shift_imm
430 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
431
432 // rm <shift_op> rs
433 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
434
435 // Return true if this is a register operand.
436 INLINE(bool is_reg() const);
437
Kristian Monsen9dcf7e22010-06-28 14:14:28 +0100438 // Return true of this operand fits in one instruction so that no
439 // 2-instruction solution with a load into the ip register is necessary.
440 bool is_single_instruction() const;
441
442 inline int32_t immediate() const {
443 ASSERT(!rm_.is_valid());
444 return imm32_;
445 }
446
Steve Blocka7e24c12009-10-30 11:49:00 +0000447 Register rm() const { return rm_; }
448
449 private:
450 Register rm_;
451 Register rs_;
452 ShiftOp shift_op_;
453 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg
454 int32_t imm32_; // valid if rm_ == no_reg
455 RelocInfo::Mode rmode_;
456
457 friend class Assembler;
458};
459
460
461// Class MemOperand represents a memory operand in load and store instructions
462class MemOperand BASE_EMBEDDED {
463 public:
464 // [rn +/- offset] Offset/NegOffset
465 // [rn +/- offset]! PreIndex/NegPreIndex
466 // [rn], +/- offset PostIndex/NegPostIndex
467 // offset is any signed 32-bit value; offset is first loaded to register ip if
468 // it does not fit the addressing mode (12-bit unsigned and sign bit)
469 explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset);
470
471 // [rn +/- rm] Offset/NegOffset
472 // [rn +/- rm]! PreIndex/NegPreIndex
473 // [rn], +/- rm PostIndex/NegPostIndex
474 explicit MemOperand(Register rn, Register rm, AddrMode am = Offset);
475
476 // [rn +/- rm <shift_op> shift_imm] Offset/NegOffset
477 // [rn +/- rm <shift_op> shift_imm]! PreIndex/NegPreIndex
478 // [rn], +/- rm <shift_op> shift_imm PostIndex/NegPostIndex
479 explicit MemOperand(Register rn, Register rm,
480 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
481
Kristian Monsen25f61362010-05-21 11:50:48 +0100482 void set_offset(int32_t offset) {
483 ASSERT(rm_.is(no_reg));
484 offset_ = offset;
485 }
486
487 uint32_t offset() {
488 ASSERT(rm_.is(no_reg));
489 return offset_;
490 }
491
Leon Clarkef7060e22010-06-03 12:02:55 +0100492 Register rn() const { return rn_; }
493 Register rm() const { return rm_; }
Kristian Monsen25f61362010-05-21 11:50:48 +0100494
Steve Blocka7e24c12009-10-30 11:49:00 +0000495 private:
496 Register rn_; // base
497 Register rm_; // register offset
498 int32_t offset_; // valid if rm_ == no_reg
499 ShiftOp shift_op_;
500 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg
501 AddrMode am_; // bits P, U, and W
502
503 friend class Assembler;
504};
505
Steve Blockd0582a62009-12-15 09:54:21 +0000506// CpuFeatures keeps track of which features are supported by the target CPU.
507// Supported features must be enabled by a Scope before use.
508class CpuFeatures : public AllStatic {
509 public:
510 // Detect features of the target CPU. Set safe defaults if the serializer
511 // is enabled (snapshots must be portable).
512 static void Probe();
513
514 // Check whether a feature is supported by the target CPU.
515 static bool IsSupported(CpuFeature f) {
516 if (f == VFP3 && !FLAG_enable_vfp3) return false;
517 return (supported_ & (1u << f)) != 0;
518 }
519
520 // Check whether a feature is currently enabled.
521 static bool IsEnabled(CpuFeature f) {
522 return (enabled_ & (1u << f)) != 0;
523 }
524
525 // Enable a specified feature within a scope.
526 class Scope BASE_EMBEDDED {
527#ifdef DEBUG
528 public:
529 explicit Scope(CpuFeature f) {
530 ASSERT(CpuFeatures::IsSupported(f));
531 ASSERT(!Serializer::enabled() ||
532 (found_by_runtime_probing_ & (1u << f)) == 0);
533 old_enabled_ = CpuFeatures::enabled_;
534 CpuFeatures::enabled_ |= 1u << f;
535 }
536 ~Scope() { CpuFeatures::enabled_ = old_enabled_; }
537 private:
538 unsigned old_enabled_;
539#else
540 public:
541 explicit Scope(CpuFeature f) {}
542#endif
543 };
544
545 private:
546 static unsigned supported_;
547 static unsigned enabled_;
548 static unsigned found_by_runtime_probing_;
549};
550
Steve Blocka7e24c12009-10-30 11:49:00 +0000551
552typedef int32_t Instr;
553
554
555extern const Instr kMovLrPc;
Steve Block6ded16b2010-05-10 14:33:55 +0100556extern const Instr kLdrPCMask;
Steve Blocka7e24c12009-10-30 11:49:00 +0000557extern const Instr kLdrPCPattern;
Steve Block6ded16b2010-05-10 14:33:55 +0100558extern const Instr kBlxRegMask;
559extern const Instr kBlxRegPattern;
Steve Blocka7e24c12009-10-30 11:49:00 +0000560
Kristian Monsen9dcf7e22010-06-28 14:14:28 +0100561extern const Instr kMovMvnMask;
562extern const Instr kMovMvnPattern;
563extern const Instr kMovMvnFlip;
564
565extern const Instr kMovLeaveCCMask;
566extern const Instr kMovLeaveCCPattern;
567extern const Instr kMovwMask;
568extern const Instr kMovwPattern;
569extern const Instr kMovwLeaveCCFlip;
570
571extern const Instr kCmpCmnMask;
572extern const Instr kCmpCmnPattern;
573extern const Instr kCmpCmnFlip;
574
575extern const Instr kALUMask;
576extern const Instr kAddPattern;
577extern const Instr kSubPattern;
578extern const Instr kAndPattern;
579extern const Instr kBicPattern;
580extern const Instr kAddSubFlip;
581extern const Instr kAndBicFlip;
Steve Blocka7e24c12009-10-30 11:49:00 +0000582
583class Assembler : public Malloced {
584 public:
585 // Create an assembler. Instructions and relocation information are emitted
586 // into a buffer, with the instructions starting from the beginning and the
587 // relocation information starting from the end of the buffer. See CodeDesc
588 // for a detailed comment on the layout (globals.h).
589 //
590 // If the provided buffer is NULL, the assembler allocates and grows its own
591 // buffer, and buffer_size determines the initial buffer size. The buffer is
592 // owned by the assembler and deallocated upon destruction of the assembler.
593 //
594 // If the provided buffer is not NULL, the assembler uses the provided buffer
595 // for code generation and assumes its size to be buffer_size. If the buffer
596 // is too small, a fatal error occurs. No deallocation of the buffer is done
597 // upon destruction of the assembler.
598 Assembler(void* buffer, int buffer_size);
599 ~Assembler();
600
601 // GetCode emits any pending (non-emitted) code and fills the descriptor
602 // desc. GetCode() is idempotent; it returns the same result if no other
603 // Assembler functions are invoked in between GetCode() calls.
604 void GetCode(CodeDesc* desc);
605
606 // Label operations & relative jumps (PPUM Appendix D)
607 //
608 // Takes a branch opcode (cc) and a label (L) and generates
609 // either a backward branch or a forward branch and links it
610 // to the label fixup chain. Usage:
611 //
612 // Label L; // unbound label
613 // j(cc, &L); // forward branch to unbound label
614 // bind(&L); // bind label to the current pc
615 // j(cc, &L); // backward branch to bound label
616 // bind(&L); // illegal: a label may be bound only once
617 //
618 // Note: The same Label can be used for forward and backward branches
619 // but it may be bound only once.
620
621 void bind(Label* L); // binds an unbound label L to the current code position
622
623 // Returns the branch offset to the given label from the current code position
624 // Links the label to the current position if it is still unbound
625 // Manages the jump elimination optimization if the second parameter is true.
626 int branch_offset(Label* L, bool jump_elimination_allowed);
627
628 // Puts a labels target address at the given position.
629 // The high 8 bits are set to zero.
630 void label_at_put(Label* L, int at_offset);
631
632 // Return the address in the constant pool of the code target address used by
633 // the branch/call instruction at pc.
634 INLINE(static Address target_address_address_at(Address pc));
635
636 // Read/Modify the code target address in the branch/call instruction at pc.
637 INLINE(static Address target_address_at(Address pc));
638 INLINE(static void set_target_address_at(Address pc, Address target));
639
Steve Blockd0582a62009-12-15 09:54:21 +0000640 // This sets the branch destination (which is in the constant pool on ARM).
641 // This is for calls and branches within generated code.
642 inline static void set_target_at(Address constant_pool_entry, Address target);
643
644 // This sets the branch destination (which is in the constant pool on ARM).
645 // This is for calls and branches to runtime code.
646 inline static void set_external_target_at(Address constant_pool_entry,
647 Address target) {
648 set_target_at(constant_pool_entry, target);
649 }
650
651 // Here we are patching the address in the constant pool, not the actual call
652 // instruction. The address in the constant pool is the same size as a
653 // pointer.
654 static const int kCallTargetSize = kPointerSize;
655 static const int kExternalTargetSize = kPointerSize;
656
Steve Blocka7e24c12009-10-30 11:49:00 +0000657 // Size of an instruction.
658 static const int kInstrSize = sizeof(Instr);
659
660 // Distance between the instruction referring to the address of the call
Steve Block6ded16b2010-05-10 14:33:55 +0100661 // target and the return address.
662#ifdef USE_BLX
663 // Call sequence is:
664 // ldr ip, [pc, #...] @ call address
665 // blx ip
666 // @ return address
667 static const int kCallTargetAddressOffset = 2 * kInstrSize;
668#else
669 // Call sequence is:
670 // mov lr, pc
671 // ldr pc, [pc, #...] @ call address
672 // @ return address
Steve Blocka7e24c12009-10-30 11:49:00 +0000673 static const int kCallTargetAddressOffset = kInstrSize;
Steve Block6ded16b2010-05-10 14:33:55 +0100674#endif
Steve Blocka7e24c12009-10-30 11:49:00 +0000675
676 // Distance between start of patched return sequence and the emitted address
677 // to jump to.
Steve Block6ded16b2010-05-10 14:33:55 +0100678#ifdef USE_BLX
Ben Murdoch7f4d5bd2010-06-15 11:15:29 +0100679 // Patched return sequence is:
Steve Block6ded16b2010-05-10 14:33:55 +0100680 // ldr ip, [pc, #0] @ emited address and start
681 // blx ip
682 static const int kPatchReturnSequenceAddressOffset = 0 * kInstrSize;
683#else
Ben Murdoch7f4d5bd2010-06-15 11:15:29 +0100684 // Patched return sequence is:
Steve Block6ded16b2010-05-10 14:33:55 +0100685 // mov lr, pc @ start of sequence
686 // ldr pc, [pc, #-4] @ emited address
687 static const int kPatchReturnSequenceAddressOffset = kInstrSize;
688#endif
Steve Blocka7e24c12009-10-30 11:49:00 +0000689
Ben Murdoch7f4d5bd2010-06-15 11:15:29 +0100690 // Distance between start of patched debug break slot and the emitted address
691 // to jump to.
692#ifdef USE_BLX
693 // Patched debug break slot code is:
694 // ldr ip, [pc, #0] @ emited address and start
695 // blx ip
696 static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize;
697#else
698 // Patched debug break slot code is:
699 // mov lr, pc @ start of sequence
700 // ldr pc, [pc, #-4] @ emited address
701 static const int kPatchDebugBreakSlotAddressOffset = kInstrSize;
702#endif
703
Steve Blocka7e24c12009-10-30 11:49:00 +0000704 // Difference between address of current opcode and value read from pc
705 // register.
706 static const int kPcLoadDelta = 8;
707
Ben Murdoch7f4d5bd2010-06-15 11:15:29 +0100708 static const int kJSReturnSequenceInstructions = 4;
709 static const int kDebugBreakSlotInstructions = 3;
710 static const int kDebugBreakSlotLength =
711 kDebugBreakSlotInstructions * kInstrSize;
Steve Blocka7e24c12009-10-30 11:49:00 +0000712
713 // ---------------------------------------------------------------------------
714 // Code generation
715
716 // Insert the smallest number of nop instructions
717 // possible to align the pc offset to a multiple
718 // of m. m must be a power of 2 (>= 4).
719 void Align(int m);
Kristian Monsen9dcf7e22010-06-28 14:14:28 +0100720 // Aligns code to something that's optimal for a jump target for the platform.
721 void CodeTargetAlign();
Steve Blocka7e24c12009-10-30 11:49:00 +0000722
723 // Branch instructions
724 void b(int branch_offset, Condition cond = al);
725 void bl(int branch_offset, Condition cond = al);
726 void blx(int branch_offset); // v5 and above
727 void blx(Register target, Condition cond = al); // v5 and above
728 void bx(Register target, Condition cond = al); // v5 and above, plus v4t
729
730 // Convenience branch instructions using labels
731 void b(Label* L, Condition cond = al) {
732 b(branch_offset(L, cond == al), cond);
733 }
734 void b(Condition cond, Label* L) { b(branch_offset(L, cond == al), cond); }
735 void bl(Label* L, Condition cond = al) { bl(branch_offset(L, false), cond); }
736 void bl(Condition cond, Label* L) { bl(branch_offset(L, false), cond); }
737 void blx(Label* L) { blx(branch_offset(L, false)); } // v5 and above
738
739 // Data-processing instructions
Andrei Popescu31002712010-02-23 13:46:05 +0000740
Steve Blocka7e24c12009-10-30 11:49:00 +0000741 void and_(Register dst, Register src1, const Operand& src2,
742 SBit s = LeaveCC, Condition cond = al);
743
744 void eor(Register dst, Register src1, const Operand& src2,
745 SBit s = LeaveCC, Condition cond = al);
746
747 void sub(Register dst, Register src1, const Operand& src2,
748 SBit s = LeaveCC, Condition cond = al);
749 void sub(Register dst, Register src1, Register src2,
750 SBit s = LeaveCC, Condition cond = al) {
751 sub(dst, src1, Operand(src2), s, cond);
752 }
753
754 void rsb(Register dst, Register src1, const Operand& src2,
755 SBit s = LeaveCC, Condition cond = al);
756
757 void add(Register dst, Register src1, const Operand& src2,
758 SBit s = LeaveCC, Condition cond = al);
Ben Murdoch7f4d5bd2010-06-15 11:15:29 +0100759 void add(Register dst, Register src1, Register src2,
760 SBit s = LeaveCC, Condition cond = al) {
761 add(dst, src1, Operand(src2), s, cond);
762 }
Steve Blocka7e24c12009-10-30 11:49:00 +0000763
764 void adc(Register dst, Register src1, const Operand& src2,
765 SBit s = LeaveCC, Condition cond = al);
766
767 void sbc(Register dst, Register src1, const Operand& src2,
768 SBit s = LeaveCC, Condition cond = al);
769
770 void rsc(Register dst, Register src1, const Operand& src2,
771 SBit s = LeaveCC, Condition cond = al);
772
773 void tst(Register src1, const Operand& src2, Condition cond = al);
774 void tst(Register src1, Register src2, Condition cond = al) {
775 tst(src1, Operand(src2), cond);
776 }
777
778 void teq(Register src1, const Operand& src2, Condition cond = al);
779
780 void cmp(Register src1, const Operand& src2, Condition cond = al);
781 void cmp(Register src1, Register src2, Condition cond = al) {
782 cmp(src1, Operand(src2), cond);
783 }
784
785 void cmn(Register src1, const Operand& src2, Condition cond = al);
786
787 void orr(Register dst, Register src1, const Operand& src2,
788 SBit s = LeaveCC, Condition cond = al);
789 void orr(Register dst, Register src1, Register src2,
790 SBit s = LeaveCC, Condition cond = al) {
791 orr(dst, src1, Operand(src2), s, cond);
792 }
793
794 void mov(Register dst, const Operand& src,
795 SBit s = LeaveCC, Condition cond = al);
796 void mov(Register dst, Register src, SBit s = LeaveCC, Condition cond = al) {
797 mov(dst, Operand(src), s, cond);
798 }
799
Kristian Monsen9dcf7e22010-06-28 14:14:28 +0100800 // ARMv7 instructions for loading a 32 bit immediate in two instructions.
801 // This may actually emit a different mov instruction, but on an ARMv7 it
802 // is guaranteed to only emit one instruction.
803 void movw(Register reg, uint32_t immediate, Condition cond = al);
804 // The constant for movt should be in the range 0-0xffff.
805 void movt(Register reg, uint32_t immediate, Condition cond = al);
806
Steve Blocka7e24c12009-10-30 11:49:00 +0000807 void bic(Register dst, Register src1, const Operand& src2,
808 SBit s = LeaveCC, Condition cond = al);
809
810 void mvn(Register dst, const Operand& src,
811 SBit s = LeaveCC, Condition cond = al);
812
813 // Multiply instructions
814
815 void mla(Register dst, Register src1, Register src2, Register srcA,
816 SBit s = LeaveCC, Condition cond = al);
817
818 void mul(Register dst, Register src1, Register src2,
819 SBit s = LeaveCC, Condition cond = al);
820
821 void smlal(Register dstL, Register dstH, Register src1, Register src2,
822 SBit s = LeaveCC, Condition cond = al);
823
824 void smull(Register dstL, Register dstH, Register src1, Register src2,
825 SBit s = LeaveCC, Condition cond = al);
826
827 void umlal(Register dstL, Register dstH, Register src1, Register src2,
828 SBit s = LeaveCC, Condition cond = al);
829
830 void umull(Register dstL, Register dstH, Register src1, Register src2,
831 SBit s = LeaveCC, Condition cond = al);
832
833 // Miscellaneous arithmetic instructions
834
835 void clz(Register dst, Register src, Condition cond = al); // v5 and above
836
Ben Murdoch7f4d5bd2010-06-15 11:15:29 +0100837 // Bitfield manipulation instructions. v7 and above.
838
839 void ubfx(Register dst, Register src, int lsb, int width,
840 Condition cond = al);
841
842 void sbfx(Register dst, Register src, int lsb, int width,
843 Condition cond = al);
844
845 void bfc(Register dst, int lsb, int width, Condition cond = al);
846
847 void bfi(Register dst, Register src, int lsb, int width,
848 Condition cond = al);
849
Steve Blocka7e24c12009-10-30 11:49:00 +0000850 // Status register access instructions
851
852 void mrs(Register dst, SRegister s, Condition cond = al);
853 void msr(SRegisterFieldMask fields, const Operand& src, Condition cond = al);
854
855 // Load/Store instructions
856 void ldr(Register dst, const MemOperand& src, Condition cond = al);
857 void str(Register src, const MemOperand& dst, Condition cond = al);
858 void ldrb(Register dst, const MemOperand& src, Condition cond = al);
859 void strb(Register src, const MemOperand& dst, Condition cond = al);
860 void ldrh(Register dst, const MemOperand& src, Condition cond = al);
861 void strh(Register src, const MemOperand& dst, Condition cond = al);
862 void ldrsb(Register dst, const MemOperand& src, Condition cond = al);
863 void ldrsh(Register dst, const MemOperand& src, Condition cond = al);
Leon Clarkef7060e22010-06-03 12:02:55 +0100864 void ldrd(Register dst1,
865 Register dst2,
866 const MemOperand& src, Condition cond = al);
867 void strd(Register src1,
868 Register src2,
869 const MemOperand& dst, Condition cond = al);
Steve Blocka7e24c12009-10-30 11:49:00 +0000870
871 // Load/Store multiple instructions
872 void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al);
873 void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al);
874
Steve Blocka7e24c12009-10-30 11:49:00 +0000875 // Exception-generating instructions and debugging support
876 void stop(const char* msg);
877
878 void bkpt(uint32_t imm16); // v5 and above
879 void swi(uint32_t imm24, Condition cond = al);
880
881 // Coprocessor instructions
882
883 void cdp(Coprocessor coproc, int opcode_1,
884 CRegister crd, CRegister crn, CRegister crm,
885 int opcode_2, Condition cond = al);
886
887 void cdp2(Coprocessor coproc, int opcode_1,
888 CRegister crd, CRegister crn, CRegister crm,
889 int opcode_2); // v5 and above
890
891 void mcr(Coprocessor coproc, int opcode_1,
892 Register rd, CRegister crn, CRegister crm,
893 int opcode_2 = 0, Condition cond = al);
894
895 void mcr2(Coprocessor coproc, int opcode_1,
896 Register rd, CRegister crn, CRegister crm,
897 int opcode_2 = 0); // v5 and above
898
899 void mrc(Coprocessor coproc, int opcode_1,
900 Register rd, CRegister crn, CRegister crm,
901 int opcode_2 = 0, Condition cond = al);
902
903 void mrc2(Coprocessor coproc, int opcode_1,
904 Register rd, CRegister crn, CRegister crm,
905 int opcode_2 = 0); // v5 and above
906
907 void ldc(Coprocessor coproc, CRegister crd, const MemOperand& src,
908 LFlag l = Short, Condition cond = al);
909 void ldc(Coprocessor coproc, CRegister crd, Register base, int option,
910 LFlag l = Short, Condition cond = al);
911
912 void ldc2(Coprocessor coproc, CRegister crd, const MemOperand& src,
913 LFlag l = Short); // v5 and above
914 void ldc2(Coprocessor coproc, CRegister crd, Register base, int option,
915 LFlag l = Short); // v5 and above
916
917 void stc(Coprocessor coproc, CRegister crd, const MemOperand& dst,
918 LFlag l = Short, Condition cond = al);
919 void stc(Coprocessor coproc, CRegister crd, Register base, int option,
920 LFlag l = Short, Condition cond = al);
921
922 void stc2(Coprocessor coproc, CRegister crd, const MemOperand& dst,
923 LFlag l = Short); // v5 and above
924 void stc2(Coprocessor coproc, CRegister crd, Register base, int option,
925 LFlag l = Short); // v5 and above
926
Steve Blockd0582a62009-12-15 09:54:21 +0000927 // Support for VFP.
928 // All these APIs support S0 to S31 and D0 to D15.
929 // Currently these APIs do not support extended D registers, i.e, D16 to D31.
930 // However, some simple modifications can allow
931 // these APIs to support D16 to D31.
932
Leon Clarked91b9f72010-01-27 17:25:45 +0000933 void vldr(const DwVfpRegister dst,
934 const Register base,
935 int offset, // Offset must be a multiple of 4.
936 const Condition cond = al);
Steve Block6ded16b2010-05-10 14:33:55 +0100937
938 void vldr(const SwVfpRegister dst,
939 const Register base,
940 int offset, // Offset must be a multiple of 4.
941 const Condition cond = al);
942
Leon Clarked91b9f72010-01-27 17:25:45 +0000943 void vstr(const DwVfpRegister src,
944 const Register base,
945 int offset, // Offset must be a multiple of 4.
946 const Condition cond = al);
Steve Block8defd9f2010-07-08 12:39:36 +0100947
948 void vmov(const DwVfpRegister dst,
Ben Murdoch3bec4d22010-07-22 14:51:16 +0100949 double imm,
950 const Condition cond = al);
951 void vmov(const SwVfpRegister dst,
952 const SwVfpRegister src,
953 const Condition cond = al);
954 void vmov(const DwVfpRegister dst,
Steve Block8defd9f2010-07-08 12:39:36 +0100955 const DwVfpRegister src,
956 const Condition cond = al);
Leon Clarkee46be812010-01-19 14:06:41 +0000957 void vmov(const DwVfpRegister dst,
958 const Register src1,
Steve Blockd0582a62009-12-15 09:54:21 +0000959 const Register src2,
Leon Clarkee46be812010-01-19 14:06:41 +0000960 const Condition cond = al);
961 void vmov(const Register dst1,
962 const Register dst2,
963 const DwVfpRegister src,
964 const Condition cond = al);
965 void vmov(const SwVfpRegister dst,
966 const Register src,
967 const Condition cond = al);
968 void vmov(const Register dst,
969 const SwVfpRegister src,
970 const Condition cond = al);
Steve Block6ded16b2010-05-10 14:33:55 +0100971 void vcvt_f64_s32(const DwVfpRegister dst,
972 const SwVfpRegister src,
973 const Condition cond = al);
974 void vcvt_f32_s32(const SwVfpRegister dst,
975 const SwVfpRegister src,
976 const Condition cond = al);
977 void vcvt_f64_u32(const DwVfpRegister dst,
978 const SwVfpRegister src,
979 const Condition cond = al);
980 void vcvt_s32_f64(const SwVfpRegister dst,
981 const DwVfpRegister src,
982 const Condition cond = al);
983 void vcvt_u32_f64(const SwVfpRegister dst,
984 const DwVfpRegister src,
985 const Condition cond = al);
986 void vcvt_f64_f32(const DwVfpRegister dst,
987 const SwVfpRegister src,
988 const Condition cond = al);
989 void vcvt_f32_f64(const SwVfpRegister dst,
990 const DwVfpRegister src,
991 const Condition cond = al);
Leon Clarkee46be812010-01-19 14:06:41 +0000992
993 void vadd(const DwVfpRegister dst,
994 const DwVfpRegister src1,
995 const DwVfpRegister src2,
996 const Condition cond = al);
997 void vsub(const DwVfpRegister dst,
998 const DwVfpRegister src1,
999 const DwVfpRegister src2,
1000 const Condition cond = al);
1001 void vmul(const DwVfpRegister dst,
1002 const DwVfpRegister src1,
1003 const DwVfpRegister src2,
1004 const Condition cond = al);
1005 void vdiv(const DwVfpRegister dst,
1006 const DwVfpRegister src1,
1007 const DwVfpRegister src2,
1008 const Condition cond = al);
1009 void vcmp(const DwVfpRegister src1,
1010 const DwVfpRegister src2,
Steve Blockd0582a62009-12-15 09:54:21 +00001011 const SBit s = LeaveCC,
1012 const Condition cond = al);
1013 void vmrs(const Register dst,
1014 const Condition cond = al);
Steve Block8defd9f2010-07-08 12:39:36 +01001015 void vsqrt(const DwVfpRegister dst,
1016 const DwVfpRegister src,
1017 const Condition cond = al);
Steve Blockd0582a62009-12-15 09:54:21 +00001018
Steve Blocka7e24c12009-10-30 11:49:00 +00001019 // Pseudo instructions
Steve Block6ded16b2010-05-10 14:33:55 +01001020 void nop(int type = 0);
Steve Blocka7e24c12009-10-30 11:49:00 +00001021
1022 void push(Register src, Condition cond = al) {
1023 str(src, MemOperand(sp, 4, NegPreIndex), cond);
1024 }
1025
1026 void pop(Register dst, Condition cond = al) {
1027 ldr(dst, MemOperand(sp, 4, PostIndex), cond);
1028 }
1029
1030 void pop() {
1031 add(sp, sp, Operand(kPointerSize));
1032 }
1033
Steve Blocka7e24c12009-10-30 11:49:00 +00001034 // Jump unconditionally to given label.
1035 void jmp(Label* L) { b(L, al); }
1036
1037 // Check the code size generated from label to here.
1038 int InstructionsGeneratedSince(Label* l) {
1039 return (pc_offset() - l->pos()) / kInstrSize;
1040 }
1041
Steve Blockd0582a62009-12-15 09:54:21 +00001042 // Check whether an immediate fits an addressing mode 1 instruction.
1043 bool ImmediateFitsAddrMode1Instruction(int32_t imm32);
1044
Steve Block6ded16b2010-05-10 14:33:55 +01001045 // Class for scoping postponing the constant pool generation.
1046 class BlockConstPoolScope {
1047 public:
1048 explicit BlockConstPoolScope(Assembler* assem) : assem_(assem) {
1049 assem_->StartBlockConstPool();
1050 }
1051 ~BlockConstPoolScope() {
1052 assem_->EndBlockConstPool();
1053 }
1054
1055 private:
1056 Assembler* assem_;
1057
1058 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockConstPoolScope);
1059 };
1060
Steve Blockd0582a62009-12-15 09:54:21 +00001061 // Postpone the generation of the constant pool for the specified number of
1062 // instructions.
1063 void BlockConstPoolFor(int instructions);
1064
Steve Blocka7e24c12009-10-30 11:49:00 +00001065 // Debugging
1066
1067 // Mark address of the ExitJSFrame code.
1068 void RecordJSReturn();
1069
Ben Murdoch7f4d5bd2010-06-15 11:15:29 +01001070 // Mark address of a debug break slot.
1071 void RecordDebugBreakSlot();
1072
Steve Blocka7e24c12009-10-30 11:49:00 +00001073 // Record a comment relocation entry that can be used by a disassembler.
1074 // Use --debug_code to enable.
1075 void RecordComment(const char* msg);
1076
1077 void RecordPosition(int pos);
1078 void RecordStatementPosition(int pos);
Ben Murdoch7f4d5bd2010-06-15 11:15:29 +01001079 bool WriteRecordedPositions();
Steve Blocka7e24c12009-10-30 11:49:00 +00001080
1081 int pc_offset() const { return pc_ - buffer_; }
1082 int current_position() const { return current_position_; }
Steve Block6ded16b2010-05-10 14:33:55 +01001083 int current_statement_position() const { return current_statement_position_; }
1084
Leon Clarkef7060e22010-06-03 12:02:55 +01001085 bool can_peephole_optimize(int instructions) {
1086 if (!FLAG_peephole_optimization) return false;
1087 if (last_bound_pos_ > pc_offset() - instructions * kInstrSize) return false;
1088 return reloc_info_writer.last_pc() <= pc_ - instructions * kInstrSize;
1089 }
1090
Steve Block6ded16b2010-05-10 14:33:55 +01001091 // Read/patch instructions
1092 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
1093 static void instr_at_put(byte* pc, Instr instr) {
1094 *reinterpret_cast<Instr*>(pc) = instr;
1095 }
1096 static bool IsNop(Instr instr, int type = 0);
1097 static bool IsBranch(Instr instr);
1098 static int GetBranchOffset(Instr instr);
1099 static bool IsLdrRegisterImmediate(Instr instr);
1100 static int GetLdrRegisterImmediateOffset(Instr instr);
1101 static Instr SetLdrRegisterImmediateOffset(Instr instr, int offset);
Leon Clarkef7060e22010-06-03 12:02:55 +01001102 static Register GetRd(Instr instr);
1103 static bool IsPush(Instr instr);
1104 static bool IsPop(Instr instr);
1105 static bool IsStrRegFpOffset(Instr instr);
1106 static bool IsLdrRegFpOffset(Instr instr);
1107 static bool IsStrRegFpNegOffset(Instr instr);
1108 static bool IsLdrRegFpNegOffset(Instr instr);
Steve Block6ded16b2010-05-10 14:33:55 +01001109
Steve Blocka7e24c12009-10-30 11:49:00 +00001110
1111 protected:
1112 int buffer_space() const { return reloc_info_writer.pos() - pc_; }
1113
1114 // Read/patch instructions
Steve Blocka7e24c12009-10-30 11:49:00 +00001115 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
1116 void instr_at_put(int pos, Instr instr) {
1117 *reinterpret_cast<Instr*>(buffer_ + pos) = instr;
1118 }
1119
1120 // Decode branch instruction at pos and return branch target pos
1121 int target_at(int pos);
1122
1123 // Patch branch instruction at pos to branch to given branch target pos
1124 void target_at_put(int pos, int target_pos);
1125
1126 // Check if is time to emit a constant pool for pending reloc info entries
1127 void CheckConstPool(bool force_emit, bool require_jump);
1128
1129 // Block the emission of the constant pool before pc_offset
1130 void BlockConstPoolBefore(int pc_offset) {
1131 if (no_const_pool_before_ < pc_offset) no_const_pool_before_ = pc_offset;
1132 }
1133
Steve Block6ded16b2010-05-10 14:33:55 +01001134 void StartBlockConstPool() {
1135 const_pool_blocked_nesting_++;
1136 }
1137 void EndBlockConstPool() {
1138 const_pool_blocked_nesting_--;
1139 }
Steve Block8defd9f2010-07-08 12:39:36 +01001140 bool is_const_pool_blocked() const { return const_pool_blocked_nesting_ > 0; }
Steve Block6ded16b2010-05-10 14:33:55 +01001141
Steve Blocka7e24c12009-10-30 11:49:00 +00001142 private:
1143 // Code buffer:
1144 // The buffer into which code and relocation info are generated.
1145 byte* buffer_;
1146 int buffer_size_;
1147 // True if the assembler owns the buffer, false if buffer is external.
1148 bool own_buffer_;
1149
1150 // Buffer size and constant pool distance are checked together at regular
1151 // intervals of kBufferCheckInterval emitted bytes
1152 static const int kBufferCheckInterval = 1*KB/2;
1153 int next_buffer_check_; // pc offset of next buffer check
1154
1155 // Code generation
1156 // The relocation writer's position is at least kGap bytes below the end of
1157 // the generated instructions. This is so that multi-instruction sequences do
1158 // not have to check for overflow. The same is true for writes of large
1159 // relocation info entries.
1160 static const int kGap = 32;
1161 byte* pc_; // the program counter; moves forward
1162
1163 // Constant pool generation
1164 // Pools are emitted in the instruction stream, preferably after unconditional
1165 // jumps or after returns from functions (in dead code locations).
1166 // If a long code sequence does not contain unconditional jumps, it is
1167 // necessary to emit the constant pool before the pool gets too far from the
1168 // location it is accessed from. In this case, we emit a jump over the emitted
1169 // constant pool.
1170 // Constants in the pool may be addresses of functions that gets relocated;
1171 // if so, a relocation info entry is associated to the constant pool entry.
1172
1173 // Repeated checking whether the constant pool should be emitted is rather
1174 // expensive. By default we only check again once a number of instructions
1175 // has been generated. That also means that the sizing of the buffers is not
1176 // an exact science, and that we rely on some slop to not overrun buffers.
1177 static const int kCheckConstIntervalInst = 32;
1178 static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize;
1179
1180
1181 // Pools are emitted after function return and in dead code at (more or less)
1182 // regular intervals of kDistBetweenPools bytes
1183 static const int kDistBetweenPools = 1*KB;
1184
1185 // Constants in pools are accessed via pc relative addressing, which can
1186 // reach +/-4KB thereby defining a maximum distance between the instruction
1187 // and the accessed constant. We satisfy this constraint by limiting the
1188 // distance between pools.
1189 static const int kMaxDistBetweenPools = 4*KB - 2*kBufferCheckInterval;
1190
Steve Block6ded16b2010-05-10 14:33:55 +01001191 // Emission of the constant pool may be blocked in some code sequences.
1192 int const_pool_blocked_nesting_; // Block emission if this is not zero.
1193 int no_const_pool_before_; // Block emission before this pc offset.
Steve Blocka7e24c12009-10-30 11:49:00 +00001194
1195 // Keep track of the last emitted pool to guarantee a maximal distance
1196 int last_const_pool_end_; // pc offset following the last constant pool
1197
1198 // Relocation info generation
1199 // Each relocation is encoded as a variable size value
1200 static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
1201 RelocInfoWriter reloc_info_writer;
1202 // Relocation info records are also used during code generation as temporary
1203 // containers for constants and code target addresses until they are emitted
1204 // to the constant pool. These pending relocation info records are temporarily
1205 // stored in a separate buffer until a constant pool is emitted.
1206 // If every instruction in a long sequence is accessing the pool, we need one
1207 // pending relocation entry per instruction.
1208 static const int kMaxNumPRInfo = kMaxDistBetweenPools/kInstrSize;
1209 RelocInfo prinfo_[kMaxNumPRInfo]; // the buffer of pending relocation info
1210 int num_prinfo_; // number of pending reloc info entries in the buffer
1211
1212 // The bound position, before this we cannot do instruction elimination.
1213 int last_bound_pos_;
1214
1215 // source position information
1216 int current_position_;
1217 int current_statement_position_;
1218 int written_position_;
1219 int written_statement_position_;
1220
1221 // Code emission
1222 inline void CheckBuffer();
1223 void GrowBuffer();
1224 inline void emit(Instr x);
1225
1226 // Instruction generation
1227 void addrmod1(Instr instr, Register rn, Register rd, const Operand& x);
1228 void addrmod2(Instr instr, Register rd, const MemOperand& x);
1229 void addrmod3(Instr instr, Register rd, const MemOperand& x);
1230 void addrmod4(Instr instr, Register rn, RegList rl);
1231 void addrmod5(Instr instr, CRegister crd, const MemOperand& x);
1232
1233 // Labels
1234 void print(Label* L);
1235 void bind_to(Label* L, int pos);
1236 void link_to(Label* L, Label* appendix);
1237 void next(Label* L);
1238
1239 // Record reloc info for current pc_
1240 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1241
1242 friend class RegExpMacroAssemblerARM;
1243 friend class RelocInfo;
1244 friend class CodePatcher;
Steve Block6ded16b2010-05-10 14:33:55 +01001245 friend class BlockConstPoolScope;
Steve Blocka7e24c12009-10-30 11:49:00 +00001246};
1247
1248} } // namespace v8::internal
1249
1250#endif // V8_ARM_ASSEMBLER_ARM_H_