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gerrit-public.fairphone.software / fp2-dev / platform / external / v8 / c5610438f36f65235862a5f5020a739d29a5c32e / . / src / compiler / mips / instruction-codes-mips.h
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Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]1// Copyright 2014 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6#define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7
8namespace v8 {
9namespace internal {
10namespace compiler {
11
12// MIPS-specific opcodes that specify which assembly sequence to emit.
13// Most opcodes specify a single instruction.
14#define TARGET_ARCH_OPCODE_LIST(V) \
15 V(MipsAdd) \
16 V(MipsAddOvf) \
17 V(MipsSub) \
18 V(MipsSubOvf) \
19 V(MipsMul) \
20 V(MipsMulHigh) \
21 V(MipsMulHighU) \
22 V(MipsDiv) \
23 V(MipsDivU) \
24 V(MipsMod) \
25 V(MipsModU) \
26 V(MipsAnd) \
27 V(MipsOr) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]28 V(MipsNor) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]29 V(MipsXor) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]30 V(MipsClz) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame]31 V(MipsCtz) \
32 V(MipsPopcnt) \
Ben Murdochc5610432016-08-08 18:44:38 +0100[diff] [blame^]33 V(MipsLsa) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]34 V(MipsShl) \
35 V(MipsShr) \
36 V(MipsSar) \
Ben Murdochc5610432016-08-08 18:44:38 +0100[diff] [blame^]37 V(MipsShlPair) \
38 V(MipsShrPair) \
39 V(MipsSarPair) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]40 V(MipsExt) \
41 V(MipsIns) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]42 V(MipsRor) \
43 V(MipsMov) \
44 V(MipsTst) \
45 V(MipsCmp) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]46 V(MipsCmpS) \
47 V(MipsAddS) \
48 V(MipsSubS) \
49 V(MipsMulS) \
50 V(MipsDivS) \
51 V(MipsModS) \
52 V(MipsAbsS) \
53 V(MipsSqrtS) \
54 V(MipsMaxS) \
55 V(MipsMinS) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]56 V(MipsCmpD) \
57 V(MipsAddD) \
58 V(MipsSubD) \
59 V(MipsMulD) \
60 V(MipsDivD) \
61 V(MipsModD) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]62 V(MipsAbsD) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]63 V(MipsSqrtD) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]64 V(MipsMaxD) \
65 V(MipsMinD) \
Ben Murdochc5610432016-08-08 18:44:38 +0100[diff] [blame^]66 V(MipsAddPair) \
67 V(MipsSubPair) \
Ben Murdochda12d292016-06-02 14:46:10 +0100[diff] [blame]68 V(MipsMulPair) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]69 V(MipsFloat32RoundDown) \
70 V(MipsFloat32RoundTruncate) \
71 V(MipsFloat32RoundUp) \
72 V(MipsFloat32RoundTiesEven) \
73 V(MipsFloat64RoundDown) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]74 V(MipsFloat64RoundTruncate) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]75 V(MipsFloat64RoundUp) \
76 V(MipsFloat64RoundTiesEven) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]77 V(MipsCvtSD) \
78 V(MipsCvtDS) \
79 V(MipsTruncWD) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]80 V(MipsRoundWD) \
81 V(MipsFloorWD) \
82 V(MipsCeilWD) \
83 V(MipsTruncWS) \
84 V(MipsRoundWS) \
85 V(MipsFloorWS) \
86 V(MipsCeilWS) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]87 V(MipsTruncUwD) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame]88 V(MipsTruncUwS) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]89 V(MipsCvtDW) \
90 V(MipsCvtDUw) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]91 V(MipsCvtSW) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame]92 V(MipsCvtSUw) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]93 V(MipsLb) \
94 V(MipsLbu) \
95 V(MipsSb) \
96 V(MipsLh) \
97 V(MipsLhu) \
98 V(MipsSh) \
99 V(MipsLw) \
100 V(MipsSw) \
101 V(MipsLwc1) \
102 V(MipsSwc1) \
103 V(MipsLdc1) \
104 V(MipsSdc1) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]105 V(MipsFloat64ExtractLowWord32) \
106 V(MipsFloat64ExtractHighWord32) \
107 V(MipsFloat64InsertLowWord32) \
108 V(MipsFloat64InsertHighWord32) \
109 V(MipsFloat64Max) \
110 V(MipsFloat64Min) \
111 V(MipsFloat32Max) \
112 V(MipsFloat32Min) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]113 V(MipsPush) \
114 V(MipsStoreToStackSlot) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]115 V(MipsStackClaim)
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]116
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]117// Addressing modes represent the "shape" of inputs to an instruction.
118// Many instructions support multiple addressing modes. Addressing modes
119// are encoded into the InstructionCode of the instruction and tell the
120// code generator after register allocation which assembler method to call.
121//
122// We use the following local notation for addressing modes:
123//
124// R = register
125// O = register or stack slot
126// D = double register
127// I = immediate (handle, external, int32)
128// MRI = [register + immediate]
129// MRR = [register + register]
130// TODO(plind): Add the new r6 address modes.
131#define TARGET_ADDRESSING_MODE_LIST(V) \
132 V(MRI) /* [%r0 + K] */ \
133 V(MRR) /* [%r0 + %r1] */
134
135
136} // namespace compiler
137} // namespace internal
138} // namespace v8
139
140#endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_