sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1 | |
| 2 | /*--------------------------------------------------------------------*/ |
| 3 | /*--- The JITter: translate ucode back to x86 code. ---*/ |
| 4 | /*--- vg_from_ucode.c ---*/ |
| 5 | /*--------------------------------------------------------------------*/ |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 6 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 7 | /* |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 8 | This file is part of Valgrind, an extensible x86 protected-mode |
| 9 | emulator for monitoring program execution on x86-Unixes. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 10 | |
| 11 | Copyright (C) 2000-2002 Julian Seward |
| 12 | jseward@acm.org |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 13 | |
| 14 | This program is free software; you can redistribute it and/or |
| 15 | modify it under the terms of the GNU General Public License as |
| 16 | published by the Free Software Foundation; either version 2 of the |
| 17 | License, or (at your option) any later version. |
| 18 | |
| 19 | This program is distributed in the hope that it will be useful, but |
| 20 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 22 | General Public License for more details. |
| 23 | |
| 24 | You should have received a copy of the GNU General Public License |
| 25 | along with this program; if not, write to the Free Software |
| 26 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 27 | 02111-1307, USA. |
| 28 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 29 | The GNU General Public License is contained in the file COPYING. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 30 | */ |
| 31 | |
| 32 | #include "vg_include.h" |
| 33 | |
| 34 | |
| 35 | /*------------------------------------------------------------*/ |
| 36 | /*--- Renamings of frequently-used global functions. ---*/ |
| 37 | /*------------------------------------------------------------*/ |
| 38 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 39 | #define dis VG_(print_codegen) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 40 | |
| 41 | /*------------------------------------------------------------*/ |
| 42 | /*--- Instruction emission -- turning final uinstrs back ---*/ |
| 43 | /*--- into x86 code. ---*/ |
| 44 | /*------------------------------------------------------------*/ |
| 45 | |
| 46 | /* [2001-07-08 This comment is now somewhat out of date.] |
| 47 | |
| 48 | This is straightforward but for one thing: to facilitate generating |
| 49 | code in a single pass, we generate position-independent code. To |
| 50 | do this, calls and jmps to fixed addresses must specify the address |
| 51 | by first loading it into a register, and jump to/call that |
| 52 | register. Fortunately, the only jump to a literal is the jump back |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 53 | to vg_dispatch, and only %eax is live then, conveniently. UCode |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 54 | call insns may only have a register as target anyway, so there's no |
| 55 | need to do anything fancy for them. |
| 56 | |
| 57 | The emit_* routines constitute the lowest level of instruction |
| 58 | emission. They simply emit the sequence of bytes corresponding to |
| 59 | the relevant instruction, with no further ado. In particular there |
| 60 | is no checking about whether uses of byte registers makes sense, |
| 61 | nor whether shift insns have their first operand in %cl, etc. |
| 62 | |
| 63 | These issues are taken care of by the level above, the synth_* |
| 64 | routines. These detect impossible operand combinations and turn |
| 65 | them into sequences of legal instructions. Finally, emitUInstr is |
| 66 | phrased in terms of the synth_* abstraction layer. */ |
| 67 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 68 | /* Static state for the current basic block */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 69 | static UChar* emitted_code; |
| 70 | static Int emitted_code_used; |
| 71 | static Int emitted_code_size; |
| 72 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 73 | /* offset (in bytes into the basic block) */ |
| 74 | static UShort jumps[VG_MAX_JUMPS]; |
| 75 | static Int jumpidx; |
| 76 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 77 | static enum eflags_state { |
| 78 | UPD_Simd, /* baseblock copy is up to date */ |
| 79 | UPD_Real, /* CPU copy is up to date */ |
| 80 | UPD_Both, /* both are current */ |
| 81 | } eflags_state; |
| 82 | |
| 83 | /* single site for resetting state */ |
| 84 | static void reset_state(void) |
| 85 | { |
| 86 | emitted_code_used = 0; |
| 87 | emitted_code_size = 500; /* reasonable initial size */ |
| 88 | emitted_code = VG_(arena_malloc)(VG_AR_JITTER, emitted_code_size); |
| 89 | jumpidx = 0; |
| 90 | eflags_state = UPD_Simd; |
| 91 | } |
| 92 | |
| 93 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 94 | /* Statistics about C functions called from generated code. */ |
| 95 | static UInt ccalls = 0; |
| 96 | static UInt ccall_reg_saves = 0; |
| 97 | static UInt ccall_args = 0; |
| 98 | static UInt ccall_arg_setup_instrs = 0; |
| 99 | static UInt ccall_stack_clears = 0; |
| 100 | static UInt ccall_retvals = 0; |
| 101 | static UInt ccall_retval_movs = 0; |
| 102 | |
| 103 | /* Statistics about frequency of each UInstr */ |
| 104 | typedef |
| 105 | struct { |
| 106 | UInt counts; |
| 107 | UInt size; |
| 108 | } Histogram; |
| 109 | |
| 110 | /* Automatically zeroed because it's static. */ |
| 111 | static Histogram histogram[100]; |
| 112 | |
| 113 | void VG_(print_ccall_stats)(void) |
| 114 | { |
| 115 | VG_(message)(Vg_DebugMsg, |
| 116 | " ccalls: %u C calls, %u%% saves+restores avoided" |
| 117 | " (%d bytes)", |
| 118 | ccalls, |
| 119 | 100-(UInt)(ccall_reg_saves/(double)(ccalls*3)*100), |
| 120 | ((ccalls*3) - ccall_reg_saves)*2); |
| 121 | VG_(message)(Vg_DebugMsg, |
| 122 | " %u args, avg 0.%d setup instrs each (%d bytes)", |
| 123 | ccall_args, |
| 124 | (UInt)(ccall_arg_setup_instrs/(double)ccall_args*100), |
| 125 | (ccall_args - ccall_arg_setup_instrs)*2); |
| 126 | VG_(message)(Vg_DebugMsg, |
| 127 | " %d%% clear the stack (%d bytes)", |
| 128 | (UInt)(ccall_stack_clears/(double)ccalls*100), |
| 129 | (ccalls - ccall_stack_clears)*3); |
| 130 | VG_(message)(Vg_DebugMsg, |
| 131 | " %u retvals, %u%% of reg-reg movs avoided (%d bytes)", |
| 132 | ccall_retvals, |
| 133 | ( ccall_retvals == 0 |
| 134 | ? 100 |
| 135 | : 100-(UInt)(ccall_retval_movs / |
| 136 | (double)ccall_retvals*100)), |
| 137 | (ccall_retvals-ccall_retval_movs)*2); |
| 138 | } |
| 139 | |
| 140 | void VG_(print_UInstr_histogram)(void) |
| 141 | { |
| 142 | Int i, j; |
| 143 | UInt total_counts = 0; |
| 144 | UInt total_size = 0; |
sewardj | 6c3769f | 2002-11-29 01:02:45 +0000 | [diff] [blame] | 145 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 146 | for (i = 0; i < 100; i++) { |
| 147 | total_counts += histogram[i].counts; |
| 148 | total_size += histogram[i].size; |
| 149 | } |
| 150 | |
| 151 | VG_(printf)("-- UInstr frequencies -----------\n"); |
| 152 | for (i = 0; i < 100; i++) { |
| 153 | if (0 != histogram[i].counts) { |
| 154 | |
| 155 | UInt count_pc = |
| 156 | (UInt)(histogram[i].counts/(double)total_counts*100 + 0.5); |
| 157 | UInt size_pc = |
| 158 | (UInt)(histogram[i].size /(double)total_size *100 + 0.5); |
| 159 | UInt avg_size = |
| 160 | (UInt)(histogram[i].size / (double)histogram[i].counts + 0.5); |
| 161 | |
| 162 | VG_(printf)("%-7s:%8u (%2u%%), avg %2dB (%2u%%) |", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 163 | VG_(name_UOpcode)(True, i), |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 164 | histogram[i].counts, count_pc, |
| 165 | avg_size, size_pc); |
| 166 | |
| 167 | for (j = 0; j < size_pc; j++) VG_(printf)("O"); |
| 168 | VG_(printf)("\n"); |
| 169 | |
| 170 | } else { |
| 171 | vg_assert(0 == histogram[i].size); |
| 172 | } |
| 173 | } |
| 174 | |
| 175 | VG_(printf)("total UInstrs %u, total size %u\n", total_counts, total_size); |
| 176 | } |
| 177 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 178 | static void expandEmittedCode ( void ) |
| 179 | { |
| 180 | Int i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 181 | UChar *tmp = VG_(arena_malloc)(VG_AR_JITTER, 2 * emitted_code_size); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 182 | /* VG_(printf)("expand to %d\n", 2 * emitted_code_size); */ |
| 183 | for (i = 0; i < emitted_code_size; i++) |
| 184 | tmp[i] = emitted_code[i]; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 185 | VG_(arena_free)(VG_AR_JITTER, emitted_code); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 186 | emitted_code = tmp; |
| 187 | emitted_code_size *= 2; |
| 188 | } |
| 189 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 190 | /* Local calls will be inlined, cross-module ones not */ |
| 191 | __inline__ void VG_(emitB) ( UInt b ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 192 | { |
| 193 | if (dis) { |
| 194 | if (b < 16) VG_(printf)("0%x ", b); else VG_(printf)("%2x ", b); |
| 195 | } |
| 196 | if (emitted_code_used == emitted_code_size) |
| 197 | expandEmittedCode(); |
| 198 | |
| 199 | emitted_code[emitted_code_used] = (UChar)b; |
| 200 | emitted_code_used++; |
| 201 | } |
| 202 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 203 | __inline__ void VG_(emitW) ( UInt l ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 204 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 205 | VG_(emitB) ( (l) & 0x000000FF ); |
| 206 | VG_(emitB) ( (l >> 8) & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 207 | } |
| 208 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 209 | __inline__ void VG_(emitL) ( UInt l ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 210 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 211 | VG_(emitB) ( (l) & 0x000000FF ); |
| 212 | VG_(emitB) ( (l >> 8) & 0x000000FF ); |
| 213 | VG_(emitB) ( (l >> 16) & 0x000000FF ); |
| 214 | VG_(emitB) ( (l >> 24) & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 215 | } |
| 216 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 217 | static void emit_get_eflags ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 218 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 219 | Int off = 4 * VGOFF_(m_eflags); |
| 220 | vg_assert(off >= 0 && off < 128); |
| 221 | |
| 222 | if (dis) |
| 223 | VG_(printf)("\t %4d: ", emitted_code_used ); |
| 224 | |
| 225 | VG_(emitB) ( 0xFF ); /* PUSHL off(%ebp) */ |
| 226 | VG_(emitB) ( 0x75 ); |
| 227 | VG_(emitB) ( off ); |
| 228 | VG_(emitB) ( 0x9D ); /* POPFL */ |
| 229 | if (dis) |
| 230 | VG_(printf)( "\n\t\tpushl %d(%%ebp) ; popfl\n", off ); |
| 231 | } |
| 232 | |
| 233 | static void emit_put_eflags ( void ) |
| 234 | { |
| 235 | Int off = 4 * VGOFF_(m_eflags); |
| 236 | vg_assert(off >= 0 && off < 128); |
| 237 | |
| 238 | if (dis) |
| 239 | VG_(printf)("\t %4d: ", emitted_code_used ); |
| 240 | |
| 241 | VG_(emitB) ( 0x9C ); /* PUSHFL */ |
| 242 | VG_(emitB) ( 0x8F ); /* POPL vg_m_state.m_eflags */ |
| 243 | VG_(emitB) ( 0x45 ); |
| 244 | VG_(emitB) ( off ); |
| 245 | if (dis) |
| 246 | VG_(printf)( "\n\t\tpushfl ; popl %d(%%ebp)\n", off ); |
| 247 | } |
| 248 | |
| 249 | static void maybe_emit_put_eflags( void ) |
| 250 | { |
| 251 | if (eflags_state == UPD_Real) { |
| 252 | eflags_state = UPD_Both; |
| 253 | emit_put_eflags(); |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | static void maybe_emit_get_eflags( void ) |
| 258 | { |
| 259 | if (eflags_state == UPD_Simd) { |
| 260 | eflags_state = UPD_Both; |
| 261 | emit_get_eflags(); |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | /* Call this before emitting each instruction. |
| 266 | |
| 267 | Arguments are: |
| 268 | upds_simd_flags: |
| 269 | if true, this instruction updates the simulated %EFLAGS state, |
| 270 | otherwise it doesn't |
| 271 | use_flags: set of (real) flags the instruction uses |
| 272 | set_flags: set of (real) flags the instruction sets |
| 273 | */ |
| 274 | __inline__ |
| 275 | void VG_(new_emit) ( Bool upds_simd_flags, |
| 276 | FlagSet use_flags, FlagSet set_flags ) |
| 277 | { |
| 278 | Bool use, set; |
| 279 | |
| 280 | use = use_flags != FlagsEmpty |
| 281 | || (set_flags != FlagsEmpty && set_flags != FlagsOSZACP); |
| 282 | set = set_flags != FlagsEmpty; |
| 283 | |
| 284 | if (0) |
| 285 | VG_(printf)( |
| 286 | "new_emit: state=%d upds_simd_flags=%d use_flags=%x set_flags=%x\n", |
| 287 | eflags_state, upds_simd_flags, use_flags, set_flags); |
| 288 | |
| 289 | if (upds_simd_flags) { |
| 290 | if (use && eflags_state == UPD_Simd) { |
| 291 | /* we need the CPU flags set, but they're not already */ |
| 292 | eflags_state = UPD_Both; |
| 293 | emit_get_eflags(); |
| 294 | } |
| 295 | if (set) { |
| 296 | /* if we're setting the flags, then the CPU will have the |
| 297 | only good copy */ |
| 298 | eflags_state = UPD_Real; |
| 299 | } |
| 300 | } else { |
| 301 | /* presume that if non-simd code is using flags, it knows what |
| 302 | it's doing (ie, it just set up the flags). */ |
| 303 | if (set) { |
| 304 | /* This instruction is going to trash the flags, so we'd |
| 305 | better save them away and say that they're only in the |
| 306 | simulated state. */ |
| 307 | maybe_emit_put_eflags(); |
| 308 | eflags_state = UPD_Simd; |
| 309 | } |
| 310 | } |
| 311 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 312 | if (dis) |
| 313 | VG_(printf)("\t %4d: ", emitted_code_used ); |
| 314 | } |
| 315 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 316 | |
| 317 | /*----------------------------------------------------*/ |
| 318 | /*--- Addressing modes ---*/ |
| 319 | /*----------------------------------------------------*/ |
| 320 | |
| 321 | static __inline__ UChar mkModRegRM ( UChar mod, UChar reg, UChar regmem ) |
| 322 | { |
| 323 | return ((mod & 3) << 6) | ((reg & 7) << 3) | (regmem & 7); |
| 324 | } |
| 325 | |
| 326 | static __inline__ UChar mkSIB ( Int scale, Int regindex, Int regbase ) |
| 327 | { |
| 328 | Int shift; |
| 329 | switch (scale) { |
| 330 | case 1: shift = 0; break; |
| 331 | case 2: shift = 1; break; |
| 332 | case 4: shift = 2; break; |
| 333 | case 8: shift = 3; break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 334 | default: VG_(core_panic)( "mkSIB" ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 335 | } |
| 336 | return ((shift & 3) << 6) | ((regindex & 7) << 3) | (regbase & 7); |
| 337 | } |
| 338 | |
| 339 | static __inline__ void emit_amode_litmem_reg ( Addr addr, Int reg ) |
| 340 | { |
| 341 | /* ($ADDR), reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 342 | VG_(emitB) ( mkModRegRM(0, reg, 5) ); |
| 343 | VG_(emitL) ( addr ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | static __inline__ void emit_amode_regmem_reg ( Int regmem, Int reg ) |
| 347 | { |
| 348 | /* (regmem), reg */ |
| 349 | if (regmem == R_ESP) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 350 | VG_(core_panic)("emit_amode_regmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 351 | if (regmem == R_EBP) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 352 | VG_(emitB) ( mkModRegRM(1, reg, 5) ); |
| 353 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 354 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 355 | VG_(emitB)( mkModRegRM(0, reg, regmem) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 356 | } |
| 357 | } |
| 358 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 359 | void VG_(emit_amode_offregmem_reg) ( Int off, Int regmem, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 360 | { |
| 361 | if (regmem == R_ESP) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 362 | VG_(core_panic)("emit_amode_offregmem_reg(ESP)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 363 | if (off < -128 || off > 127) { |
| 364 | /* Use a large offset */ |
| 365 | /* d32(regmem), reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 366 | VG_(emitB) ( mkModRegRM(2, reg, regmem) ); |
| 367 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 368 | } else { |
| 369 | /* d8(regmem), reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 370 | VG_(emitB) ( mkModRegRM(1, reg, regmem) ); |
| 371 | VG_(emitB) ( off & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 372 | } |
| 373 | } |
| 374 | |
| 375 | static __inline__ void emit_amode_sib_reg ( Int off, Int scale, Int regbase, |
| 376 | Int regindex, Int reg ) |
| 377 | { |
| 378 | if (regindex == R_ESP) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 379 | VG_(core_panic)("emit_amode_sib_reg(ESP)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 380 | if (off < -128 || off > 127) { |
| 381 | /* Use a 32-bit offset */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 382 | VG_(emitB) ( mkModRegRM(2, reg, 4) ); /* SIB with 32-bit displacement */ |
| 383 | VG_(emitB) ( mkSIB( scale, regindex, regbase ) ); |
| 384 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 385 | } else { |
| 386 | /* Use an 8-bit offset */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 387 | VG_(emitB) ( mkModRegRM(1, reg, 4) ); /* SIB with 8-bit displacement */ |
| 388 | VG_(emitB) ( mkSIB( scale, regindex, regbase ) ); |
| 389 | VG_(emitB) ( off & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 390 | } |
| 391 | } |
| 392 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 393 | void VG_(emit_amode_ereg_greg) ( Int e_reg, Int g_reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 394 | { |
| 395 | /* other_reg, reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 396 | VG_(emitB) ( mkModRegRM(3, g_reg, e_reg) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 397 | } |
| 398 | |
| 399 | static __inline__ void emit_amode_greg_ereg ( Int g_reg, Int e_reg ) |
| 400 | { |
| 401 | /* other_reg, reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 402 | VG_(emitB) ( mkModRegRM(3, g_reg, e_reg) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 403 | } |
| 404 | |
| 405 | |
| 406 | /*----------------------------------------------------*/ |
| 407 | /*--- Opcode translation ---*/ |
| 408 | /*----------------------------------------------------*/ |
| 409 | |
| 410 | static __inline__ Int mkGrp1opcode ( Opcode opc ) |
| 411 | { |
| 412 | switch (opc) { |
| 413 | case ADD: return 0; |
| 414 | case OR: return 1; |
| 415 | case ADC: return 2; |
| 416 | case SBB: return 3; |
| 417 | case AND: return 4; |
| 418 | case SUB: return 5; |
| 419 | case XOR: return 6; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 420 | default: VG_(core_panic)("mkGrp1opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 421 | } |
| 422 | } |
| 423 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 424 | static __inline__ FlagSet nonshiftop_use(Opcode opc) |
| 425 | { |
| 426 | switch(opc) { |
| 427 | case ADC: |
| 428 | case SBB: |
| 429 | return FlagC; |
| 430 | |
| 431 | case ADD: |
| 432 | case OR: |
| 433 | case AND: |
| 434 | case SUB: |
| 435 | case XOR: |
| 436 | return FlagsEmpty; |
| 437 | |
| 438 | default: |
| 439 | VG_(core_panic)("nonshiftop_use"); |
| 440 | } |
| 441 | } |
| 442 | |
| 443 | static __inline__ FlagSet nonshiftop_set(Opcode opc) |
| 444 | { |
| 445 | switch(opc) { |
| 446 | case ADC: |
| 447 | case SBB: |
| 448 | case ADD: |
| 449 | case OR: |
| 450 | case AND: |
| 451 | case SUB: |
| 452 | case XOR: |
| 453 | return FlagsOSZACP; |
| 454 | |
| 455 | default: |
| 456 | VG_(core_panic)("nonshiftop_set"); |
| 457 | } |
| 458 | } |
| 459 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 460 | static __inline__ Int mkGrp2opcode ( Opcode opc ) |
| 461 | { |
| 462 | switch (opc) { |
| 463 | case ROL: return 0; |
| 464 | case ROR: return 1; |
| 465 | case RCL: return 2; |
| 466 | case RCR: return 3; |
| 467 | case SHL: return 4; |
| 468 | case SHR: return 5; |
| 469 | case SAR: return 7; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 470 | default: VG_(core_panic)("mkGrp2opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 471 | } |
| 472 | } |
| 473 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 474 | static __inline__ FlagSet shiftop_use(Opcode opc) |
| 475 | { |
| 476 | switch(opc) { |
| 477 | case ROR: |
| 478 | case ROL: |
| 479 | case SHL: |
| 480 | case SHR: |
| 481 | case SAR: |
| 482 | return FlagsEmpty; |
| 483 | |
| 484 | case RCL: |
| 485 | case RCR: |
| 486 | return FlagC; |
| 487 | |
| 488 | default: |
| 489 | VG_(core_panic)("shiftop_use"); |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | static __inline__ FlagSet shiftop_set(Opcode opc) |
| 494 | { |
| 495 | switch(opc) { |
| 496 | case ROR: |
| 497 | case ROL: |
| 498 | case RCL: |
| 499 | case RCR: |
| 500 | return FlagsOC; |
| 501 | |
| 502 | case SHL: |
| 503 | case SHR: |
| 504 | case SAR: |
| 505 | return FlagsOSZACP; |
| 506 | |
| 507 | default: |
| 508 | VG_(core_panic)("shiftop_set"); |
| 509 | } |
| 510 | } |
| 511 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 512 | static __inline__ Int mkGrp3opcode ( Opcode opc ) |
| 513 | { |
| 514 | switch (opc) { |
| 515 | case NOT: return 2; |
| 516 | case NEG: return 3; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 517 | default: VG_(core_panic)("mkGrp3opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 518 | } |
| 519 | } |
| 520 | |
| 521 | static __inline__ Int mkGrp4opcode ( Opcode opc ) |
| 522 | { |
| 523 | switch (opc) { |
| 524 | case INC: return 0; |
| 525 | case DEC: return 1; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 526 | default: VG_(core_panic)("mkGrp4opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 527 | } |
| 528 | } |
| 529 | |
| 530 | static __inline__ Int mkGrp5opcode ( Opcode opc ) |
| 531 | { |
| 532 | switch (opc) { |
| 533 | case CALLM: return 2; |
| 534 | case JMP: return 4; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 535 | default: VG_(core_panic)("mkGrp5opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 536 | } |
| 537 | } |
| 538 | |
| 539 | static __inline__ UChar mkPrimaryOpcode ( Opcode opc ) |
| 540 | { |
| 541 | switch (opc) { |
| 542 | case ADD: return 0x00; |
| 543 | case ADC: return 0x10; |
| 544 | case AND: return 0x20; |
| 545 | case XOR: return 0x30; |
| 546 | case OR: return 0x08; |
| 547 | case SBB: return 0x18; |
| 548 | case SUB: return 0x28; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 549 | default: VG_(core_panic)("mkPrimaryOpcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 550 | } |
| 551 | } |
| 552 | |
| 553 | /*----------------------------------------------------*/ |
| 554 | /*--- v-size (4, or 2 with OSO) insn emitters ---*/ |
| 555 | /*----------------------------------------------------*/ |
| 556 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 557 | void VG_(emit_movv_offregmem_reg) ( Int sz, Int off, Int areg, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 558 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 559 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 560 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 561 | VG_(emitB) ( 0x8B ); /* MOV Ev, Gv */ |
| 562 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 563 | if (dis) |
| 564 | VG_(printf)( "\n\t\tmov%c\t0x%x(%s), %s\n", |
| 565 | nameISize(sz), off, nameIReg(4,areg), nameIReg(sz,reg)); |
| 566 | } |
| 567 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 568 | void VG_(emit_movv_reg_offregmem) ( Int sz, Int reg, Int off, Int areg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 569 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 570 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 571 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 572 | VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */ |
| 573 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 574 | if (dis) |
| 575 | VG_(printf)( "\n\t\tmov%c\t%s, 0x%x(%s)\n", |
| 576 | nameISize(sz), nameIReg(sz,reg), off, nameIReg(4,areg)); |
| 577 | } |
| 578 | |
| 579 | static void emit_movv_regmem_reg ( Int sz, Int reg1, Int reg2 ) |
| 580 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 581 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 582 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 583 | VG_(emitB) ( 0x8B ); /* MOV Ev, Gv */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 584 | emit_amode_regmem_reg ( reg1, reg2 ); |
| 585 | if (dis) |
| 586 | VG_(printf)( "\n\t\tmov%c\t(%s), %s\n", |
| 587 | nameISize(sz), nameIReg(4,reg1), nameIReg(sz,reg2)); |
| 588 | } |
| 589 | |
| 590 | static void emit_movv_reg_regmem ( Int sz, Int reg1, Int reg2 ) |
| 591 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 592 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 593 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 594 | VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 595 | emit_amode_regmem_reg ( reg2, reg1 ); |
| 596 | if (dis) |
| 597 | VG_(printf)( "\n\t\tmov%c\t%s, (%s)\n", |
| 598 | nameISize(sz), nameIReg(sz,reg1), nameIReg(4,reg2)); |
| 599 | } |
| 600 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 601 | void VG_(emit_movv_reg_reg) ( Int sz, Int reg1, Int reg2 ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 602 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 603 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 604 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 605 | VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */ |
| 606 | VG_(emit_amode_ereg_greg) ( reg2, reg1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 607 | if (dis) |
| 608 | VG_(printf)( "\n\t\tmov%c\t%s, %s\n", |
| 609 | nameISize(sz), nameIReg(sz,reg1), nameIReg(sz,reg2)); |
| 610 | } |
| 611 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 612 | void VG_(emit_nonshiftopv_lit_reg) ( Bool upd_cc, Int sz, Opcode opc, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 613 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 614 | VG_(new_emit)(upd_cc, nonshiftop_use(opc), nonshiftop_set(opc)); |
| 615 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 616 | if (sz == 2) VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 617 | if (lit == VG_(extend_s_8to32)(lit & 0x000000FF)) { |
| 618 | /* short form OK */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 619 | VG_(emitB) ( 0x83 ); /* Grp1 Ib,Ev */ |
| 620 | VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) ); |
| 621 | VG_(emitB) ( lit & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 622 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 623 | VG_(emitB) ( 0x81 ); /* Grp1 Iv,Ev */ |
| 624 | VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) ); |
| 625 | if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 626 | } |
| 627 | if (dis) |
| 628 | VG_(printf)( "\n\t\t%s%c\t$0x%x, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 629 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 630 | lit, nameIReg(sz,reg)); |
| 631 | } |
| 632 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 633 | void VG_(emit_nonshiftopv_lit_offregmem) ( Bool upd_cc, Int sz, Opcode opc, UInt lit, |
| 634 | Int off, Int regmem ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 635 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 636 | VG_(new_emit)(upd_cc, nonshiftop_use(opc), nonshiftop_set(opc)); |
| 637 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 638 | if (lit == VG_(extend_s_8to32)(lit & 0x000000FF)) { |
| 639 | /* short form OK */ |
| 640 | VG_(emitB) ( 0x83 ); /* Grp1 Ib,Ev */ |
| 641 | VG_(emit_amode_offregmem_reg) ( off, regmem, mkGrp1opcode(opc) ); |
| 642 | VG_(emitB) ( lit & 0x000000FF ); |
| 643 | } else { |
| 644 | VG_(emitB) ( 0x81 ); /* Grp1 Iv,Ev */ |
| 645 | VG_(emit_amode_offregmem_reg) ( off, regmem, mkGrp1opcode(opc) ); |
| 646 | if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit ); |
| 647 | } |
| 648 | if (dis) |
| 649 | VG_(printf)( "\n\t\t%s%c\t$0x%x, 0x%x(%s)\n", |
| 650 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
| 651 | lit, off, nameIReg(sz,regmem)); |
| 652 | } |
| 653 | |
| 654 | void VG_(emit_shiftopv_lit_reg) ( Bool upd_cc, Int sz, Opcode opc, UInt lit, Int reg ) |
| 655 | { |
| 656 | VG_(new_emit)(upd_cc, shiftop_use(opc), shiftop_set(opc)); |
| 657 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 658 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 659 | VG_(emitB) ( 0xC1 ); /* Grp2 Ib,Ev */ |
| 660 | VG_(emit_amode_ereg_greg) ( reg, mkGrp2opcode(opc) ); |
| 661 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 662 | if (dis) |
| 663 | VG_(printf)( "\n\t\t%s%c\t$%d, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 664 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 665 | lit, nameIReg(sz,reg)); |
| 666 | } |
| 667 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 668 | static void emit_shiftopv_cl_stack0 ( Bool upd_cc, Int sz, Opcode opc ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 669 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 670 | VG_(new_emit)(upd_cc, shiftop_use(opc), shiftop_set(opc)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 671 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 672 | VG_(emitB) ( 0xD3 ); /* Grp2 CL,Ev */ |
| 673 | VG_(emitB) ( mkModRegRM ( 1, mkGrp2opcode(opc), 4 ) ); |
| 674 | VG_(emitB) ( 0x24 ); /* a SIB, I think `d8(%esp)' */ |
| 675 | VG_(emitB) ( 0x00 ); /* the d8 displacement */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 676 | if (dis) |
| 677 | VG_(printf)("\n\t\t%s%c %%cl, 0(%%esp)\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 678 | VG_(name_UOpcode)(False,opc), nameISize(sz) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 679 | } |
| 680 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 681 | static void emit_shiftopb_cl_stack0 ( Bool upd_cc, Opcode opc ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 682 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 683 | VG_(new_emit)(upd_cc, shiftop_use(opc), shiftop_set(opc)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 684 | VG_(emitB) ( 0xD2 ); /* Grp2 CL,Eb */ |
| 685 | VG_(emitB) ( mkModRegRM ( 1, mkGrp2opcode(opc), 4 ) ); |
| 686 | VG_(emitB) ( 0x24 ); /* a SIB, I think `d8(%esp)' */ |
| 687 | VG_(emitB) ( 0x00 ); /* the d8 displacement */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 688 | if (dis) |
| 689 | VG_(printf)("\n\t\t%s%c %%cl, 0(%%esp)\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 690 | VG_(name_UOpcode)(False,opc), nameISize(1) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 691 | } |
| 692 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 693 | static void emit_nonshiftopv_offregmem_reg ( Bool upd_cc, Int sz, Opcode opc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 694 | Int off, Int areg, Int reg ) |
| 695 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 696 | VG_(new_emit)(upd_cc, nonshiftop_use(opc), nonshiftop_set(opc)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 697 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 698 | VG_(emitB) ( 3 + mkPrimaryOpcode(opc) ); /* op Ev, Gv */ |
| 699 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 700 | if (dis) |
| 701 | VG_(printf)( "\n\t\t%s%c\t0x%x(%s), %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 702 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 703 | off, nameIReg(4,areg), nameIReg(sz,reg)); |
| 704 | } |
| 705 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 706 | static void emit_nonshiftopv_reg_offregmem ( Bool upd_cc, Int sz, Opcode opc, |
| 707 | Int off, Int areg, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 708 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 709 | VG_(new_emit)(upd_cc, nonshiftop_use(opc), nonshiftop_set(opc)); |
| 710 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 711 | VG_(emitB) ( 1 + mkPrimaryOpcode(opc) ); /* op Gv, Ev */ |
| 712 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
| 713 | if (dis) |
| 714 | VG_(printf)( "\n\t\t%s%c\t0x%s, %x(%s),\n", |
| 715 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
| 716 | nameIReg(sz,reg), off, nameIReg(4,areg)); |
| 717 | } |
| 718 | |
| 719 | void VG_(emit_nonshiftopv_reg_reg) ( Bool upd_cc, Int sz, Opcode opc, |
| 720 | Int reg1, Int reg2 ) |
| 721 | { |
| 722 | VG_(new_emit)(upd_cc, nonshiftop_use(opc), nonshiftop_set(opc)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 723 | if (sz == 2) VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 724 | # if 0 |
| 725 | /* Perfectly correct, but the GNU assembler uses the other form. |
| 726 | Therefore we too use the other form, to aid verification. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 727 | VG_(emitB) ( 3 + mkPrimaryOpcode(opc) ); /* op Ev, Gv */ |
| 728 | VG_(emit_amode_ereg_greg) ( reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 729 | # else |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 730 | VG_(emitB) ( 1 + mkPrimaryOpcode(opc) ); /* op Gv, Ev */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 731 | emit_amode_greg_ereg ( reg1, reg2 ); |
| 732 | # endif |
| 733 | if (dis) |
| 734 | VG_(printf)( "\n\t\t%s%c\t%s, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 735 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 736 | nameIReg(sz,reg1), nameIReg(sz,reg2)); |
| 737 | } |
| 738 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 739 | void VG_(emit_movv_lit_reg) ( Int sz, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 740 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 741 | if (lit == 0 && eflags_state != UPD_Real) { |
| 742 | /* Only emit this for zeroing if it won't stomp flags */ |
| 743 | VG_(emit_nonshiftopv_reg_reg) ( False, sz, XOR, reg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 744 | return; |
| 745 | } |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 746 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 747 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 748 | VG_(emitB) ( 0xB8+reg ); /* MOV imm, Gv */ |
| 749 | if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 750 | if (dis) |
| 751 | VG_(printf)( "\n\t\tmov%c\t$0x%x, %s\n", |
| 752 | nameISize(sz), lit, nameIReg(sz,reg)); |
| 753 | } |
| 754 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 755 | void VG_(emit_unaryopv_reg) ( Bool upd_cc, Int sz, Opcode opc, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 756 | { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 757 | switch (opc) { |
| 758 | case NEG: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 759 | VG_(new_emit)(upd_cc, FlagsEmpty, FlagsOSZACP); |
| 760 | if (sz == 2) VG_(emitB) ( 0x66 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 761 | VG_(emitB) ( 0xF7 ); |
| 762 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NEG) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 763 | if (dis) |
| 764 | VG_(printf)( "\n\t\tneg%c\t%s\n", |
| 765 | nameISize(sz), nameIReg(sz,reg)); |
| 766 | break; |
| 767 | case NOT: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 768 | VG_(new_emit)(upd_cc, FlagsEmpty, FlagsEmpty); |
| 769 | if (sz == 2) VG_(emitB) ( 0x66 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 770 | VG_(emitB) ( 0xF7 ); |
| 771 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NOT) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 772 | if (dis) |
| 773 | VG_(printf)( "\n\t\tnot%c\t%s\n", |
| 774 | nameISize(sz), nameIReg(sz,reg)); |
| 775 | break; |
| 776 | case DEC: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 777 | VG_(new_emit)(upd_cc, FlagsEmpty, FlagsOSZAP); |
| 778 | if (sz == 2) VG_(emitB) ( 0x66 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 779 | VG_(emitB) ( 0x48 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 780 | if (dis) |
| 781 | VG_(printf)( "\n\t\tdec%c\t%s\n", |
| 782 | nameISize(sz), nameIReg(sz,reg)); |
| 783 | break; |
| 784 | case INC: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 785 | VG_(new_emit)(upd_cc, FlagsEmpty, FlagsOSZAP); |
| 786 | if (sz == 2) VG_(emitB) ( 0x66 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 787 | VG_(emitB) ( 0x40 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 788 | if (dis) |
| 789 | VG_(printf)( "\n\t\tinc%c\t%s\n", |
| 790 | nameISize(sz), nameIReg(sz,reg)); |
| 791 | break; |
| 792 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 793 | VG_(core_panic)("VG_(emit_unaryopv_reg)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 794 | } |
| 795 | } |
| 796 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 797 | void VG_(emit_pushv_reg) ( Int sz, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 798 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 799 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 800 | if (sz == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 801 | VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 802 | } else { |
| 803 | vg_assert(sz == 4); |
| 804 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 805 | VG_(emitB) ( 0x50 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 806 | if (dis) |
| 807 | VG_(printf)("\n\t\tpush%c %s\n", nameISize(sz), nameIReg(sz,reg)); |
| 808 | } |
| 809 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 810 | void VG_(emit_popv_reg) ( Int sz, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 811 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 812 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 813 | if (sz == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 814 | VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 815 | } else { |
| 816 | vg_assert(sz == 4); |
| 817 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 818 | VG_(emitB) ( 0x58 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 819 | if (dis) |
| 820 | VG_(printf)("\n\t\tpop%c %s\n", nameISize(sz), nameIReg(sz,reg)); |
| 821 | } |
| 822 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 823 | void VG_(emit_pushl_lit32) ( UInt int32 ) |
| 824 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 825 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 826 | VG_(emitB) ( 0x68 ); |
| 827 | VG_(emitL) ( int32 ); |
| 828 | if (dis) |
| 829 | VG_(printf)("\n\t\tpushl $0x%x\n", int32 ); |
| 830 | } |
| 831 | |
| 832 | void VG_(emit_pushl_lit8) ( Int lit8 ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 833 | { |
| 834 | vg_assert(lit8 >= -128 && lit8 < 128); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 835 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 836 | VG_(emitB) ( 0x6A ); |
| 837 | VG_(emitB) ( (UChar)((UInt)lit8) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 838 | if (dis) |
| 839 | VG_(printf)("\n\t\tpushl $%d\n", lit8 ); |
| 840 | } |
| 841 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 842 | void VG_(emit_cmpl_zero_reg) ( Bool upd_cc, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 843 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 844 | VG_(new_emit)(upd_cc, False, FlagsOSZACP); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 845 | VG_(emitB) ( 0x83 ); |
| 846 | VG_(emit_amode_ereg_greg) ( reg, 7 /* Grp 3 opcode for CMP */ ); |
| 847 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 848 | if (dis) |
| 849 | VG_(printf)("\n\t\tcmpl $0, %s\n", nameIReg(4,reg)); |
| 850 | } |
| 851 | |
| 852 | static void emit_swapl_reg_ECX ( Int reg ) |
| 853 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 854 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 855 | VG_(emitB) ( 0x87 ); /* XCHG Gv,Ev */ |
| 856 | VG_(emit_amode_ereg_greg) ( reg, R_ECX ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 857 | if (dis) |
| 858 | VG_(printf)("\n\t\txchgl %%ecx, %s\n", nameIReg(4,reg)); |
| 859 | } |
| 860 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 861 | void VG_(emit_swapl_reg_EAX) ( Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 862 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 863 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 864 | VG_(emitB) ( 0x90 + reg ); /* XCHG Gv,eAX */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 865 | if (dis) |
| 866 | VG_(printf)("\n\t\txchgl %%eax, %s\n", nameIReg(4,reg)); |
| 867 | } |
| 868 | |
| 869 | static void emit_swapl_reg_reg ( Int reg1, Int reg2 ) |
| 870 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 871 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 872 | VG_(emitB) ( 0x87 ); /* XCHG Gv,Ev */ |
| 873 | VG_(emit_amode_ereg_greg) ( reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 874 | if (dis) |
| 875 | VG_(printf)("\n\t\txchgl %s, %s\n", nameIReg(4,reg1), |
| 876 | nameIReg(4,reg2)); |
| 877 | } |
| 878 | |
| 879 | static void emit_bswapl_reg ( Int reg ) |
| 880 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 881 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 882 | VG_(emitB) ( 0x0F ); |
| 883 | VG_(emitB) ( 0xC8 + reg ); /* BSWAP r32 */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 884 | if (dis) |
| 885 | VG_(printf)("\n\t\tbswapl %s\n", nameIReg(4,reg)); |
| 886 | } |
| 887 | |
| 888 | static void emit_movl_reg_reg ( Int regs, Int regd ) |
| 889 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 890 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 891 | VG_(emitB) ( 0x89 ); /* MOV Gv,Ev */ |
| 892 | VG_(emit_amode_ereg_greg) ( regd, regs ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 893 | if (dis) |
| 894 | VG_(printf)("\n\t\tmovl %s, %s\n", nameIReg(4,regs), nameIReg(4,regd)); |
| 895 | } |
| 896 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 897 | void VG_(emit_movv_lit_offregmem) ( Int sz, UInt lit, Int off, Int memreg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 898 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 899 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 900 | if (sz == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 901 | VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 902 | } else { |
| 903 | vg_assert(sz == 4); |
| 904 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 905 | VG_(emitB) ( 0xC7 ); /* Grp11 Ev */ |
| 906 | VG_(emit_amode_offregmem_reg) ( off, memreg, 0 /* Grp11 subopcode for MOV */ ); |
| 907 | if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 908 | if (dis) |
| 909 | VG_(printf)( "\n\t\tmov%c\t$0x%x, 0x%x(%s)\n", |
| 910 | nameISize(sz), lit, off, nameIReg(4,memreg) ); |
| 911 | } |
| 912 | |
| 913 | |
| 914 | /*----------------------------------------------------*/ |
| 915 | /*--- b-size (1 byte) instruction emitters ---*/ |
| 916 | /*----------------------------------------------------*/ |
| 917 | |
| 918 | /* There is some doubt as to whether C6 (Grp 11) is in the |
| 919 | 486 insn set. ToDo: investigate. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 920 | void VG_(emit_movb_lit_offregmem) ( UInt lit, Int off, Int memreg ) |
| 921 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 922 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 923 | VG_(emitB) ( 0xC6 ); /* Grp11 Eb */ |
| 924 | VG_(emit_amode_offregmem_reg) ( off, memreg, 0 /* Grp11 subopcode for MOV */ ); |
| 925 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 926 | if (dis) |
| 927 | VG_(printf)( "\n\t\tmovb\t$0x%x, 0x%x(%s)\n", |
| 928 | lit, off, nameIReg(4,memreg) ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 929 | } |
| 930 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 931 | static void emit_nonshiftopb_offregmem_reg ( Bool upd_cc, Opcode opc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 932 | Int off, Int areg, Int reg ) |
| 933 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 934 | VG_(new_emit)(upd_cc, (opc == ADC || opc == SBB) ? FlagC : FlagsEmpty, True); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 935 | VG_(emitB) ( 2 + mkPrimaryOpcode(opc) ); /* op Eb, Gb */ |
| 936 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 937 | if (dis) |
| 938 | VG_(printf)( "\n\t\t%sb\t0x%x(%s), %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 939 | VG_(name_UOpcode)(False,opc), off, nameIReg(4,areg), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 940 | nameIReg(1,reg)); |
| 941 | } |
| 942 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 943 | static void emit_nonshiftopb_lit_offregmem ( Bool upd_cc, Opcode opc, |
| 944 | UInt lit, Int off, Int areg ) |
| 945 | { |
| 946 | VG_(new_emit)(upd_cc, nonshiftop_use(opc), nonshiftop_set(opc)); |
| 947 | VG_(emitB) ( 0x80 ); |
| 948 | VG_(emit_amode_offregmem_reg) ( off, areg, mkGrp1opcode(opc) ); |
| 949 | VG_(emitB) ( lit ); |
| 950 | if (dis) |
| 951 | VG_(printf)( "\n\t\t%sb\t$0x%x, 0x%x(%s)\n", |
| 952 | VG_(name_UOpcode)(False,opc), lit, off, nameIReg(4,areg)); |
| 953 | } |
| 954 | |
| 955 | static void emit_nonshiftopb_reg_offregmem ( Bool upd_cc, Opcode opc, |
| 956 | Int off, Int areg, Int reg ) |
| 957 | { |
| 958 | VG_(new_emit)(upd_cc, nonshiftop_use(opc), nonshiftop_set(opc)); |
| 959 | VG_(emitB) ( 0 + mkPrimaryOpcode(opc) ); /* op Gb, Eb */ |
| 960 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
| 961 | if (dis) |
| 962 | VG_(printf)( "\n\t\t%sb\t0x%s , %x(%s)\n", |
| 963 | VG_(name_UOpcode)(False,opc), |
| 964 | nameIReg(1,reg), |
| 965 | off, nameIReg(4,areg)); |
| 966 | } |
| 967 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 968 | void VG_(emit_movb_reg_offregmem) ( Int reg, Int off, Int areg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 969 | { |
| 970 | /* Could do better when reg == %al. */ |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 971 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 972 | VG_(emitB) ( 0x88 ); /* MOV G1, E1 */ |
| 973 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 974 | if (dis) |
| 975 | VG_(printf)( "\n\t\tmovb\t%s, 0x%x(%s)\n", |
| 976 | nameIReg(1,reg), off, nameIReg(4,areg)); |
| 977 | } |
| 978 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 979 | static void emit_nonshiftopb_reg_reg ( Bool upd_cc, Opcode opc, Int reg1, Int reg2 ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 980 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 981 | VG_(new_emit)(upd_cc, nonshiftop_use(opc), nonshiftop_set(opc)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 982 | VG_(emitB) ( 2 + mkPrimaryOpcode(opc) ); /* op Eb, Gb */ |
| 983 | VG_(emit_amode_ereg_greg) ( reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 984 | if (dis) |
| 985 | VG_(printf)( "\n\t\t%sb\t%s, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 986 | VG_(name_UOpcode)(False,opc), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 987 | nameIReg(1,reg1), nameIReg(1,reg2)); |
| 988 | } |
| 989 | |
| 990 | static void emit_movb_reg_regmem ( Int reg1, Int reg2 ) |
| 991 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 992 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 993 | VG_(emitB) ( 0x88 ); /* MOV G1, E1 */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 994 | emit_amode_regmem_reg ( reg2, reg1 ); |
| 995 | if (dis) |
| 996 | VG_(printf)( "\n\t\tmovb\t%s, (%s)\n", nameIReg(1,reg1), |
| 997 | nameIReg(4,reg2)); |
| 998 | } |
| 999 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1000 | static void emit_nonshiftopb_lit_reg ( Bool upd_cc, Opcode opc, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1001 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1002 | VG_(new_emit)(upd_cc, nonshiftop_use(opc), nonshiftop_set(opc)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1003 | VG_(emitB) ( 0x80 ); /* Grp1 Ib,Eb */ |
| 1004 | VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) ); |
| 1005 | VG_(emitB) ( lit & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1006 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1007 | VG_(printf)( "\n\t\t%sb\t$0x%x, %s\n", VG_(name_UOpcode)(False,opc), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1008 | lit, nameIReg(1,reg)); |
| 1009 | } |
| 1010 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1011 | static void emit_shiftopb_lit_reg ( Bool upd_cc, Opcode opc, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1012 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1013 | VG_(new_emit)(upd_cc, shiftop_use(opc), shiftop_set(opc)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1014 | VG_(emitB) ( 0xC0 ); /* Grp2 Ib,Eb */ |
| 1015 | VG_(emit_amode_ereg_greg) ( reg, mkGrp2opcode(opc) ); |
| 1016 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1017 | if (dis) |
| 1018 | VG_(printf)( "\n\t\t%sb\t$%d, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1019 | VG_(name_UOpcode)(False,opc), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1020 | lit, nameIReg(1,reg)); |
| 1021 | } |
| 1022 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1023 | void VG_(emit_unaryopb_reg) ( Bool upd_cc, Opcode opc, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1024 | { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1025 | switch (opc) { |
| 1026 | case INC: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1027 | VG_(new_emit)(upd_cc, FlagsEmpty, FlagsOSZAP); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1028 | VG_(emitB) ( 0xFE ); |
| 1029 | VG_(emit_amode_ereg_greg) ( reg, mkGrp4opcode(INC) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1030 | if (dis) |
| 1031 | VG_(printf)( "\n\t\tincb\t%s\n", nameIReg(1,reg)); |
| 1032 | break; |
| 1033 | case DEC: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1034 | VG_(new_emit)(upd_cc, FlagsEmpty, FlagsOSZAP); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1035 | VG_(emitB) ( 0xFE ); |
| 1036 | VG_(emit_amode_ereg_greg) ( reg, mkGrp4opcode(DEC) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1037 | if (dis) |
| 1038 | VG_(printf)( "\n\t\tdecb\t%s\n", nameIReg(1,reg)); |
| 1039 | break; |
| 1040 | case NOT: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1041 | VG_(new_emit)(upd_cc, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1042 | VG_(emitB) ( 0xF6 ); |
| 1043 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NOT) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1044 | if (dis) |
| 1045 | VG_(printf)( "\n\t\tnotb\t%s\n", nameIReg(1,reg)); |
| 1046 | break; |
| 1047 | case NEG: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1048 | VG_(new_emit)(upd_cc, FlagsEmpty, FlagsOSZACP); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1049 | VG_(emitB) ( 0xF6 ); |
| 1050 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NEG) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1051 | if (dis) |
| 1052 | VG_(printf)( "\n\t\tnegb\t%s\n", nameIReg(1,reg)); |
| 1053 | break; |
| 1054 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1055 | VG_(core_panic)("VG_(emit_unaryopb_reg)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1056 | } |
| 1057 | } |
| 1058 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1059 | void VG_(emit_testb_lit_reg) ( Bool upd_cc, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1060 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1061 | VG_(new_emit)(upd_cc, FlagsEmpty, FlagsOSZACP); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1062 | VG_(emitB) ( 0xF6 ); /* Grp3 Eb */ |
| 1063 | VG_(emit_amode_ereg_greg) ( reg, 0 /* Grp3 subopcode for TEST */ ); |
| 1064 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1065 | if (dis) |
| 1066 | VG_(printf)("\n\t\ttestb $0x%x, %s\n", lit, nameIReg(1,reg)); |
| 1067 | } |
| 1068 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1069 | /*----------------------------------------------------*/ |
| 1070 | /*--- zero-extended load emitters ---*/ |
| 1071 | /*----------------------------------------------------*/ |
| 1072 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1073 | void VG_(emit_movzbl_offregmem_reg) ( Int off, Int regmem, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1074 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1075 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1076 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB6 ); /* MOVZBL */ |
| 1077 | VG_(emit_amode_offregmem_reg) ( off, regmem, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1078 | if (dis) |
| 1079 | VG_(printf)( "\n\t\tmovzbl\t0x%x(%s), %s\n", |
| 1080 | off, nameIReg(4,regmem), nameIReg(4,reg)); |
| 1081 | } |
| 1082 | |
| 1083 | static void emit_movzbl_regmem_reg ( Int reg1, Int reg2 ) |
| 1084 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1085 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1086 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB6 ); /* MOVZBL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1087 | emit_amode_regmem_reg ( reg1, reg2 ); |
| 1088 | if (dis) |
| 1089 | VG_(printf)( "\n\t\tmovzbl\t(%s), %s\n", nameIReg(4,reg1), |
| 1090 | nameIReg(4,reg2)); |
| 1091 | } |
| 1092 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1093 | void VG_(emit_movzwl_offregmem_reg) ( Int off, Int areg, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1094 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1095 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1096 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB7 ); /* MOVZWL */ |
| 1097 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1098 | if (dis) |
| 1099 | VG_(printf)( "\n\t\tmovzwl\t0x%x(%s), %s\n", |
| 1100 | off, nameIReg(4,areg), nameIReg(4,reg)); |
| 1101 | } |
| 1102 | |
| 1103 | static void emit_movzwl_regmem_reg ( Int reg1, Int reg2 ) |
| 1104 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1105 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1106 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB7 ); /* MOVZWL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1107 | emit_amode_regmem_reg ( reg1, reg2 ); |
| 1108 | if (dis) |
| 1109 | VG_(printf)( "\n\t\tmovzwl\t(%s), %s\n", nameIReg(4,reg1), |
| 1110 | nameIReg(4,reg2)); |
| 1111 | } |
| 1112 | |
| 1113 | /*----------------------------------------------------*/ |
| 1114 | /*--- FPU instruction emitters ---*/ |
| 1115 | /*----------------------------------------------------*/ |
| 1116 | |
| 1117 | static void emit_get_fpu_state ( void ) |
| 1118 | { |
| 1119 | Int off = 4 * VGOFF_(m_fpustate); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1120 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1121 | VG_(emitB) ( 0xDD ); VG_(emitB) ( 0xA5 ); /* frstor d32(%ebp) */ |
| 1122 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1123 | if (dis) |
| 1124 | VG_(printf)("\n\t\tfrstor\t%d(%%ebp)\n", off ); |
| 1125 | } |
| 1126 | |
| 1127 | static void emit_put_fpu_state ( void ) |
| 1128 | { |
| 1129 | Int off = 4 * VGOFF_(m_fpustate); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1130 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1131 | VG_(emitB) ( 0xDD ); VG_(emitB) ( 0xB5 ); /* fnsave d32(%ebp) */ |
| 1132 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1133 | if (dis) |
| 1134 | VG_(printf)("\n\t\tfnsave\t%d(%%ebp)\n", off ); |
| 1135 | } |
| 1136 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1137 | static void emit_fpu_no_mem ( FlagSet uses_flags, FlagSet sets_flags, |
| 1138 | UChar first_byte, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1139 | UChar second_byte ) |
| 1140 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1141 | VG_(new_emit)(True, uses_flags, sets_flags); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1142 | VG_(emitB) ( first_byte ); |
| 1143 | VG_(emitB) ( second_byte ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1144 | if (dis) |
| 1145 | VG_(printf)("\n\t\tfpu-0x%x:0x%x\n", |
| 1146 | (UInt)first_byte, (UInt)second_byte ); |
| 1147 | } |
| 1148 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1149 | static void emit_fpu_regmem ( FlagSet uses_flags, FlagSet sets_flags, |
| 1150 | UChar first_byte, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1151 | UChar second_byte_masked, |
| 1152 | Int reg ) |
| 1153 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1154 | VG_(new_emit)(True, uses_flags, sets_flags); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1155 | VG_(emitB) ( first_byte ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1156 | emit_amode_regmem_reg ( reg, second_byte_masked >> 3 ); |
| 1157 | if (dis) |
| 1158 | VG_(printf)("\n\t\tfpu-0x%x:0x%x-(%s)\n", |
| 1159 | (UInt)first_byte, (UInt)second_byte_masked, |
| 1160 | nameIReg(4,reg) ); |
| 1161 | } |
| 1162 | |
| 1163 | |
| 1164 | /*----------------------------------------------------*/ |
| 1165 | /*--- misc instruction emitters ---*/ |
| 1166 | /*----------------------------------------------------*/ |
| 1167 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1168 | void VG_(emit_call_reg) ( Int reg ) |
| 1169 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1170 | VG_(new_emit)(False, FlagsEmpty, FlagsOSZACP); /* XXX */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1171 | VG_(emitB) ( 0xFF ); /* Grp5 */ |
| 1172 | VG_(emit_amode_ereg_greg) ( reg, mkGrp5opcode(CALLM) ); |
| 1173 | if (dis) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1174 | VG_(printf)( "\n\t\tcall\t*%s\n", nameIReg(4,reg) ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1175 | } |
| 1176 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1177 | static void emit_call_star_EBP_off ( Bool upd_cc, Int byte_off, FlagSet use_flag, FlagSet set_flag ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1178 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1179 | /* Used for helpers which expect to see Simd flags in Real flags */ |
| 1180 | VG_(new_emit)(upd_cc, use_flag, set_flag); |
| 1181 | |
| 1182 | if (byte_off < -128 || byte_off > 127) { |
| 1183 | VG_(emitB) ( 0xFF ); |
| 1184 | VG_(emitB) ( 0x95 ); |
| 1185 | VG_(emitL) ( byte_off ); |
| 1186 | } else { |
| 1187 | VG_(emitB) ( 0xFF ); |
| 1188 | VG_(emitB) ( 0x55 ); |
| 1189 | VG_(emitB) ( byte_off ); |
| 1190 | } |
| 1191 | if (dis) |
| 1192 | VG_(printf)( "\n\t\tcall * %d(%%ebp)\n", byte_off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1193 | } |
| 1194 | |
| 1195 | |
| 1196 | static void emit_addlit8_offregmem ( Int lit8, Int regmem, Int off ) |
| 1197 | { |
| 1198 | vg_assert(lit8 >= -128 && lit8 < 128); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1199 | VG_(new_emit)(True, FlagsEmpty, FlagsOSZACP); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1200 | VG_(emitB) ( 0x83 ); /* Grp1 Ib,Ev */ |
| 1201 | VG_(emit_amode_offregmem_reg) ( off, regmem, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1202 | 0 /* Grp1 subopcode for ADD */ ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1203 | VG_(emitB) ( lit8 & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1204 | if (dis) |
| 1205 | VG_(printf)( "\n\t\taddl $%d, %d(%s)\n", lit8, off, |
| 1206 | nameIReg(4,regmem)); |
| 1207 | } |
| 1208 | |
| 1209 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1210 | void VG_(emit_add_lit_to_esp) ( Int lit ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1211 | { |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1212 | if (lit < -128 || lit > 127) VG_(core_panic)("VG_(emit_add_lit_to_esp)"); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1213 | VG_(new_emit)(False, FlagsEmpty, FlagsEmpty); |
| 1214 | VG_(emitB) ( 0x8D ); |
| 1215 | VG_(emitB) ( 0x64 ); |
| 1216 | VG_(emitB) ( 0x24 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1217 | VG_(emitB) ( lit & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1218 | if (dis) |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1219 | VG_(printf)( "\n\t\tlea\t%d(%%esp), %%esp\n", lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1220 | } |
| 1221 | |
| 1222 | |
| 1223 | static void emit_movb_AL_zeroESPmem ( void ) |
| 1224 | { |
| 1225 | /* movb %al, 0(%esp) */ |
| 1226 | /* 88442400 movb %al, 0(%esp) */ |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1227 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1228 | VG_(emitB) ( 0x88 ); |
| 1229 | VG_(emitB) ( 0x44 ); |
| 1230 | VG_(emitB) ( 0x24 ); |
| 1231 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1232 | if (dis) |
| 1233 | VG_(printf)( "\n\t\tmovb %%al, 0(%%esp)\n" ); |
| 1234 | } |
| 1235 | |
| 1236 | static void emit_movb_zeroESPmem_AL ( void ) |
| 1237 | { |
| 1238 | /* movb 0(%esp), %al */ |
| 1239 | /* 8A442400 movb 0(%esp), %al */ |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1240 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1241 | VG_(emitB) ( 0x8A ); |
| 1242 | VG_(emitB) ( 0x44 ); |
| 1243 | VG_(emitB) ( 0x24 ); |
| 1244 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1245 | if (dis) |
| 1246 | VG_(printf)( "\n\t\tmovb 0(%%esp), %%al\n" ); |
| 1247 | } |
| 1248 | |
| 1249 | |
| 1250 | /* Emit a jump short with an 8-bit signed offset. Note that the |
| 1251 | offset is that which should be added to %eip once %eip has been |
| 1252 | advanced over this insn. */ |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1253 | void VG_(emit_jcondshort_delta) ( Bool simd, Condcode cond, Int delta ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1254 | { |
| 1255 | vg_assert(delta >= -128 && delta <= 127); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1256 | VG_(new_emit)(simd, FlagsOSZCP, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1257 | VG_(emitB) ( 0x70 + (UInt)cond ); |
| 1258 | VG_(emitB) ( (UChar)delta ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1259 | if (dis) |
| 1260 | VG_(printf)( "\n\t\tj%s-8\t%%eip+%d\n", |
| 1261 | VG_(nameCondcode)(cond), delta ); |
| 1262 | } |
| 1263 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1264 | static void emit_setb_reg ( Int reg, Condcode cond ) |
| 1265 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1266 | VG_(new_emit)(True, FlagsOSZCP, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1267 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0x90 + (UChar)cond ); |
| 1268 | VG_(emit_amode_ereg_greg) ( reg, 0 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1269 | if (dis) |
| 1270 | VG_(printf)("\n\t\tset%s %s\n", |
| 1271 | VG_(nameCondcode)(cond), nameIReg(1,reg)); |
| 1272 | } |
| 1273 | |
| 1274 | static void emit_ret ( void ) |
| 1275 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1276 | maybe_emit_put_eflags(); /* make sure flags are stored */ |
| 1277 | VG_(new_emit)(False, False, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1278 | VG_(emitB) ( 0xC3 ); /* RET */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1279 | if (dis) |
| 1280 | VG_(printf)("\n\t\tret\n"); |
| 1281 | } |
| 1282 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1283 | /* Predicate used in sanity checks elsewhere - returns true if any |
| 1284 | jump-site is an actual chained jump */ |
| 1285 | Bool VG_(is_chained_jumpsite)(Addr a) |
| 1286 | { |
| 1287 | UChar *cp = (UChar *)a; |
| 1288 | |
| 1289 | return (*cp == 0xE9); /* 0xE9 -- jmp */ |
| 1290 | } |
| 1291 | |
sewardj | 83f1186 | 2002-12-01 02:07:08 +0000 | [diff] [blame] | 1292 | static |
| 1293 | Bool is_fresh_jumpsite(UChar *cp) |
| 1294 | { |
| 1295 | return |
| 1296 | cp[0] == 0x0F && /* UD2 */ |
| 1297 | cp[1] == 0x0B && |
| 1298 | cp[2] == 0x0F && /* UD2 */ |
| 1299 | cp[3] == 0x0B && |
| 1300 | cp[4] == 0x90; /* NOP */ |
| 1301 | } |
| 1302 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1303 | /* Predicate used in sanity checks elsewhere - returns true if all |
| 1304 | jump-sites are calls to VG_(patch_me) */ |
| 1305 | Bool VG_(is_unchained_jumpsite)(Addr a) |
| 1306 | { |
| 1307 | UChar *cp = (UChar *)a; |
| 1308 | Int delta = ((Addr)&VG_(patch_me)) - (a + VG_PATCHME_CALLSZ); |
| 1309 | Int idelta; |
| 1310 | |
| 1311 | if (*cp++ != 0xE8) /* 0xE8 == call */ |
| 1312 | return False; |
| 1313 | |
| 1314 | idelta = (*cp++) << 0; |
| 1315 | idelta |= (*cp++) << 8; |
| 1316 | idelta |= (*cp++) << 16; |
| 1317 | idelta |= (*cp++) << 24; |
| 1318 | |
| 1319 | return idelta == delta; |
| 1320 | } |
| 1321 | |
| 1322 | /* Return target address for a direct jmp */ |
| 1323 | Addr VG_(get_jmp_dest)(Addr a) |
| 1324 | { |
| 1325 | Int delta; |
| 1326 | UChar *cp = (UChar *)a; |
| 1327 | |
| 1328 | if (*cp++ != 0xE9) /* 0xE9 == jmp */ |
| 1329 | return 0; |
| 1330 | |
| 1331 | delta = (*cp++) << 0; |
| 1332 | delta |= (*cp++) << 8; |
| 1333 | delta |= (*cp++) << 16; |
| 1334 | delta |= (*cp++) << 24; |
| 1335 | |
| 1336 | return a + VG_PATCHME_JMPSZ + delta; |
| 1337 | } |
| 1338 | |
| 1339 | /* unchain a BB by generating a call to VG_(patch_me) */ |
| 1340 | void VG_(unchain_jumpsite)(Addr a) |
| 1341 | { |
| 1342 | Int delta = ((Addr)&VG_(patch_me)) - (a + VG_PATCHME_CALLSZ); |
| 1343 | UChar *cp = (UChar *)a; |
| 1344 | |
| 1345 | if (VG_(is_unchained_jumpsite)(a)) |
| 1346 | return; /* don't write unnecessarily */ |
| 1347 | |
sewardj | 83f1186 | 2002-12-01 02:07:08 +0000 | [diff] [blame] | 1348 | if (!is_fresh_jumpsite(cp)) |
| 1349 | VG_(bb_dechain_count)++; /* update stats */ |
| 1350 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1351 | *cp++ = 0xE8; /* call */ |
| 1352 | *cp++ = (delta >> 0) & 0xff; |
| 1353 | *cp++ = (delta >> 8) & 0xff; |
| 1354 | *cp++ = (delta >> 16) & 0xff; |
| 1355 | *cp++ = (delta >> 24) & 0xff; |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1356 | } |
| 1357 | |
| 1358 | /* This doesn't actually generate a call to VG_(patch_me), but |
| 1359 | reserves enough space in the instruction stream for it to happen |
| 1360 | and records the offset into the jump table. This is because call |
| 1361 | is a relative jump, and so will be affected when this code gets |
| 1362 | moved about. The translation table will "unchain" this basic block |
| 1363 | on insertion (with VG_(unchain_BB)()), and thereby generate a |
| 1364 | proper call instruction. */ |
| 1365 | static void emit_call_patchme( void ) |
| 1366 | { |
| 1367 | vg_assert(VG_PATCHME_CALLSZ == 5); |
| 1368 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1369 | maybe_emit_put_eflags(); /* save flags before end of BB */ |
| 1370 | VG_(new_emit)(False, False, False); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1371 | |
| 1372 | if (jumpidx >= VG_MAX_JUMPS) { |
| 1373 | /* If there too many jumps in this basic block, fall back to |
| 1374 | dispatch loop. We still need to keep it the same size as the |
| 1375 | call sequence. */ |
| 1376 | VG_(emitB) ( 0xC3 ); /* ret */ |
| 1377 | VG_(emitB) ( 0x90 ); /* nop */ |
| 1378 | VG_(emitB) ( 0x90 ); /* nop */ |
| 1379 | VG_(emitB) ( 0x90 ); /* nop */ |
| 1380 | VG_(emitB) ( 0x90 ); /* nop */ |
| 1381 | |
| 1382 | if (dis) |
| 1383 | VG_(printf)("\n\t\tret; nop; nop; nop; nop\n"); |
| 1384 | |
| 1385 | if (0 && VG_(clo_verbosity)) |
| 1386 | VG_(message)(Vg_DebugMsg, "too many chained jumps in basic-block"); |
| 1387 | } else { |
| 1388 | jumps[jumpidx++] = emitted_code_used; |
| 1389 | |
| 1390 | VG_(emitB) ( 0x0F ); /* UD2 - undefined instruction */ |
| 1391 | VG_(emitB) ( 0x0B ); |
| 1392 | VG_(emitB) ( 0x0F ); /* UD2 - undefined instruction */ |
| 1393 | VG_(emitB) ( 0x0B ); |
| 1394 | VG_(emitB) ( 0x90 ); /* NOP */ |
| 1395 | |
| 1396 | if (dis) |
| 1397 | VG_(printf)("\n\t\tud2; ud2; nop\n"); |
| 1398 | } |
| 1399 | } |
| 1400 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1401 | void VG_(emit_pushal) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1402 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1403 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1404 | VG_(emitB) ( 0x60 ); /* PUSHAL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1405 | if (dis) |
| 1406 | VG_(printf)("\n\t\tpushal\n"); |
| 1407 | } |
| 1408 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1409 | void VG_(emit_popal) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1410 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1411 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1412 | VG_(emitB) ( 0x61 ); /* POPAL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1413 | if (dis) |
| 1414 | VG_(printf)("\n\t\tpopal\n"); |
| 1415 | } |
| 1416 | |
| 1417 | static void emit_lea_litreg_reg ( UInt lit, Int regmem, Int reg ) |
| 1418 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1419 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1420 | VG_(emitB) ( 0x8D ); /* LEA M,Gv */ |
| 1421 | VG_(emit_amode_offregmem_reg) ( (Int)lit, regmem, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1422 | if (dis) |
| 1423 | VG_(printf)("\n\t\tleal 0x%x(%s), %s\n", |
| 1424 | lit, nameIReg(4,regmem), nameIReg(4,reg) ); |
| 1425 | } |
| 1426 | |
| 1427 | static void emit_lea_sib_reg ( UInt lit, Int scale, |
| 1428 | Int regbase, Int regindex, Int reg ) |
| 1429 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1430 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1431 | VG_(emitB) ( 0x8D ); /* LEA M,Gv */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1432 | emit_amode_sib_reg ( (Int)lit, scale, regbase, regindex, reg ); |
| 1433 | if (dis) |
| 1434 | VG_(printf)("\n\t\tleal 0x%x(%s,%s,%d), %s\n", |
| 1435 | lit, nameIReg(4,regbase), |
| 1436 | nameIReg(4,regindex), scale, |
| 1437 | nameIReg(4,reg) ); |
| 1438 | } |
| 1439 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1440 | void VG_(emit_AMD_prefetch_reg) ( Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1441 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1442 | VG_(new_emit)(True, FlagsEmpty, FlagsEmpty); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1443 | VG_(emitB) ( 0x0F ); |
| 1444 | VG_(emitB) ( 0x0D ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1445 | emit_amode_regmem_reg ( reg, 1 /* 0 is prefetch; 1 is prefetchw */ ); |
| 1446 | if (dis) |
| 1447 | VG_(printf)("\n\t\tamd-prefetch (%s)\n", nameIReg(4,reg) ); |
| 1448 | } |
| 1449 | |
| 1450 | /*----------------------------------------------------*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1451 | /*--- Helper offset -> addr translation ---*/ |
| 1452 | /*----------------------------------------------------*/ |
| 1453 | |
| 1454 | /* Finds the baseBlock offset of a skin-specified helper. |
| 1455 | * Searches through compacts first, then non-compacts. */ |
| 1456 | Int VG_(helper_offset)(Addr a) |
| 1457 | { |
| 1458 | Int i; |
| 1459 | |
| 1460 | for (i = 0; i < VG_(n_compact_helpers); i++) |
| 1461 | if (VG_(compact_helper_addrs)[i] == a) |
| 1462 | return VG_(compact_helper_offsets)[i]; |
| 1463 | for (i = 0; i < VG_(n_noncompact_helpers); i++) |
| 1464 | if (VG_(noncompact_helper_addrs)[i] == a) |
| 1465 | return VG_(noncompact_helper_offsets)[i]; |
| 1466 | |
| 1467 | /* Shouldn't get here */ |
| 1468 | VG_(printf)( |
| 1469 | "\nCouldn't find offset of helper from its address (%p).\n" |
| 1470 | "A helper function probably used hasn't been registered?\n\n", a); |
| 1471 | |
| 1472 | VG_(printf)(" compact helpers: "); |
| 1473 | for (i = 0; i < VG_(n_compact_helpers); i++) |
| 1474 | VG_(printf)("%p ", VG_(compact_helper_addrs)[i]); |
| 1475 | |
| 1476 | VG_(printf)("\n non-compact helpers: "); |
| 1477 | for (i = 0; i < VG_(n_noncompact_helpers); i++) |
| 1478 | VG_(printf)("%p ", VG_(noncompact_helper_addrs)[i]); |
| 1479 | |
| 1480 | VG_(printf)("\n"); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1481 | VG_(skin_panic)("Unfound helper"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1482 | } |
| 1483 | |
| 1484 | /*----------------------------------------------------*/ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1485 | /*--- Instruction synthesisers ---*/ |
| 1486 | /*----------------------------------------------------*/ |
| 1487 | |
| 1488 | static Condcode invertCondition ( Condcode cond ) |
| 1489 | { |
| 1490 | return (Condcode)(1 ^ (UInt)cond); |
| 1491 | } |
| 1492 | |
| 1493 | |
| 1494 | /* Synthesise a call to *baseBlock[offset], ie, |
| 1495 | call * (4 x offset)(%ebp). |
| 1496 | */ |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1497 | void VG_(synth_call) ( Bool ensure_shortform, Int word_offset, |
| 1498 | Bool upd_cc, FlagSet use_flags, FlagSet set_flags ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1499 | { |
| 1500 | vg_assert(word_offset >= 0); |
| 1501 | vg_assert(word_offset < VG_BASEBLOCK_WORDS); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1502 | if (ensure_shortform) { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1503 | vg_assert(word_offset < 32); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1504 | } |
| 1505 | emit_call_star_EBP_off ( upd_cc, 4 * word_offset, use_flags, set_flags ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1506 | } |
| 1507 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1508 | static void maybe_emit_movl_reg_reg ( UInt src, UInt dst ) |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1509 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1510 | if (src != dst) { |
| 1511 | VG_(emit_movv_reg_reg) ( 4, src, dst ); |
| 1512 | ccall_arg_setup_instrs++; |
| 1513 | } |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1514 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1515 | |
| 1516 | /* 'maybe' because it is sometimes skipped eg. for "movl %eax,%eax" */ |
| 1517 | static void maybe_emit_movl_litOrReg_reg ( UInt litOrReg, Tag tag, UInt reg ) |
| 1518 | { |
| 1519 | if (RealReg == tag) { |
| 1520 | maybe_emit_movl_reg_reg ( litOrReg, reg ); |
| 1521 | } else if (Literal == tag) { |
| 1522 | VG_(emit_movv_lit_reg) ( 4, litOrReg, reg ); |
| 1523 | ccall_arg_setup_instrs++; |
| 1524 | } |
| 1525 | else |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1526 | VG_(core_panic)("emit_movl_litOrReg_reg: unexpected tag"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1527 | } |
| 1528 | |
| 1529 | static |
| 1530 | void emit_swapl_arg_regs ( UInt reg1, UInt reg2 ) |
| 1531 | { |
| 1532 | if (R_EAX == reg1) { |
| 1533 | VG_(emit_swapl_reg_EAX) ( reg2 ); |
| 1534 | } else if (R_EAX == reg2) { |
| 1535 | VG_(emit_swapl_reg_EAX) ( reg1 ); |
| 1536 | } else { |
| 1537 | emit_swapl_reg_reg ( reg1, reg2 ); |
| 1538 | } |
| 1539 | ccall_arg_setup_instrs++; |
| 1540 | } |
| 1541 | |
| 1542 | static |
| 1543 | void emit_two_regs_args_setup ( UInt src1, UInt src2, UInt dst1, UInt dst2) |
| 1544 | { |
| 1545 | if (dst1 != src2) { |
| 1546 | maybe_emit_movl_reg_reg ( src1, dst1 ); |
| 1547 | maybe_emit_movl_reg_reg ( src2, dst2 ); |
| 1548 | |
| 1549 | } else if (dst2 != src1) { |
| 1550 | maybe_emit_movl_reg_reg ( src2, dst2 ); |
| 1551 | maybe_emit_movl_reg_reg ( src1, dst1 ); |
| 1552 | |
| 1553 | } else { |
| 1554 | /* swap to break cycle */ |
| 1555 | emit_swapl_arg_regs ( dst1, dst2 ); |
| 1556 | } |
| 1557 | } |
| 1558 | |
| 1559 | static |
| 1560 | void emit_three_regs_args_setup ( UInt src1, UInt src2, UInt src3, |
| 1561 | UInt dst1, UInt dst2, UInt dst3) |
| 1562 | { |
| 1563 | if (dst1 != src2 && dst1 != src3) { |
| 1564 | maybe_emit_movl_reg_reg ( src1, dst1 ); |
| 1565 | emit_two_regs_args_setup ( src2, src3, dst2, dst3 ); |
| 1566 | |
| 1567 | } else if (dst2 != src1 && dst2 != src3) { |
| 1568 | maybe_emit_movl_reg_reg ( src2, dst2 ); |
| 1569 | emit_two_regs_args_setup ( src1, src3, dst1, dst3 ); |
| 1570 | |
| 1571 | } else if (dst3 != src1 && dst3 != src2) { |
| 1572 | maybe_emit_movl_reg_reg ( src3, dst3 ); |
| 1573 | emit_two_regs_args_setup ( src1, src2, dst1, dst2 ); |
| 1574 | |
| 1575 | } else { |
| 1576 | /* break cycle */ |
| 1577 | if (dst1 == src2 && dst2 == src3 && dst3 == src1) { |
| 1578 | emit_swapl_arg_regs ( dst1, dst2 ); |
| 1579 | emit_swapl_arg_regs ( dst1, dst3 ); |
| 1580 | |
| 1581 | } else if (dst1 == src3 && dst2 == src1 && dst3 == src2) { |
| 1582 | emit_swapl_arg_regs ( dst1, dst3 ); |
| 1583 | emit_swapl_arg_regs ( dst1, dst2 ); |
| 1584 | |
| 1585 | } else { |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1586 | VG_(core_panic)("impossible 3-cycle"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1587 | } |
| 1588 | } |
| 1589 | } |
| 1590 | |
| 1591 | static |
| 1592 | void emit_two_regs_or_lits_args_setup ( UInt argv[], Tag tagv[], |
| 1593 | UInt src1, UInt src2, |
| 1594 | UInt dst1, UInt dst2) |
| 1595 | { |
| 1596 | /* If either are lits, order doesn't matter */ |
| 1597 | if (Literal == tagv[src1] || Literal == tagv[src2]) { |
| 1598 | maybe_emit_movl_litOrReg_reg ( argv[src1], tagv[src1], dst1 ); |
| 1599 | maybe_emit_movl_litOrReg_reg ( argv[src2], tagv[src2], dst2 ); |
| 1600 | |
| 1601 | } else { |
| 1602 | emit_two_regs_args_setup ( argv[src1], argv[src2], dst1, dst2 ); |
| 1603 | } |
| 1604 | } |
| 1605 | |
| 1606 | static |
| 1607 | void emit_three_regs_or_lits_args_setup ( UInt argv[], Tag tagv[], |
| 1608 | UInt src1, UInt src2, UInt src3, |
| 1609 | UInt dst1, UInt dst2, UInt dst3) |
| 1610 | { |
| 1611 | // SSS: fix this eventually -- make STOREV use two RealRegs? |
| 1612 | /* Not supporting literals for 3-arg C functions -- they're only used |
| 1613 | by STOREV which has 2 args */ |
| 1614 | vg_assert(RealReg == tagv[src1] && |
| 1615 | RealReg == tagv[src2] && |
| 1616 | RealReg == tagv[src3]); |
| 1617 | emit_three_regs_args_setup ( argv[src1], argv[src2], argv[src3], |
| 1618 | dst1, dst2, dst3 ); |
| 1619 | } |
| 1620 | |
| 1621 | /* Synthesise a call to a C function `fn' (which must be registered in |
| 1622 | baseBlock) doing all the reg saving and arg handling work. |
| 1623 | |
| 1624 | WARNING: a UInstr should *not* be translated with synth_ccall followed |
| 1625 | by some other x86 assembly code; vg_liveness_analysis() doesn't expect |
| 1626 | such behaviour and everything will fall over. |
| 1627 | */ |
| 1628 | void VG_(synth_ccall) ( Addr fn, Int argc, Int regparms_n, UInt argv[], |
| 1629 | Tag tagv[], Int ret_reg, |
| 1630 | RRegSet regs_live_before, RRegSet regs_live_after ) |
| 1631 | { |
| 1632 | Int i; |
| 1633 | Int stack_used = 0; |
| 1634 | Bool preserve_eax, preserve_ecx, preserve_edx; |
| 1635 | |
| 1636 | vg_assert(0 <= regparms_n && regparms_n <= 3); |
| 1637 | |
| 1638 | ccalls++; |
| 1639 | |
| 1640 | /* If %e[acd]x is live before and after the C call, save/restore it. |
| 1641 | Unless the return values clobbers the reg; in this case we must not |
| 1642 | save/restore the reg, because the restore would clobber the return |
| 1643 | value. (Before and after the UInstr really constitute separate live |
| 1644 | ranges, but you miss this if you don't consider what happens during |
| 1645 | the UInstr.) */ |
| 1646 | # define PRESERVE_REG(realReg) \ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1647 | (IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), regs_live_before) && \ |
| 1648 | IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), regs_live_after) && \ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1649 | ret_reg != realReg) |
| 1650 | |
| 1651 | preserve_eax = PRESERVE_REG(R_EAX); |
| 1652 | preserve_ecx = PRESERVE_REG(R_ECX); |
| 1653 | preserve_edx = PRESERVE_REG(R_EDX); |
| 1654 | |
| 1655 | # undef PRESERVE_REG |
| 1656 | |
| 1657 | /* Save caller-save regs as required */ |
| 1658 | if (preserve_eax) { VG_(emit_pushv_reg) ( 4, R_EAX ); ccall_reg_saves++; } |
| 1659 | if (preserve_ecx) { VG_(emit_pushv_reg) ( 4, R_ECX ); ccall_reg_saves++; } |
| 1660 | if (preserve_edx) { VG_(emit_pushv_reg) ( 4, R_EDX ); ccall_reg_saves++; } |
| 1661 | |
| 1662 | /* Args are passed in two groups: (a) via stack (b) via regs. regparms_n |
| 1663 | is the number of args passed in regs (maximum 3 for GCC on x86). */ |
| 1664 | |
| 1665 | ccall_args += argc; |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1666 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1667 | /* First push stack args (RealRegs or Literals) in reverse order. */ |
| 1668 | for (i = argc-1; i >= regparms_n; i--) { |
| 1669 | switch (tagv[i]) { |
| 1670 | case RealReg: |
| 1671 | VG_(emit_pushv_reg) ( 4, argv[i] ); |
| 1672 | break; |
| 1673 | case Literal: |
| 1674 | /* Use short form of pushl if possible. */ |
| 1675 | if (argv[i] == VG_(extend_s_8to32) ( argv[i] )) |
| 1676 | VG_(emit_pushl_lit8) ( VG_(extend_s_8to32)(argv[i]) ); |
| 1677 | else |
| 1678 | VG_(emit_pushl_lit32)( argv[i] ); |
| 1679 | break; |
| 1680 | default: |
| 1681 | VG_(printf)("tag=%d\n", tagv[i]); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1682 | VG_(core_panic)("VG_(synth_ccall): bad tag"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1683 | } |
| 1684 | stack_used += 4; |
| 1685 | ccall_arg_setup_instrs++; |
| 1686 | } |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1687 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1688 | /* Then setup args in registers (arg[123] --> %e[adc]x; note order!). |
| 1689 | If moving values between registers, be careful not to clobber any on |
| 1690 | the way. Happily we can use xchgl to swap registers. |
| 1691 | */ |
| 1692 | switch (regparms_n) { |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1693 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1694 | /* Trickiest. Args passed in %eax, %edx, and %ecx. */ |
| 1695 | case 3: |
| 1696 | emit_three_regs_or_lits_args_setup ( argv, tagv, 0, 1, 2, |
| 1697 | R_EAX, R_EDX, R_ECX ); |
| 1698 | break; |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1699 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1700 | /* Less-tricky. Args passed in %eax and %edx. */ |
| 1701 | case 2: |
| 1702 | emit_two_regs_or_lits_args_setup ( argv, tagv, 0, 1, R_EAX, R_EDX ); |
| 1703 | break; |
| 1704 | |
| 1705 | /* Easy. Just move arg1 into %eax (if not already in there). */ |
| 1706 | case 1: |
| 1707 | maybe_emit_movl_litOrReg_reg ( argv[0], tagv[0], R_EAX ); |
| 1708 | break; |
| 1709 | |
| 1710 | case 0: |
| 1711 | break; |
| 1712 | |
| 1713 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1714 | VG_(core_panic)("VG_(synth_call): regparms_n value not in range 0..3"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1715 | } |
| 1716 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1717 | /* Call the function - may trash all flags */ |
| 1718 | VG_(synth_call) ( False, VG_(helper_offset) ( fn ), False, FlagsEmpty, FlagsOSZACP ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1719 | |
| 1720 | /* Clear any args from stack */ |
| 1721 | if (0 != stack_used) { |
| 1722 | VG_(emit_add_lit_to_esp) ( stack_used ); |
| 1723 | ccall_stack_clears++; |
| 1724 | } |
| 1725 | |
| 1726 | /* Move return value into ret_reg if necessary and not already there */ |
| 1727 | if (INVALID_REALREG != ret_reg) { |
| 1728 | ccall_retvals++; |
| 1729 | if (R_EAX != ret_reg) { |
| 1730 | VG_(emit_movv_reg_reg) ( 4, R_EAX, ret_reg ); |
| 1731 | ccall_retval_movs++; |
| 1732 | } |
| 1733 | } |
| 1734 | |
| 1735 | /* Restore live caller-save regs as required */ |
| 1736 | if (preserve_edx) VG_(emit_popv_reg) ( 4, R_EDX ); |
| 1737 | if (preserve_ecx) VG_(emit_popv_reg) ( 4, R_ECX ); |
| 1738 | if (preserve_eax) VG_(emit_popv_reg) ( 4, R_EAX ); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1739 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1740 | |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1741 | static void load_ebp_from_JmpKind ( JmpKind jmpkind ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1742 | { |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1743 | switch (jmpkind) { |
| 1744 | case JmpBoring: |
| 1745 | break; |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1746 | case JmpRet: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1747 | break; |
| 1748 | case JmpCall: |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1749 | break; |
| 1750 | case JmpSyscall: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1751 | VG_(emit_movv_lit_reg) ( 4, VG_TRC_EBP_JMP_SYSCALL, R_EBP ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1752 | break; |
| 1753 | case JmpClientReq: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1754 | VG_(emit_movv_lit_reg) ( 4, VG_TRC_EBP_JMP_CLIENTREQ, R_EBP ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1755 | break; |
| 1756 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1757 | VG_(core_panic)("load_ebp_from_JmpKind"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1758 | } |
| 1759 | } |
| 1760 | |
| 1761 | /* Jump to the next translation, by loading its original addr into |
| 1762 | %eax and returning to the scheduler. Signal special requirements |
| 1763 | by loading a special value into %ebp first. |
| 1764 | */ |
| 1765 | static void synth_jmp_reg ( Int reg, JmpKind jmpkind ) |
| 1766 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1767 | maybe_emit_put_eflags(); /* save flags here */ |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1768 | load_ebp_from_JmpKind ( jmpkind ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1769 | if (reg != R_EAX) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1770 | VG_(emit_movv_reg_reg) ( 4, reg, R_EAX ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1771 | emit_ret(); |
| 1772 | } |
| 1773 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1774 | static void synth_mov_reg_offregmem ( Int size, Int reg, Int off, Int areg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1775 | |
| 1776 | /* Same deal as synth_jmp_reg. */ |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1777 | static void synth_jmp_lit ( Addr addr, JmpKind jmpkind ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1778 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1779 | maybe_emit_put_eflags(); /* save flags here */ |
| 1780 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1781 | VG_(emit_movv_lit_reg) ( 4, addr, R_EAX ); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1782 | |
| 1783 | if (VG_(clo_chain_bb) && (jmpkind == JmpBoring || jmpkind == JmpCall)) { |
| 1784 | synth_mov_reg_offregmem(4, R_EAX, 4*VGOFF_(m_eip), R_EBP); /* update EIP */ |
| 1785 | emit_call_patchme(); |
| 1786 | } else { |
| 1787 | load_ebp_from_JmpKind ( jmpkind ); |
| 1788 | emit_ret(); |
| 1789 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1790 | } |
| 1791 | |
| 1792 | |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1793 | static void synth_mov_offregmem_reg ( Int size, Int off, Int areg, Int reg ); |
| 1794 | static void synth_nonshiftop_lit_reg ( Bool upd_cc, |
| 1795 | Opcode opcode, Int size, |
| 1796 | UInt lit, Int reg ); |
| 1797 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1798 | static void synth_jcond_lit ( Condcode cond, |
| 1799 | Addr addr, |
| 1800 | Bool eax_trashable ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1801 | { |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1802 | UInt mask; |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1803 | Int delta; |
| 1804 | Bool simd; |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1805 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1806 | if (VG_(clo_chain_bb)) { |
| 1807 | /* When using BB chaining, the jump sequence is: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1808 | ensure that simulated eflags are up-to-date |
| 1809 | jmp short if not cond to xyxyxy, using the real |
| 1810 | machine eflags if we can, synthesising a suitable sequence |
| 1811 | to examine the simulated ones otherwise |
| 1812 | addr -> eax |
| 1813 | call VG_(patch_me)/jmp target |
| 1814 | xyxyxy |
| 1815 | |
| 1816 | <possibly sequence to compute some condition> |
| 1817 | j<cond> xyxyxy |
| 1818 | mov $0x4000d190,%eax // 5 |
| 1819 | mov %eax, VGOFF_(m_eip)(%ebp) // 3 |
| 1820 | call 0x40050f9a <vgPlain_patch_me> // 5 |
| 1821 | xyxyxy: mov $0x4000d042,%eax |
| 1822 | call 0x40050f9a <vgPlain_patch_me> |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1823 | */ |
sewardj | 83f1186 | 2002-12-01 02:07:08 +0000 | [diff] [blame] | 1824 | delta = 5+3+5; |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1825 | } else { |
| 1826 | /* When not using BB chaining: |
| 1827 | ensure that simulated eflags are up-to-date |
| 1828 | jmp short if not cond to xyxyxy, using the real |
| 1829 | machine eflags if we can, synthesising a suitable sequence |
| 1830 | to examine the simulated ones otherwise |
| 1831 | addr -> eax |
| 1832 | ret |
| 1833 | xyxyxy |
| 1834 | |
| 1835 | <possibly sequence to compute some condition> |
| 1836 | j<cond> xyxyxy |
| 1837 | movl $0x44556677, %eax // 5 |
| 1838 | ret // 1 |
| 1839 | xyxyxy: |
| 1840 | */ |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1841 | delta = 5+1; |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1842 | } |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1843 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1844 | /* Ensure simulated %EFLAGS are up-to-date, by copying back %eflags |
| 1845 | if need be */ |
| 1846 | maybe_emit_put_eflags(); |
| 1847 | vg_assert(eflags_state == UPD_Both || eflags_state == UPD_Simd); |
| 1848 | |
| 1849 | if (eflags_state == UPD_Both) { |
| 1850 | /* The flags are already set up, so we just use them as is. */ |
| 1851 | simd = True; |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1852 | cond = invertCondition(cond); |
| 1853 | } else { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1854 | |
| 1855 | /* The simd state contains the most recent version, so we emit a |
| 1856 | sequence to calculate the relevant condition directly out of |
| 1857 | the simd flags. This is much cheaper (on P3/P4/Athlon) than |
| 1858 | copying them back to the real flags via popf. Notice that |
| 1859 | some of these sequences trash %eax, but that should be free |
| 1860 | now since this is the end of a bb and therefore all regs are |
| 1861 | dead. */ |
| 1862 | simd = False; |
| 1863 | |
| 1864 | switch (cond) { |
| 1865 | |
| 1866 | case CondLE: |
| 1867 | case CondNLE: |
| 1868 | vg_assert(eax_trashable); |
| 1869 | |
| 1870 | VG_(emit_movv_offregmem_reg) |
| 1871 | ( 4, VGOFF_(m_eflags) * 4, R_EBP, R_EAX ); |
| 1872 | /* eax == %EFLAGS */ |
| 1873 | |
| 1874 | VG_(emit_shiftopv_lit_reg)( False, 4, SHR, 11-7, R_EAX ); |
| 1875 | /* eax has OF in SF's place */ |
| 1876 | |
| 1877 | emit_nonshiftopv_offregmem_reg |
| 1878 | ( False, 4, XOR, VGOFF_(m_eflags) * 4, R_EBP, R_EAX ); |
| 1879 | /* eax has (OF xor SF) in SF's place */ |
| 1880 | |
| 1881 | VG_(emit_shiftopv_lit_reg)( False, 4, SHR, 7-6, R_EAX ); |
| 1882 | /* eax has (OF xor SF) in ZF's place */ |
| 1883 | |
| 1884 | emit_nonshiftopv_offregmem_reg |
| 1885 | ( False, 4, OR, VGOFF_(m_eflags) * 4, R_EBP, R_EAX ); |
| 1886 | /* eax has ((OF xor SF) or ZF) in SF's place */ |
| 1887 | |
| 1888 | VG_(emit_nonshiftopv_lit_reg)( False, 4, AND, 1 << 6, R_EAX ); |
| 1889 | /* Z is now set iff ((OF xor SF) or ZF) == 1 */ |
| 1890 | |
| 1891 | if (cond == CondLE) cond = CondZ; else cond = CondNZ; |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1892 | break; |
| 1893 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1894 | case CondL: |
| 1895 | case CondNL: |
| 1896 | vg_assert(eax_trashable); |
| 1897 | |
| 1898 | VG_(emit_movv_offregmem_reg) |
| 1899 | ( 4, VGOFF_(m_eflags) * 4, R_EBP, R_EAX ); |
| 1900 | /* eax == %EFLAGS */ |
| 1901 | |
| 1902 | VG_(emit_shiftopv_lit_reg)( False, 4, SHR, 11-7, R_EAX ); |
| 1903 | /* eax has OF in SF's place */ |
| 1904 | |
| 1905 | emit_nonshiftopv_offregmem_reg |
| 1906 | ( False, 4, XOR, VGOFF_(m_eflags) * 4, R_EBP, R_EAX ); |
| 1907 | /* eax has (OF xor SF) in SF's place */ |
| 1908 | |
| 1909 | VG_(emit_nonshiftopv_lit_reg)( False, 4, AND, 1 << 7, R_EAX ); |
| 1910 | /* Z is now set iff (OF xor SF) == 1 */ |
| 1911 | |
| 1912 | if (cond == CondL) cond = CondZ; else cond = CondNZ; |
| 1913 | break; |
| 1914 | |
| 1915 | case CondB: |
| 1916 | case CondNB: |
| 1917 | mask = EFlagC; goto simple; /* C=1 */ |
| 1918 | |
| 1919 | case CondZ: |
| 1920 | case CondNZ: |
| 1921 | mask = EFlagZ; goto simple; /* Z=1 */ |
| 1922 | |
| 1923 | case CondBE: |
| 1924 | case CondNBE: |
| 1925 | mask = EFlagC | EFlagZ; goto simple; /* C=1 || Z=1 */ |
| 1926 | |
| 1927 | case CondS: |
| 1928 | case CondNS: |
| 1929 | mask = EFlagS; goto simple; /* S=1 */ |
| 1930 | |
| 1931 | case CondP: |
sewardj | 06d3f8c | 2002-12-08 19:50:36 +0000 | [diff] [blame^] | 1932 | case CondNP: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1933 | mask = EFlagP; goto simple; /* P=1 */ |
| 1934 | |
| 1935 | default: |
| 1936 | VG_(printf)("synth_jcond_lit: unhandled simd case %d (%s)\n", |
| 1937 | (Int)cond, VG_(nameCondcode)(cond) ); |
| 1938 | VG_(core_panic)("synth_jcond_lit: unhandled simd case"); |
| 1939 | |
| 1940 | simple: |
| 1941 | VG_(new_emit)(False, False, FlagsOSZACP); |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1942 | if ((mask & 0xff) == mask) { |
| 1943 | VG_(emitB) ( 0xF6 ); /* Grp3 */ |
| 1944 | VG_(emit_amode_offregmem_reg)( |
| 1945 | VGOFF_(m_eflags) * 4, R_EBP, 0 /* subcode for TEST */); |
| 1946 | VG_(emitB) (mask); |
| 1947 | if (dis) |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1948 | VG_(printf)("\n\t\ttestb $0x%x, %d(%%ebp)\n", |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1949 | mask, VGOFF_(m_eflags) * 4); |
| 1950 | } else { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1951 | /* all cond codes are in lower 16 bits */ |
| 1952 | vg_assert((mask & 0xffff) == mask); |
| 1953 | |
| 1954 | VG_(emitB) ( 0x66 ); |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1955 | VG_(emitB) ( 0xF7 ); |
| 1956 | VG_(emit_amode_offregmem_reg)( |
| 1957 | VGOFF_(m_eflags) * 4, R_EBP, 0 /* subcode for TEST */); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1958 | VG_(emitW) (mask); |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1959 | if (dis) |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1960 | VG_(printf)("\n\t\ttestl $0x%x, %d(%%ebp)\n", |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1961 | mask, VGOFF_(m_eflags) * 4); |
| 1962 | } |
| 1963 | |
| 1964 | if (cond & 1) |
| 1965 | cond = CondNZ; |
| 1966 | else |
| 1967 | cond = CondZ; |
| 1968 | break; |
| 1969 | } |
| 1970 | } |
| 1971 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1972 | VG_(emit_jcondshort_delta) ( simd, cond, delta ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1973 | synth_jmp_lit ( addr, JmpBoring ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1974 | } |
| 1975 | |
| 1976 | |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1977 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1978 | static void synth_jmp_ifzero_reg_lit ( Int reg, Addr addr ) |
| 1979 | { |
| 1980 | /* 0000 83FF00 cmpl $0, %edi |
| 1981 | 0003 750A jnz next |
| 1982 | 0005 B844332211 movl $0x11223344, %eax |
| 1983 | 000a C3 ret |
| 1984 | next: |
| 1985 | */ |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1986 | VG_(emit_cmpl_zero_reg) ( False, reg ); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1987 | if (VG_(clo_chain_bb)) |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1988 | VG_(emit_jcondshort_delta) ( False, CondNZ, 5+3+5 ); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1989 | else |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 1990 | VG_(emit_jcondshort_delta) ( False, CondNZ, 5+1 ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1991 | synth_jmp_lit ( addr, JmpBoring ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1992 | } |
| 1993 | |
| 1994 | |
| 1995 | static void synth_mov_lit_reg ( Int size, UInt lit, Int reg ) |
| 1996 | { |
| 1997 | /* Load the zero-extended literal into reg, at size l, |
| 1998 | regardless of the request size. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1999 | VG_(emit_movv_lit_reg) ( 4, lit, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2000 | } |
| 2001 | |
| 2002 | |
| 2003 | static void synth_mov_regmem_reg ( Int size, Int reg1, Int reg2 ) |
| 2004 | { |
| 2005 | switch (size) { |
| 2006 | case 4: emit_movv_regmem_reg ( 4, reg1, reg2 ); break; |
| 2007 | case 2: emit_movzwl_regmem_reg ( reg1, reg2 ); break; |
| 2008 | case 1: emit_movzbl_regmem_reg ( reg1, reg2 ); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2009 | default: VG_(core_panic)("synth_mov_regmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2010 | } |
| 2011 | } |
| 2012 | |
| 2013 | |
| 2014 | static void synth_mov_offregmem_reg ( Int size, Int off, Int areg, Int reg ) |
| 2015 | { |
| 2016 | switch (size) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2017 | case 4: VG_(emit_movv_offregmem_reg) ( 4, off, areg, reg ); break; |
| 2018 | case 2: VG_(emit_movzwl_offregmem_reg) ( off, areg, reg ); break; |
| 2019 | case 1: VG_(emit_movzbl_offregmem_reg) ( off, areg, reg ); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2020 | default: VG_(core_panic)("synth_mov_offregmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2021 | } |
| 2022 | } |
| 2023 | |
| 2024 | |
| 2025 | static void synth_mov_reg_offregmem ( Int size, Int reg, |
| 2026 | Int off, Int areg ) |
| 2027 | { |
| 2028 | switch (size) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2029 | case 4: VG_(emit_movv_reg_offregmem) ( 4, reg, off, areg ); break; |
| 2030 | case 2: VG_(emit_movv_reg_offregmem) ( 2, reg, off, areg ); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2031 | case 1: if (reg < 4) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2032 | VG_(emit_movb_reg_offregmem) ( reg, off, areg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2033 | } |
| 2034 | else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2035 | VG_(emit_swapl_reg_EAX) ( reg ); |
| 2036 | VG_(emit_movb_reg_offregmem) ( R_AL, off, areg ); |
| 2037 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2038 | } |
| 2039 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2040 | default: VG_(core_panic)("synth_mov_reg_offregmem"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2041 | } |
| 2042 | } |
| 2043 | |
| 2044 | |
| 2045 | static void synth_mov_reg_memreg ( Int size, Int reg1, Int reg2 ) |
| 2046 | { |
| 2047 | Int s1; |
| 2048 | switch (size) { |
| 2049 | case 4: emit_movv_reg_regmem ( 4, reg1, reg2 ); break; |
| 2050 | case 2: emit_movv_reg_regmem ( 2, reg1, reg2 ); break; |
| 2051 | case 1: if (reg1 < 4) { |
| 2052 | emit_movb_reg_regmem ( reg1, reg2 ); |
| 2053 | } |
| 2054 | else { |
| 2055 | /* Choose a swap reg which is < 4 and not reg1 or reg2. */ |
| 2056 | for (s1 = 0; s1 == reg1 || s1 == reg2; s1++) ; |
| 2057 | emit_swapl_reg_reg ( s1, reg1 ); |
| 2058 | emit_movb_reg_regmem ( s1, reg2 ); |
| 2059 | emit_swapl_reg_reg ( s1, reg1 ); |
| 2060 | } |
| 2061 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2062 | default: VG_(core_panic)("synth_mov_reg_litmem"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2063 | } |
| 2064 | } |
| 2065 | |
| 2066 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2067 | static void synth_unaryop_reg ( Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2068 | Opcode opcode, Int size, |
| 2069 | Int reg ) |
| 2070 | { |
| 2071 | /* NB! opcode is a uinstr opcode, not an x86 one! */ |
| 2072 | switch (size) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2073 | case 4: VG_(emit_unaryopv_reg) ( upd_cc, 4, opcode, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2074 | break; |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2075 | case 2: VG_(emit_unaryopv_reg) ( upd_cc, 2, opcode, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2076 | break; |
| 2077 | case 1: if (reg < 4) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2078 | VG_(emit_unaryopb_reg) ( upd_cc, opcode, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2079 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2080 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2081 | VG_(emit_unaryopb_reg) ( upd_cc, opcode, R_AL ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2082 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2083 | } |
| 2084 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2085 | default: VG_(core_panic)("synth_unaryop_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2086 | } |
| 2087 | } |
| 2088 | |
| 2089 | |
| 2090 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2091 | static void synth_nonshiftop_reg_reg ( Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2092 | Opcode opcode, Int size, |
| 2093 | Int reg1, Int reg2 ) |
| 2094 | { |
| 2095 | /* NB! opcode is a uinstr opcode, not an x86 one! */ |
| 2096 | switch (size) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2097 | case 4: VG_(emit_nonshiftopv_reg_reg) ( upd_cc, 4, opcode, reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2098 | break; |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2099 | case 2: VG_(emit_nonshiftopv_reg_reg) ( upd_cc, 2, opcode, reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2100 | break; |
| 2101 | case 1: { /* Horrible ... */ |
| 2102 | Int s1, s2; |
| 2103 | /* Choose s1 and s2 to be x86 regs which we can talk about the |
| 2104 | lowest 8 bits, ie either %eax, %ebx, %ecx or %edx. Make |
| 2105 | sure s1 != s2 and that neither of them equal either reg1 or |
| 2106 | reg2. Then use them as temporaries to make things work. */ |
| 2107 | if (reg1 < 4 && reg2 < 4) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2108 | emit_nonshiftopb_reg_reg(upd_cc, opcode, reg1, reg2); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2109 | break; |
| 2110 | } |
| 2111 | for (s1 = 0; s1 == reg1 || s1 == reg2; s1++) ; |
| 2112 | if (reg1 >= 4 && reg2 < 4) { |
| 2113 | emit_swapl_reg_reg ( reg1, s1 ); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2114 | emit_nonshiftopb_reg_reg(upd_cc, opcode, s1, reg2); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2115 | emit_swapl_reg_reg ( reg1, s1 ); |
| 2116 | break; |
| 2117 | } |
| 2118 | for (s2 = 0; s2 == reg1 || s2 == reg2 || s2 == s1; s2++) ; |
| 2119 | if (reg1 < 4 && reg2 >= 4) { |
| 2120 | emit_swapl_reg_reg ( reg2, s2 ); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2121 | emit_nonshiftopb_reg_reg(upd_cc, opcode, reg1, s2); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2122 | emit_swapl_reg_reg ( reg2, s2 ); |
| 2123 | break; |
| 2124 | } |
| 2125 | if (reg1 >= 4 && reg2 >= 4 && reg1 != reg2) { |
| 2126 | emit_swapl_reg_reg ( reg1, s1 ); |
| 2127 | emit_swapl_reg_reg ( reg2, s2 ); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2128 | emit_nonshiftopb_reg_reg(upd_cc, opcode, s1, s2); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2129 | emit_swapl_reg_reg ( reg1, s1 ); |
| 2130 | emit_swapl_reg_reg ( reg2, s2 ); |
| 2131 | break; |
| 2132 | } |
| 2133 | if (reg1 >= 4 && reg2 >= 4 && reg1 == reg2) { |
| 2134 | emit_swapl_reg_reg ( reg1, s1 ); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2135 | emit_nonshiftopb_reg_reg(upd_cc, opcode, s1, s1); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2136 | emit_swapl_reg_reg ( reg1, s1 ); |
| 2137 | break; |
| 2138 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2139 | VG_(core_panic)("synth_nonshiftopb_reg_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2140 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2141 | default: VG_(core_panic)("synth_nonshiftop_reg_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2142 | } |
| 2143 | } |
| 2144 | |
| 2145 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2146 | static void synth_nonshiftop_reg_offregmem ( |
| 2147 | Bool upd_cc, |
| 2148 | Opcode opcode, Int size, |
| 2149 | Int off, Int areg, Int reg ) |
| 2150 | { |
| 2151 | switch (size) { |
| 2152 | case 4: |
| 2153 | emit_nonshiftopv_reg_offregmem ( upd_cc, 4, opcode, off, areg, reg ); |
| 2154 | break; |
| 2155 | case 2: |
| 2156 | emit_nonshiftopv_reg_offregmem ( upd_cc, 2, opcode, off, areg, reg ); |
| 2157 | break; |
| 2158 | case 1: |
| 2159 | if (reg < 4) { |
| 2160 | emit_nonshiftopb_reg_offregmem ( upd_cc, opcode, off, areg, reg ); |
| 2161 | } else { |
| 2162 | VG_(emit_swapl_reg_EAX) ( reg ); |
| 2163 | emit_nonshiftopb_reg_offregmem ( upd_cc, opcode, off, areg, R_AL ); |
| 2164 | VG_(emit_swapl_reg_EAX) ( reg ); |
| 2165 | } |
| 2166 | break; |
| 2167 | default: |
| 2168 | VG_(core_panic)("synth_nonshiftop_reg_offregmem"); |
| 2169 | } |
| 2170 | } |
| 2171 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2172 | static void synth_nonshiftop_offregmem_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2173 | Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2174 | Opcode opcode, Int size, |
| 2175 | Int off, Int areg, Int reg ) |
| 2176 | { |
| 2177 | switch (size) { |
| 2178 | case 4: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2179 | emit_nonshiftopv_offregmem_reg ( upd_cc, 4, opcode, off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2180 | break; |
| 2181 | case 2: |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2182 | emit_nonshiftopv_offregmem_reg ( upd_cc, 2, opcode, off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2183 | break; |
| 2184 | case 1: |
| 2185 | if (reg < 4) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2186 | emit_nonshiftopb_offregmem_reg ( upd_cc, opcode, off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2187 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2188 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2189 | emit_nonshiftopb_offregmem_reg ( upd_cc, opcode, off, areg, R_AL ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2190 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2191 | } |
| 2192 | break; |
| 2193 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2194 | VG_(core_panic)("synth_nonshiftop_offregmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2195 | } |
| 2196 | } |
| 2197 | |
| 2198 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2199 | static void synth_nonshiftop_lit_reg ( Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2200 | Opcode opcode, Int size, |
| 2201 | UInt lit, Int reg ) |
| 2202 | { |
| 2203 | switch (size) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2204 | case 4: VG_(emit_nonshiftopv_lit_reg) ( upd_cc, 4, opcode, lit, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2205 | break; |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2206 | case 2: VG_(emit_nonshiftopv_lit_reg) ( upd_cc, 2, opcode, lit, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2207 | break; |
| 2208 | case 1: if (reg < 4) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2209 | emit_nonshiftopb_lit_reg ( upd_cc, opcode, lit, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2210 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2211 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2212 | emit_nonshiftopb_lit_reg ( upd_cc, opcode, lit, R_AL ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2213 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2214 | } |
| 2215 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2216 | default: VG_(core_panic)("synth_nonshiftop_lit_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2217 | } |
| 2218 | } |
| 2219 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2220 | static void synth_nonshiftop_lit_offregmem ( Bool upd_cc, |
| 2221 | Opcode opcode, Int size, |
| 2222 | UInt lit, Int off, Int regmem ) |
| 2223 | { |
| 2224 | switch (size) { |
| 2225 | case 4: VG_(emit_nonshiftopv_lit_offregmem) ( upd_cc, 4, opcode, lit, off, regmem ); |
| 2226 | break; |
| 2227 | case 2: VG_(emit_nonshiftopv_lit_offregmem) ( upd_cc, 2, opcode, lit, off, regmem ); |
| 2228 | break; |
| 2229 | case 1: emit_nonshiftopb_lit_offregmem ( upd_cc, opcode, lit, off, regmem ); |
| 2230 | break; |
| 2231 | default: VG_(core_panic)("synth_nonshiftop_lit_offregmem"); |
| 2232 | } |
| 2233 | } |
| 2234 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2235 | |
| 2236 | static void synth_push_reg ( Int size, Int reg ) |
| 2237 | { |
| 2238 | switch (size) { |
| 2239 | case 4: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2240 | VG_(emit_pushv_reg) ( 4, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2241 | break; |
| 2242 | case 2: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2243 | VG_(emit_pushv_reg) ( 2, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2244 | break; |
| 2245 | /* Pray that we don't have to generate this really cruddy bit of |
| 2246 | code very often. Could do better, but can I be bothered? */ |
| 2247 | case 1: |
| 2248 | vg_assert(reg != R_ESP); /* duh */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2249 | VG_(emit_add_lit_to_esp)(-1); |
| 2250 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2251 | emit_movb_AL_zeroESPmem(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2252 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2253 | break; |
| 2254 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2255 | VG_(core_panic)("synth_push_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2256 | } |
| 2257 | } |
| 2258 | |
| 2259 | |
| 2260 | static void synth_pop_reg ( Int size, Int reg ) |
| 2261 | { |
| 2262 | switch (size) { |
| 2263 | case 4: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2264 | VG_(emit_popv_reg) ( 4, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2265 | break; |
| 2266 | case 2: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2267 | VG_(emit_popv_reg) ( 2, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2268 | break; |
| 2269 | case 1: |
| 2270 | /* Same comment as above applies. */ |
| 2271 | vg_assert(reg != R_ESP); /* duh */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2272 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2273 | emit_movb_zeroESPmem_AL(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2274 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
| 2275 | VG_(emit_add_lit_to_esp)(1); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2276 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2277 | default: VG_(core_panic)("synth_pop_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2278 | } |
| 2279 | } |
| 2280 | |
| 2281 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2282 | static void synth_shiftop_reg_reg ( Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2283 | Opcode opcode, Int size, |
| 2284 | Int regs, Int regd ) |
| 2285 | { |
| 2286 | synth_push_reg ( size, regd ); |
| 2287 | if (regs != R_ECX) emit_swapl_reg_ECX ( regs ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2288 | switch (size) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2289 | case 4: emit_shiftopv_cl_stack0 ( upd_cc, 4, opcode ); break; |
| 2290 | case 2: emit_shiftopv_cl_stack0 ( upd_cc, 2, opcode ); break; |
| 2291 | case 1: emit_shiftopb_cl_stack0 ( upd_cc, opcode ); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2292 | default: VG_(core_panic)("synth_shiftop_reg_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2293 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2294 | if (regs != R_ECX) emit_swapl_reg_ECX ( regs ); |
| 2295 | synth_pop_reg ( size, regd ); |
| 2296 | } |
| 2297 | |
| 2298 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2299 | static void synth_shiftop_lit_reg ( Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2300 | Opcode opcode, Int size, |
| 2301 | UInt lit, Int reg ) |
| 2302 | { |
| 2303 | switch (size) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2304 | case 4: VG_(emit_shiftopv_lit_reg) ( upd_cc, 4, opcode, lit, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2305 | break; |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2306 | case 2: VG_(emit_shiftopv_lit_reg) ( upd_cc, 2, opcode, lit, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2307 | break; |
| 2308 | case 1: if (reg < 4) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2309 | emit_shiftopb_lit_reg ( upd_cc, opcode, lit, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2310 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2311 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2312 | emit_shiftopb_lit_reg ( upd_cc, opcode, lit, R_AL ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2313 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2314 | } |
| 2315 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2316 | default: VG_(core_panic)("synth_shiftop_lit_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2317 | } |
| 2318 | } |
| 2319 | |
| 2320 | |
| 2321 | static void synth_setb_reg ( Int reg, Condcode cond ) |
| 2322 | { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2323 | if (reg < 4) { |
| 2324 | emit_setb_reg ( reg, cond ); |
| 2325 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2326 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2327 | emit_setb_reg ( R_AL, cond ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2328 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2329 | } |
| 2330 | } |
| 2331 | |
| 2332 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2333 | static void synth_fpu_regmem ( Bool uses_flags, Bool sets_flags, |
| 2334 | UChar first_byte, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2335 | UChar second_byte_masked, |
| 2336 | Int reg ) |
| 2337 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2338 | emit_fpu_regmem ( uses_flags, sets_flags, first_byte, second_byte_masked, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2339 | } |
| 2340 | |
| 2341 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2342 | static void synth_fpu_no_mem ( Bool uses_flags, Bool sets_flags, |
| 2343 | UChar first_byte, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2344 | UChar second_byte ) |
| 2345 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2346 | emit_fpu_no_mem ( uses_flags, sets_flags, first_byte, second_byte ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2347 | } |
| 2348 | |
| 2349 | |
| 2350 | static void synth_movl_reg_reg ( Int src, Int dst ) |
| 2351 | { |
| 2352 | emit_movl_reg_reg ( src, dst ); |
| 2353 | } |
| 2354 | |
| 2355 | static void synth_cmovl_reg_reg ( Condcode cond, Int src, Int dst ) |
| 2356 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2357 | VG_(emit_jcondshort_delta) ( True, invertCondition(cond), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2358 | 2 /* length of the next insn */ ); |
| 2359 | emit_movl_reg_reg ( src, dst ); |
| 2360 | } |
| 2361 | |
| 2362 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2363 | /*----------------------------------------------------*/ |
| 2364 | /*--- Top level of the uinstr -> x86 translation. ---*/ |
| 2365 | /*----------------------------------------------------*/ |
| 2366 | |
| 2367 | /* Return the byte offset from %ebp (ie, into baseBlock) |
| 2368 | for the specified ArchReg or SpillNo. */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2369 | static Int spillOrArchOffset ( Int size, Tag tag, UInt value ) |
| 2370 | { |
| 2371 | if (tag == SpillNo) { |
| 2372 | vg_assert(size == 4); |
| 2373 | vg_assert(value >= 0 && value < VG_MAX_SPILLSLOTS); |
| 2374 | return 4 * (value + VGOFF_(spillslots)); |
| 2375 | } |
| 2376 | if (tag == ArchReg) { |
| 2377 | switch (value) { |
| 2378 | case R_EAX: return 4 * VGOFF_(m_eax); |
| 2379 | case R_ECX: return 4 * VGOFF_(m_ecx); |
| 2380 | case R_EDX: return 4 * VGOFF_(m_edx); |
| 2381 | case R_EBX: return 4 * VGOFF_(m_ebx); |
| 2382 | case R_ESP: |
| 2383 | if (size == 1) return 4 * VGOFF_(m_eax) + 1; |
| 2384 | else return 4 * VGOFF_(m_esp); |
| 2385 | case R_EBP: |
| 2386 | if (size == 1) return 4 * VGOFF_(m_ecx) + 1; |
| 2387 | else return 4 * VGOFF_(m_ebp); |
| 2388 | case R_ESI: |
| 2389 | if (size == 1) return 4 * VGOFF_(m_edx) + 1; |
| 2390 | else return 4 * VGOFF_(m_esi); |
| 2391 | case R_EDI: |
| 2392 | if (size == 1) return 4 * VGOFF_(m_ebx) + 1; |
| 2393 | else return 4 * VGOFF_(m_edi); |
| 2394 | } |
| 2395 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2396 | VG_(core_panic)("spillOrArchOffset"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2397 | } |
| 2398 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2399 | static Int eflagsOffset ( void ) |
| 2400 | { |
| 2401 | return 4 * VGOFF_(m_eflags); |
| 2402 | } |
| 2403 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2404 | static Int segRegOffset ( UInt archregs ) |
| 2405 | { |
| 2406 | switch (archregs) { |
| 2407 | case R_CS: return 4 * VGOFF_(m_cs); |
| 2408 | case R_SS: return 4 * VGOFF_(m_ss); |
| 2409 | case R_DS: return 4 * VGOFF_(m_ds); |
| 2410 | case R_ES: return 4 * VGOFF_(m_es); |
| 2411 | case R_FS: return 4 * VGOFF_(m_fs); |
| 2412 | case R_GS: return 4 * VGOFF_(m_gs); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2413 | default: VG_(core_panic)("segRegOffset"); |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2414 | } |
| 2415 | } |
| 2416 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2417 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2418 | /* Return the byte offset from %ebp (ie, into baseBlock) |
| 2419 | for the specified shadow register */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2420 | Int VG_(shadow_reg_offset) ( Int arch ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2421 | { |
| 2422 | switch (arch) { |
| 2423 | case R_EAX: return 4 * VGOFF_(sh_eax); |
| 2424 | case R_ECX: return 4 * VGOFF_(sh_ecx); |
| 2425 | case R_EDX: return 4 * VGOFF_(sh_edx); |
| 2426 | case R_EBX: return 4 * VGOFF_(sh_ebx); |
| 2427 | case R_ESP: return 4 * VGOFF_(sh_esp); |
| 2428 | case R_EBP: return 4 * VGOFF_(sh_ebp); |
| 2429 | case R_ESI: return 4 * VGOFF_(sh_esi); |
| 2430 | case R_EDI: return 4 * VGOFF_(sh_edi); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2431 | default: VG_(core_panic)( "shadowOffset"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2432 | } |
| 2433 | } |
| 2434 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2435 | Int VG_(shadow_flags_offset) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2436 | { |
| 2437 | return 4 * VGOFF_(sh_eflags); |
| 2438 | } |
| 2439 | |
| 2440 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2441 | |
| 2442 | static void synth_WIDEN_signed ( Int sz_src, Int sz_dst, Int reg ) |
| 2443 | { |
| 2444 | if (sz_src == 1 && sz_dst == 4) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2445 | VG_(emit_shiftopv_lit_reg) ( False, 4, SHL, 24, reg ); |
| 2446 | VG_(emit_shiftopv_lit_reg) ( False, 4, SAR, 24, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2447 | } |
| 2448 | else if (sz_src == 2 && sz_dst == 4) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2449 | VG_(emit_shiftopv_lit_reg) ( False, 4, SHL, 16, reg ); |
| 2450 | VG_(emit_shiftopv_lit_reg) ( False, 4, SAR, 16, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2451 | } |
| 2452 | else if (sz_src == 1 && sz_dst == 2) { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2453 | VG_(emit_shiftopv_lit_reg) ( False, 2, SHL, 8, reg ); |
| 2454 | VG_(emit_shiftopv_lit_reg) ( False, 2, SAR, 8, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2455 | } |
| 2456 | else |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2457 | VG_(core_panic)("synth_WIDEN"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2458 | } |
| 2459 | |
| 2460 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2461 | static void synth_handle_esp_assignment ( Int i, Int reg, |
| 2462 | RRegSet regs_live_before, |
| 2463 | RRegSet regs_live_after ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2464 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2465 | UInt argv[] = { reg }; |
| 2466 | Tag tagv[] = { RealReg }; |
| 2467 | |
| 2468 | VG_(synth_ccall) ( (Addr) VG_(handle_esp_assignment), 1, 1, argv, tagv, |
| 2469 | INVALID_REALREG, regs_live_before, regs_live_after); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2470 | } |
| 2471 | |
| 2472 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2473 | /*----------------------------------------------------*/ |
| 2474 | /*--- Generate code for a single UInstr. ---*/ |
| 2475 | /*----------------------------------------------------*/ |
| 2476 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2477 | static __inline__ |
| 2478 | Bool writeFlagUse ( UInstr* u ) |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2479 | { |
| 2480 | return (u->flags_w != FlagsEmpty); |
| 2481 | } |
| 2482 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2483 | static __inline__ |
| 2484 | Bool readFlagUse ( UInstr* u ) |
| 2485 | { |
| 2486 | /* If the UInstr writes some flags but not all, then we still need |
| 2487 | to consider it as reading flags so that the unchanged values are |
| 2488 | passed through properly. (D is special) */ |
| 2489 | return |
| 2490 | (u->flags_r != FlagsEmpty) || |
| 2491 | (u->flags_w != FlagsEmpty && u->flags_w != FlagsOSZACP) ; |
| 2492 | } |
| 2493 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2494 | static __inline__ |
| 2495 | Bool anyFlagUse ( UInstr* u ) |
| 2496 | { |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2497 | return readFlagUse(u) || writeFlagUse(u); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2498 | } |
| 2499 | |
| 2500 | |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2501 | /* *fplive==True indicates that the simulated machine's FPU state is in |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2502 | the real FPU. If so we need to be very careful not to trash it. |
| 2503 | If FPU state is live and we deem it necessary to copy it back to |
| 2504 | the simulated machine's FPU state, we do so. The final state of |
| 2505 | fpliveness is returned. In short we _must_ do put_fpu_state if |
| 2506 | there is any chance at all that the code generated for a UInstr |
| 2507 | will change the real FPU state. |
| 2508 | */ |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2509 | static void emitUInstr ( UCodeBlock* cb, Int i, |
| 2510 | RRegSet regs_live_before, |
| 2511 | /* Running state, which we update. */ |
| 2512 | Bool* fplive, /* True<==>FPU state in real FPU */ |
| 2513 | Addr* orig_eip, /* previous curr_eip, or zero */ |
| 2514 | Addr* curr_eip ) /* current eip */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2515 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2516 | Int old_emitted_code_used; |
| 2517 | UInstr* u = &cb->instrs[i]; |
| 2518 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2519 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2520 | VG_(pp_UInstr_regs)(i, u); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2521 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2522 | old_emitted_code_used = emitted_code_used; |
| 2523 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2524 | switch (u->opcode) { |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 2525 | case NOP: case LOCK: case CALLM_S: case CALLM_E: break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2526 | |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2527 | case INCEIP: |
| 2528 | /* Advance %EIP some small amount. */ |
| 2529 | *curr_eip += (UInt)(u->val1); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2530 | |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2531 | if (*orig_eip == 0 /* we don't know what the old value was */ |
| 2532 | || ((*orig_eip & ~0xFF) != (*curr_eip & ~0xFF))) { |
| 2533 | /* We have to update all 32 bits of the value. */ |
| 2534 | VG_(emit_movv_lit_offregmem)( |
| 2535 | 4, *curr_eip, 4*VGOFF_(m_eip), R_EBP); |
| 2536 | } else { |
| 2537 | /* Cool! we only need to update lowest 8 bits */ |
| 2538 | VG_(emit_movb_lit_offregmem)( |
| 2539 | *curr_eip & 0xFF, 4*VGOFF_(m_eip)+0, R_EBP); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2540 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2541 | |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2542 | *orig_eip = *curr_eip; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2543 | break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2544 | |
| 2545 | case LEA1: { |
| 2546 | vg_assert(u->tag1 == RealReg); |
| 2547 | vg_assert(u->tag2 == RealReg); |
| 2548 | emit_lea_litreg_reg ( u->lit32, u->val1, u->val2 ); |
| 2549 | break; |
| 2550 | } |
| 2551 | |
| 2552 | case LEA2: { |
| 2553 | vg_assert(u->tag1 == RealReg); |
| 2554 | vg_assert(u->tag2 == RealReg); |
| 2555 | vg_assert(u->tag3 == RealReg); |
| 2556 | emit_lea_sib_reg ( u->lit32, u->extra4b, |
| 2557 | u->val1, u->val2, u->val3 ); |
| 2558 | break; |
| 2559 | } |
| 2560 | |
| 2561 | case WIDEN: { |
| 2562 | vg_assert(u->tag1 == RealReg); |
| 2563 | if (u->signed_widen) { |
| 2564 | synth_WIDEN_signed ( u->extra4b, u->size, u->val1 ); |
| 2565 | } else { |
| 2566 | /* no need to generate any code. */ |
| 2567 | } |
| 2568 | break; |
| 2569 | } |
| 2570 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2571 | case STORE: { |
| 2572 | vg_assert(u->tag1 == RealReg); |
| 2573 | vg_assert(u->tag2 == RealReg); |
| 2574 | synth_mov_reg_memreg ( u->size, u->val1, u->val2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2575 | break; |
| 2576 | } |
| 2577 | |
| 2578 | case LOAD: { |
| 2579 | vg_assert(u->tag1 == RealReg); |
| 2580 | vg_assert(u->tag2 == RealReg); |
| 2581 | synth_mov_regmem_reg ( u->size, u->val1, u->val2 ); |
| 2582 | break; |
| 2583 | } |
| 2584 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2585 | case GET: { |
| 2586 | vg_assert(u->tag1 == ArchReg || u->tag1 == SpillNo); |
| 2587 | vg_assert(u->tag2 == RealReg); |
| 2588 | synth_mov_offregmem_reg ( |
| 2589 | u->size, |
| 2590 | spillOrArchOffset( u->size, u->tag1, u->val1 ), |
| 2591 | R_EBP, |
| 2592 | u->val2 |
| 2593 | ); |
| 2594 | break; |
| 2595 | } |
| 2596 | |
| 2597 | case PUT: { |
| 2598 | vg_assert(u->tag2 == ArchReg || u->tag2 == SpillNo); |
| 2599 | vg_assert(u->tag1 == RealReg); |
| 2600 | if (u->tag2 == ArchReg |
| 2601 | && u->val2 == R_ESP |
| 2602 | && u->size == 4 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2603 | && (VG_(track_events).new_mem_stack || |
| 2604 | VG_(track_events).new_mem_stack_aligned || |
| 2605 | VG_(track_events).die_mem_stack || |
| 2606 | VG_(track_events).die_mem_stack_aligned || |
| 2607 | VG_(track_events).post_mem_write)) |
| 2608 | { |
| 2609 | synth_handle_esp_assignment ( i, u->val1, regs_live_before, |
| 2610 | u->regs_live_after ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2611 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2612 | else { |
| 2613 | synth_mov_reg_offregmem ( |
| 2614 | u->size, |
| 2615 | u->val1, |
| 2616 | spillOrArchOffset( u->size, u->tag2, u->val2 ), |
| 2617 | R_EBP |
| 2618 | ); |
| 2619 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2620 | break; |
| 2621 | } |
| 2622 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2623 | case GETSEG: { |
| 2624 | vg_assert(u->tag1 == ArchRegS); |
| 2625 | vg_assert(u->tag2 == RealReg); |
| 2626 | vg_assert(u->size == 2); |
| 2627 | synth_mov_offregmem_reg ( |
| 2628 | 4, |
| 2629 | segRegOffset( u->val1 ), |
| 2630 | R_EBP, |
| 2631 | u->val2 |
| 2632 | ); |
| 2633 | break; |
| 2634 | } |
| 2635 | |
| 2636 | case PUTSEG: { |
| 2637 | vg_assert(u->tag1 == RealReg); |
| 2638 | vg_assert(u->tag2 == ArchRegS); |
| 2639 | vg_assert(u->size == 2); |
| 2640 | synth_mov_reg_offregmem ( |
| 2641 | 4, |
| 2642 | u->val1, |
| 2643 | segRegOffset( u->val2 ), |
| 2644 | R_EBP |
| 2645 | ); |
| 2646 | break; |
| 2647 | } |
| 2648 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2649 | case GETF: { |
| 2650 | vg_assert(u->size == 2 || u->size == 4); |
| 2651 | vg_assert(u->tag1 == RealReg); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2652 | |
| 2653 | /* This complexity is because the D(irection) flag is stored |
| 2654 | separately from the rest of EFLAGS. */ |
| 2655 | |
| 2656 | /* We're only fetching from the Simd state, so make sure it's |
| 2657 | up to date. */ |
| 2658 | maybe_emit_put_eflags(); |
| 2659 | |
| 2660 | /* get D in u->val1 (== 1 or -1) */ |
| 2661 | synth_mov_offregmem_reg (u->size, 4*VGOFF_(m_dflag), R_EBP, u->val1); |
| 2662 | |
| 2663 | /* u->val1 &= EFlagD (== 0 or EFlagD) */ |
| 2664 | synth_nonshiftop_lit_reg(False, AND, u->size, EFlagD, u->val1); |
| 2665 | |
| 2666 | /* EFLAGS &= ~EFlagD (make sure there's no surprises) */ |
| 2667 | synth_nonshiftop_lit_offregmem(False, AND, u->size, ~EFlagD, |
| 2668 | eflagsOffset(), R_EBP); |
| 2669 | |
| 2670 | /* EFLAGS &= ~EFlagD (make sure there's no surprises) */ |
| 2671 | synth_nonshiftop_lit_offregmem(False, AND, u->size, ~EFlagD, |
| 2672 | eflagsOffset(), R_EBP); |
| 2673 | |
| 2674 | /* u->val1 |= EFLAGS (EFLAGS & EflagD == 0) */ |
| 2675 | synth_nonshiftop_offregmem_reg(False, OR, u->size, |
| 2676 | eflagsOffset(), R_EBP, u->val1); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2677 | break; |
| 2678 | } |
| 2679 | |
| 2680 | case PUTF: { |
| 2681 | vg_assert(u->size == 2 || u->size == 4); |
| 2682 | vg_assert(u->tag1 == RealReg); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2683 | |
| 2684 | /* When putting a value into EFLAGS, this generates the |
| 2685 | correct value for m_dflag (-1 or 1), and clears the D bit |
| 2686 | in EFLAGS. */ |
| 2687 | |
| 2688 | /* We're updating the whole flag state, so the old state |
| 2689 | doesn't matter; make sure that the new simulated state |
| 2690 | will be fetched when needed. */ |
| 2691 | eflags_state = UPD_Simd; |
| 2692 | |
| 2693 | /* store EFLAGS (with D) */ |
| 2694 | synth_mov_reg_offregmem (u->size, u->val1, eflagsOffset(), R_EBP); |
| 2695 | |
| 2696 | /* u->val1 &= EFlagD */ |
| 2697 | synth_nonshiftop_lit_reg(False, AND, u->size, EFlagD, u->val1); |
| 2698 | |
| 2699 | /* computes: u->val1 = (u->val1 == 0) ? 1 : -1 */ |
| 2700 | synth_unaryop_reg(False, NEG, u->size, u->val1); |
| 2701 | synth_nonshiftop_reg_reg(False, SBB, u->size, u->val1, u->val1); |
| 2702 | synth_nonshiftop_lit_reg(False, SBB, u->size, -1, u->val1); |
| 2703 | |
| 2704 | /* save D */ |
| 2705 | synth_mov_reg_offregmem(u->size, u->val1, 4*VGOFF_(m_dflag), R_EBP); |
| 2706 | |
| 2707 | /* EFLAGS &= ~EFlagD */ |
| 2708 | synth_nonshiftop_lit_offregmem(False, AND, u->size, ~EFlagD, |
| 2709 | eflagsOffset(), R_EBP); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2710 | break; |
| 2711 | } |
| 2712 | |
| 2713 | case MOV: { |
| 2714 | vg_assert(u->tag1 == RealReg || u->tag1 == Literal); |
| 2715 | vg_assert(u->tag2 == RealReg); |
| 2716 | switch (u->tag1) { |
| 2717 | case RealReg: vg_assert(u->size == 4); |
| 2718 | if (u->val1 != u->val2) |
| 2719 | synth_movl_reg_reg ( u->val1, u->val2 ); |
| 2720 | break; |
| 2721 | case Literal: synth_mov_lit_reg ( u->size, u->lit32, u->val2 ); |
| 2722 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2723 | default: VG_(core_panic)("emitUInstr:mov"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2724 | } |
| 2725 | break; |
| 2726 | } |
| 2727 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2728 | case USESEG: { |
| 2729 | /* Lazy: copy all three vals; synth_ccall ignores any unnecessary |
| 2730 | ones. */ |
sewardj | d077f53 | 2002-09-30 21:52:50 +0000 | [diff] [blame] | 2731 | UInt argv[] = { u->val1, u->val2 }; |
| 2732 | UInt tagv[] = { RealReg, RealReg }; |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2733 | UInt ret_reg = u->val2; |
| 2734 | |
| 2735 | vg_assert(u->tag1 == RealReg); |
| 2736 | vg_assert(u->tag2 == RealReg); |
| 2737 | vg_assert(u->size == 0); |
| 2738 | |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2739 | if (*fplive) { |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2740 | emit_put_fpu_state(); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2741 | *fplive = False; |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2742 | } |
| 2743 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2744 | VG_(synth_ccall) ( (Addr) & VG_(do_useseg), |
| 2745 | 2, /* args */ |
| 2746 | 0, /* regparms_n */ |
| 2747 | argv, tagv, |
| 2748 | ret_reg, regs_live_before, u->regs_live_after ); |
| 2749 | break; |
| 2750 | } |
| 2751 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2752 | case SBB: |
| 2753 | case ADC: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2754 | case XOR: |
| 2755 | case OR: |
| 2756 | case AND: |
| 2757 | case SUB: |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2758 | case ADD: { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2759 | vg_assert(u->tag2 == RealReg); |
| 2760 | switch (u->tag1) { |
| 2761 | case Literal: synth_nonshiftop_lit_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2762 | anyFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2763 | u->opcode, u->size, u->lit32, u->val2 ); |
| 2764 | break; |
| 2765 | case RealReg: synth_nonshiftop_reg_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2766 | anyFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2767 | u->opcode, u->size, u->val1, u->val2 ); |
| 2768 | break; |
| 2769 | case ArchReg: synth_nonshiftop_offregmem_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2770 | anyFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2771 | u->opcode, u->size, |
| 2772 | spillOrArchOffset( u->size, u->tag1, u->val1 ), |
| 2773 | R_EBP, |
| 2774 | u->val2 ); |
| 2775 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2776 | default: VG_(core_panic)("emitUInstr:non-shift-op"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2777 | } |
| 2778 | break; |
| 2779 | } |
| 2780 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2781 | case RCR: |
| 2782 | case RCL: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2783 | case ROR: |
| 2784 | case ROL: |
| 2785 | case SAR: |
| 2786 | case SHR: |
| 2787 | case SHL: { |
| 2788 | vg_assert(u->tag2 == RealReg); |
| 2789 | switch (u->tag1) { |
| 2790 | case Literal: synth_shiftop_lit_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2791 | anyFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2792 | u->opcode, u->size, u->lit32, u->val2 ); |
| 2793 | break; |
| 2794 | case RealReg: synth_shiftop_reg_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2795 | anyFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2796 | u->opcode, u->size, u->val1, u->val2 ); |
| 2797 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2798 | default: VG_(core_panic)("emitUInstr:non-shift-op"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2799 | } |
| 2800 | break; |
| 2801 | } |
| 2802 | |
| 2803 | case INC: |
| 2804 | case DEC: |
| 2805 | case NEG: |
| 2806 | case NOT: |
| 2807 | vg_assert(u->tag1 == RealReg); |
| 2808 | synth_unaryop_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2809 | anyFlagUse(u), u->opcode, u->size, u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2810 | break; |
| 2811 | |
| 2812 | case BSWAP: |
| 2813 | vg_assert(u->tag1 == RealReg); |
| 2814 | vg_assert(u->size == 4); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2815 | vg_assert(!VG_(any_flag_use)(u)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2816 | emit_bswapl_reg ( u->val1 ); |
| 2817 | break; |
| 2818 | |
| 2819 | case CMOV: |
| 2820 | vg_assert(u->tag1 == RealReg); |
| 2821 | vg_assert(u->tag2 == RealReg); |
| 2822 | vg_assert(u->cond != CondAlways); |
| 2823 | vg_assert(u->size == 4); |
| 2824 | synth_cmovl_reg_reg ( u->cond, u->val1, u->val2 ); |
| 2825 | break; |
| 2826 | |
| 2827 | case JMP: { |
| 2828 | vg_assert(u->tag2 == NoValue); |
| 2829 | vg_assert(u->tag1 == RealReg || u->tag1 == Literal); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2830 | if (*fplive) { |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2831 | emit_put_fpu_state(); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2832 | *fplive = False; |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2833 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2834 | if (u->cond == CondAlways) { |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2835 | switch (u->tag1) { |
| 2836 | case RealReg: |
| 2837 | synth_jmp_reg ( u->val1, u->jmpkind ); |
| 2838 | break; |
| 2839 | case Literal: |
| 2840 | synth_jmp_lit ( u->lit32, u->jmpkind ); |
| 2841 | break; |
| 2842 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2843 | VG_(core_panic)("emitUInstr(JMP, unconditional, default)"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2844 | break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2845 | } |
| 2846 | } else { |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2847 | switch (u->tag1) { |
| 2848 | case RealReg: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2849 | VG_(core_panic)("emitUInstr(JMP, conditional, RealReg)"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2850 | break; |
| 2851 | case Literal: |
| 2852 | vg_assert(u->jmpkind == JmpBoring); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2853 | /* %eax had better not be live since synth_jcond_lit |
| 2854 | trashes it in some circumstances. If that turns |
| 2855 | out to be a problem we can get synth_jcond_lit to |
| 2856 | push/pop it when it is live. */ |
| 2857 | vg_assert(! IS_RREG_LIVE(VG_(realreg_to_rank)(R_EAX), |
| 2858 | u->regs_live_after)); |
| 2859 | synth_jcond_lit ( u->cond, u->lit32, True ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2860 | break; |
| 2861 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2862 | VG_(core_panic)("emitUInstr(JMP, conditional, default)"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2863 | break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2864 | } |
| 2865 | } |
| 2866 | break; |
| 2867 | } |
| 2868 | |
| 2869 | case JIFZ: |
| 2870 | vg_assert(u->tag1 == RealReg); |
| 2871 | vg_assert(u->tag2 == Literal); |
| 2872 | vg_assert(u->size == 4); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2873 | if (*fplive) { |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2874 | emit_put_fpu_state(); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2875 | *fplive = False; |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2876 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2877 | synth_jmp_ifzero_reg_lit ( u->val1, u->lit32 ); |
| 2878 | break; |
| 2879 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2880 | case PUSH: |
| 2881 | vg_assert(u->tag1 == RealReg); |
| 2882 | vg_assert(u->tag2 == NoValue); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2883 | VG_(emit_pushv_reg) ( 4, u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2884 | break; |
| 2885 | |
| 2886 | case POP: |
| 2887 | vg_assert(u->tag1 == RealReg); |
| 2888 | vg_assert(u->tag2 == NoValue); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2889 | VG_(emit_popv_reg) ( 4, u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2890 | break; |
| 2891 | |
| 2892 | case CALLM: |
| 2893 | vg_assert(u->tag1 == Lit16); |
| 2894 | vg_assert(u->tag2 == NoValue); |
| 2895 | vg_assert(u->size == 0); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2896 | if (*fplive) { |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2897 | emit_put_fpu_state(); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2898 | *fplive = False; |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2899 | } |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2900 | /* Call to a helper which is pretending to be a real CPU |
| 2901 | instruction (and therefore operates on Real flags and |
| 2902 | registers) */ |
| 2903 | VG_(synth_call) ( False, u->val1, |
| 2904 | True, u->flags_r, u->flags_w ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2905 | break; |
| 2906 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2907 | case CCALL: { |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2908 | /* If you change this, remember to change USESEG above, since |
| 2909 | that's just a copy of this, slightly simplified. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2910 | /* Lazy: copy all three vals; synth_ccall ignores any unnecessary |
| 2911 | ones. */ |
| 2912 | UInt argv[] = { u->val1, u->val2, u->val3 }; |
| 2913 | UInt tagv[] = { RealReg, RealReg, RealReg }; |
| 2914 | UInt ret_reg = ( u->has_ret_val ? u->val3 : INVALID_REALREG ); |
| 2915 | |
| 2916 | if (u->argc >= 1) vg_assert(u->tag1 == RealReg); |
| 2917 | else vg_assert(u->tag1 == NoValue); |
| 2918 | if (u->argc >= 2) vg_assert(u->tag2 == RealReg); |
| 2919 | else vg_assert(u->tag2 == NoValue); |
| 2920 | if (u->argc == 3 || u->has_ret_val) vg_assert(u->tag3 == RealReg); |
| 2921 | else vg_assert(u->tag3 == NoValue); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 2922 | vg_assert(u->size == 0); |
| 2923 | |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2924 | if (*fplive) { |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2925 | emit_put_fpu_state(); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2926 | *fplive = False; |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2927 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2928 | VG_(synth_ccall) ( u->lit32, u->argc, u->regparms_n, argv, tagv, |
| 2929 | ret_reg, regs_live_before, u->regs_live_after ); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 2930 | break; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2931 | } |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2932 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2933 | case CLEAR: |
| 2934 | vg_assert(u->tag1 == Lit16); |
| 2935 | vg_assert(u->tag2 == NoValue); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2936 | VG_(emit_add_lit_to_esp) ( u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2937 | break; |
| 2938 | |
| 2939 | case CC2VAL: |
| 2940 | vg_assert(u->tag1 == RealReg); |
| 2941 | vg_assert(u->tag2 == NoValue); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2942 | vg_assert(VG_(any_flag_use)(u)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2943 | synth_setb_reg ( u->val1, u->cond ); |
| 2944 | break; |
| 2945 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2946 | case FPU_R: |
| 2947 | case FPU_W: |
| 2948 | vg_assert(u->tag1 == Lit16); |
| 2949 | vg_assert(u->tag2 == RealReg); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2950 | if (!(*fplive)) { |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2951 | emit_get_fpu_state(); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2952 | *fplive = True; |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2953 | } |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2954 | synth_fpu_regmem ( u->flags_r, u->flags_w, |
| 2955 | (u->val1 >> 8) & 0xFF, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2956 | u->val1 & 0xFF, |
| 2957 | u->val2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2958 | break; |
| 2959 | |
| 2960 | case FPU: |
| 2961 | vg_assert(u->tag1 == Lit16); |
| 2962 | vg_assert(u->tag2 == NoValue); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2963 | if (anyFlagUse ( u )) |
sewardj | 4a7456e | 2002-03-24 13:52:19 +0000 | [diff] [blame] | 2964 | emit_get_eflags(); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2965 | if (!(*fplive)) { |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2966 | emit_get_fpu_state(); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2967 | *fplive = True; |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2968 | } |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 2969 | synth_fpu_no_mem ( u->flags_r, u->flags_w, |
| 2970 | (u->val1 >> 8) & 0xFF, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2971 | u->val1 & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2972 | break; |
| 2973 | |
| 2974 | default: |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2975 | if (VG_(needs).extended_UCode) { |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2976 | if (*fplive) { |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2977 | emit_put_fpu_state(); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2978 | *fplive = False; |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2979 | } |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2980 | SK_(emit_XUInstr)(u, regs_live_before); |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2981 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2982 | VG_(printf)("\nError:\n" |
| 2983 | " unhandled opcode: %u. Perhaps " |
| 2984 | " VG_(needs).extended_UCode should be set?\n", |
| 2985 | u->opcode); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2986 | VG_(pp_UInstr)(0,u); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2987 | VG_(core_panic)("emitUInstr: unimplemented opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2988 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2989 | } |
| 2990 | |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2991 | if (0 && (*fplive)) { |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2992 | emit_put_fpu_state(); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 2993 | *fplive = False; |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2994 | } |
| 2995 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2996 | /* Update UInstr histogram */ |
| 2997 | vg_assert(u->opcode < 100); |
| 2998 | histogram[u->opcode].counts++; |
| 2999 | histogram[u->opcode].size += (emitted_code_used - old_emitted_code_used); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3000 | } |
| 3001 | |
| 3002 | |
| 3003 | /* Emit x86 for the ucode in cb, returning the address of the |
| 3004 | generated code and setting *nbytes to its size. */ |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 3005 | UChar* VG_(emit_code) ( UCodeBlock* cb, |
| 3006 | Int* nbytes, |
| 3007 | UShort j[VG_MAX_JUMPS] ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3008 | { |
| 3009 | Int i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 3010 | UChar regs_live_before = 0; /* No regs live at BB start */ |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 3011 | Bool fplive; |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 3012 | Addr orig_eip, curr_eip; |
| 3013 | |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 3014 | reset_state(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3015 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 3016 | if (dis) VG_(printf)("Generated x86 code:\n"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3017 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 3018 | /* Generate decl VG_(dispatch_ctr) and drop into dispatch if we hit |
| 3019 | zero. We have to do this regardless of whether we're t-chaining |
| 3020 | or not. */ |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 3021 | VG_(new_emit)(False, FlagsEmpty, FlagsOSZAP); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 3022 | VG_(emitB) (0xFF); /* decl */ |
| 3023 | emit_amode_litmem_reg((Addr)&VG_(dispatch_ctr), 1); |
| 3024 | if (dis) |
| 3025 | VG_(printf)("\n\t\tdecl (%p)\n", &VG_(dispatch_ctr)); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 3026 | VG_(emit_jcondshort_delta)(False, CondNZ, 5+1); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 3027 | VG_(emit_movv_lit_reg) ( 4, VG_TRC_INNER_COUNTERZERO, R_EBP ); |
| 3028 | emit_ret(); |
| 3029 | |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 3030 | /* Set up running state. */ |
| 3031 | fplive = False; |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 3032 | orig_eip = cb->orig_eip; /* we know EIP is up to date on BB entry */ |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 3033 | curr_eip = cb->orig_eip; |
| 3034 | vg_assert(curr_eip != 0); /* otherwise the incremental updating |
| 3035 | algorithm gets messed up. */ |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 3036 | /* for each uinstr ... */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3037 | for (i = 0; i < cb->used; i++) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 3038 | UInstr* u = &cb->instrs[i]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3039 | if (cb->instrs[i].opcode != NOP) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 3040 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3041 | /* Check on the sanity of this insn. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 3042 | Bool sane = VG_(saneUInstr)( False, False, u ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3043 | if (!sane) { |
| 3044 | VG_(printf)("\ninsane instruction\n"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 3045 | VG_(up_UInstr)( i, u ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3046 | } |
| 3047 | vg_assert(sane); |
sewardj | b5ff83e | 2002-12-01 19:40:49 +0000 | [diff] [blame] | 3048 | emitUInstr( cb, i, regs_live_before, |
| 3049 | &fplive, &orig_eip, &curr_eip ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3050 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 3051 | regs_live_before = u->regs_live_after; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3052 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 3053 | if (dis) VG_(printf)("\n"); |
sewardj | fa492d4 | 2002-12-08 18:20:01 +0000 | [diff] [blame] | 3054 | vg_assert(!fplive); /* FPU state must be saved by end of BB */ |
| 3055 | vg_assert(eflags_state != UPD_Real); /* flags can't just be in CPU */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3056 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 3057 | if (j != NULL) { |
| 3058 | vg_assert(jumpidx <= VG_MAX_JUMPS); |
| 3059 | for(i = 0; i < jumpidx; i++) |
| 3060 | j[i] = jumps[i]; |
| 3061 | } |
| 3062 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3063 | /* Returns a pointer to the emitted code. This will have to be |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 3064 | copied by the caller into the translation cache, and then freed */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3065 | *nbytes = emitted_code_used; |
| 3066 | return emitted_code; |
| 3067 | } |
| 3068 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 3069 | #undef dis |
| 3070 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 3071 | /*--------------------------------------------------------------------*/ |
| 3072 | /*--- end vg_from_ucode.c ---*/ |
| 3073 | /*--------------------------------------------------------------------*/ |