sewardj | 07133bf | 2002-06-13 10:25:56 +0000 | [diff] [blame] | 1 | |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 2 | /*--------------------------------------------------------------------*/ |
njn | 101e572 | 2005-04-21 02:37:54 +0000 | [diff] [blame] | 3 | /*--- Cachegrind: everything but the simulation itself. ---*/ |
njn25 | cac76cb | 2002-09-23 11:21:57 +0000 | [diff] [blame] | 4 | /*--- cg_main.c ---*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 5 | /*--------------------------------------------------------------------*/ |
| 6 | |
| 7 | /* |
nethercote | 137bc55 | 2003-11-14 17:47:54 +0000 | [diff] [blame] | 8 | This file is part of Cachegrind, a Valgrind tool for cache |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 9 | profiling programs. |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 10 | |
sewardj | 0f157dd | 2013-10-18 14:27:36 +0000 | [diff] [blame] | 11 | Copyright (C) 2002-2013 Nicholas Nethercote |
njn | 2bc1012 | 2005-05-08 02:10:27 +0000 | [diff] [blame] | 12 | njn@valgrind.org |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 13 | |
| 14 | This program is free software; you can redistribute it and/or |
| 15 | modify it under the terms of the GNU General Public License as |
| 16 | published by the Free Software Foundation; either version 2 of the |
| 17 | License, or (at your option) any later version. |
| 18 | |
| 19 | This program is distributed in the hope that it will be useful, but |
| 20 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 22 | General Public License for more details. |
| 23 | |
| 24 | You should have received a copy of the GNU General Public License |
| 25 | along with this program; if not, write to the Free Software |
| 26 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 27 | 02111-1307, USA. |
| 28 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 29 | The GNU General Public License is contained in the file COPYING. |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 30 | */ |
| 31 | |
njn | c7561b9 | 2005-06-19 01:24:32 +0000 | [diff] [blame] | 32 | #include "pub_tool_basics.h" |
sewardj | 4cfea4f | 2006-10-14 19:26:10 +0000 | [diff] [blame] | 33 | #include "pub_tool_vki.h" |
njn | ea27e46 | 2005-05-31 02:38:09 +0000 | [diff] [blame] | 34 | #include "pub_tool_debuginfo.h" |
njn | 97405b2 | 2005-06-02 03:39:33 +0000 | [diff] [blame] | 35 | #include "pub_tool_libcbase.h" |
njn | 132bfcc | 2005-06-04 19:16:06 +0000 | [diff] [blame] | 36 | #include "pub_tool_libcassert.h" |
njn | eb8896b | 2005-06-04 20:03:55 +0000 | [diff] [blame] | 37 | #include "pub_tool_libcfile.h" |
njn | 36a20fa | 2005-06-03 03:08:39 +0000 | [diff] [blame] | 38 | #include "pub_tool_libcprint.h" |
njn | f39e9a3 | 2005-06-12 02:43:17 +0000 | [diff] [blame] | 39 | #include "pub_tool_libcproc.h" |
njn | f536bbb | 2005-06-13 04:21:38 +0000 | [diff] [blame] | 40 | #include "pub_tool_machine.h" |
njn | 717cde5 | 2005-05-10 02:47:21 +0000 | [diff] [blame] | 41 | #include "pub_tool_mallocfree.h" |
njn | 2024234 | 2005-05-16 23:31:24 +0000 | [diff] [blame] | 42 | #include "pub_tool_options.h" |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 43 | #include "pub_tool_oset.h" |
njn | 43b9a8a | 2005-05-10 04:37:01 +0000 | [diff] [blame] | 44 | #include "pub_tool_tooliface.h" |
sewardj | 14c7cc5 | 2007-02-25 15:08:24 +0000 | [diff] [blame] | 45 | #include "pub_tool_xarray.h" |
sewardj | 45f4e7c | 2005-09-27 19:20:21 +0000 | [diff] [blame] | 46 | #include "pub_tool_clientstate.h" |
sewardj | 5bb8682 | 2005-12-23 12:47:42 +0000 | [diff] [blame] | 47 | #include "pub_tool_machine.h" // VG_(fnptr_to_fnentry) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 48 | |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 49 | #include "cg_arch.h" |
nethercote | 27fc1da | 2004-01-04 16:56:57 +0000 | [diff] [blame] | 50 | #include "cg_sim.c" |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 51 | #include "cg_branchpred.c" |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 52 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 53 | /*------------------------------------------------------------*/ |
| 54 | /*--- Constants ---*/ |
| 55 | /*------------------------------------------------------------*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 56 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 57 | /* Set to 1 for very verbose debugging */ |
| 58 | #define DEBUG_CG 0 |
| 59 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 60 | #define MIN_LINE_SIZE 16 |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 61 | #define FILE_LEN VKI_PATH_MAX |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 62 | #define FN_LEN 256 |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 63 | |
| 64 | /*------------------------------------------------------------*/ |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 65 | /*--- Options ---*/ |
| 66 | /*------------------------------------------------------------*/ |
| 67 | |
njn | 374a36d | 2007-11-23 01:41:32 +0000 | [diff] [blame] | 68 | static Bool clo_cache_sim = True; /* do cache simulation? */ |
| 69 | static Bool clo_branch_sim = False; /* do branch simulation? */ |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 70 | static const HChar* clo_cachegrind_out_file = "cachegrind.out.%p"; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 71 | |
| 72 | /*------------------------------------------------------------*/ |
sewardj | 98763d5 | 2012-06-03 22:40:07 +0000 | [diff] [blame] | 73 | /*--- Cachesim configuration ---*/ |
| 74 | /*------------------------------------------------------------*/ |
| 75 | |
| 76 | static Int min_line_size = 0; /* min of L1 and LL cache line sizes */ |
| 77 | |
| 78 | /*------------------------------------------------------------*/ |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 79 | /*--- Types and Data Structures ---*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 80 | /*------------------------------------------------------------*/ |
| 81 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 82 | typedef |
| 83 | struct { |
| 84 | ULong a; /* total # memory accesses of this kind */ |
| 85 | ULong m1; /* misses in the first level cache */ |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 86 | ULong mL; /* misses in the second level cache */ |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 87 | } |
| 88 | CacheCC; |
| 89 | |
| 90 | typedef |
| 91 | struct { |
| 92 | ULong b; /* total # branches of this kind */ |
| 93 | ULong mp; /* number of branches mispredicted */ |
| 94 | } |
| 95 | BranchCC; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 96 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 97 | //------------------------------------------------------------ |
| 98 | // Primary data structure #1: CC table |
| 99 | // - Holds the per-source-line hit/miss stats, grouped by file/function/line. |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 100 | // - an ordered set of CCs. CC indexing done by file/function/line (as |
| 101 | // determined from the instrAddr). |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 102 | // - Traversed for dumping stats at end in file/func/line hierarchy. |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 103 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 104 | typedef struct { |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 105 | HChar* file; |
| 106 | HChar* fn; |
| 107 | Int line; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 108 | } |
| 109 | CodeLoc; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 110 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 111 | typedef struct { |
| 112 | CodeLoc loc; /* Source location that these counts pertain to */ |
| 113 | CacheCC Ir; /* Insn read counts */ |
| 114 | CacheCC Dr; /* Data read counts */ |
| 115 | CacheCC Dw; /* Data write/modify counts */ |
| 116 | BranchCC Bc; /* Conditional branch counts */ |
| 117 | BranchCC Bi; /* Indirect branch counts */ |
| 118 | } LineCC; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 119 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 120 | // First compare file, then fn, then line. |
tom | 5a835d5 | 2007-12-30 12:28:26 +0000 | [diff] [blame] | 121 | static Word cmp_CodeLoc_LineCC(const void *vloc, const void *vcc) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 122 | { |
njn | afa1226 | 2005-12-24 03:10:56 +0000 | [diff] [blame] | 123 | Word res; |
florian | 3e79863 | 2012-11-24 19:41:54 +0000 | [diff] [blame] | 124 | const CodeLoc* a = (const CodeLoc*)vloc; |
| 125 | const CodeLoc* b = &(((const LineCC*)vcc)->loc); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 126 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 127 | res = VG_(strcmp)(a->file, b->file); |
| 128 | if (0 != res) |
| 129 | return res; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 130 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 131 | res = VG_(strcmp)(a->fn, b->fn); |
| 132 | if (0 != res) |
| 133 | return res; |
| 134 | |
| 135 | return a->line - b->line; |
| 136 | } |
| 137 | |
| 138 | static OSet* CC_table; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 139 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 140 | //------------------------------------------------------------ |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 141 | // Primary data structure #2: InstrInfo table |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 142 | // - Holds the cached info about each instr that is used for simulation. |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 143 | // - table(SB_start_addr, list(InstrInfo)) |
| 144 | // - For each SB, each InstrInfo in the list holds info about the |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 145 | // instruction (instrLen, instrAddr, etc), plus a pointer to its line |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 146 | // CC. This node is what's passed to the simulation function. |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 147 | // - When SBs are discarded the relevant list(instr_details) is freed. |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 148 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 149 | typedef struct _InstrInfo InstrInfo; |
| 150 | struct _InstrInfo { |
nethercote | ca1f2dc | 2004-07-21 08:49:02 +0000 | [diff] [blame] | 151 | Addr instr_addr; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 152 | UChar instr_len; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 153 | LineCC* parent; // parent line-CC |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 154 | }; |
| 155 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 156 | typedef struct _SB_info SB_info; |
| 157 | struct _SB_info { |
| 158 | Addr SB_addr; // key; MUST BE FIRST |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 159 | Int n_instrs; |
| 160 | InstrInfo instrs[0]; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 161 | }; |
| 162 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 163 | static OSet* instrInfoTable; |
| 164 | |
| 165 | //------------------------------------------------------------ |
| 166 | // Secondary data structure: string table |
| 167 | // - holds strings, avoiding dups |
| 168 | // - used for filenames and function names, each of which will be |
| 169 | // pointed to by one or more CCs. |
| 170 | // - it also allows equality checks just by pointer comparison, which |
| 171 | // is good when printing the output file at the end. |
| 172 | |
| 173 | static OSet* stringTable; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 174 | |
| 175 | //------------------------------------------------------------ |
| 176 | // Stats |
sewardj | 4f29ddf | 2002-05-03 22:29:04 +0000 | [diff] [blame] | 177 | static Int distinct_files = 0; |
| 178 | static Int distinct_fns = 0; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 179 | static Int distinct_lines = 0; |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 180 | static Int distinct_instrsGen = 0; |
| 181 | static Int distinct_instrsNoX = 0; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 182 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 183 | static Int full_debugs = 0; |
| 184 | static Int file_line_debugs = 0; |
| 185 | static Int fn_debugs = 0; |
| 186 | static Int no_debugs = 0; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 187 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 188 | /*------------------------------------------------------------*/ |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 189 | /*--- String table operations ---*/ |
| 190 | /*------------------------------------------------------------*/ |
| 191 | |
tom | 5a835d5 | 2007-12-30 12:28:26 +0000 | [diff] [blame] | 192 | static Word stringCmp( const void* key, const void* elem ) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 193 | { |
florian | 3e79863 | 2012-11-24 19:41:54 +0000 | [diff] [blame] | 194 | return VG_(strcmp)(*(const HChar *const *)key, *(const HChar *const *)elem); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 195 | } |
| 196 | |
| 197 | // Get a permanent string; either pull it out of the string table if it's |
| 198 | // been encountered before, or dup it and put it into the string table. |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 199 | static HChar* get_perm_string(HChar* s) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 200 | { |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 201 | HChar** s_ptr = VG_(OSetGen_Lookup)(stringTable, &s); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 202 | if (s_ptr) { |
| 203 | return *s_ptr; |
| 204 | } else { |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 205 | HChar** s_node = VG_(OSetGen_AllocNode)(stringTable, sizeof(HChar*)); |
sewardj | 9c606bd | 2008-09-18 18:12:50 +0000 | [diff] [blame] | 206 | *s_node = VG_(strdup)("cg.main.gps.1", s); |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 207 | VG_(OSetGen_Insert)(stringTable, s_node); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 208 | return *s_node; |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | /*------------------------------------------------------------*/ |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 213 | /*--- CC table operations ---*/ |
| 214 | /*------------------------------------------------------------*/ |
njn | 4294fd4 | 2002-06-05 14:41:10 +0000 | [diff] [blame] | 215 | |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 216 | static void get_debug_info(Addr instr_addr, HChar file[FILE_LEN], |
| 217 | HChar fn[FN_LEN], UInt* line) |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 218 | { |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 219 | HChar dir[FILE_LEN]; |
njn | f3b61d6 | 2007-09-17 00:41:07 +0000 | [diff] [blame] | 220 | Bool found_dirname; |
sewardj | 7cee6f9 | 2005-06-13 17:39:06 +0000 | [diff] [blame] | 221 | Bool found_file_line = VG_(get_filename_linenum)( |
| 222 | instr_addr, |
| 223 | file, FILE_LEN, |
njn | f3b61d6 | 2007-09-17 00:41:07 +0000 | [diff] [blame] | 224 | dir, FILE_LEN, &found_dirname, |
sewardj | 7cee6f9 | 2005-06-13 17:39:06 +0000 | [diff] [blame] | 225 | line |
| 226 | ); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 227 | Bool found_fn = VG_(get_fnname)(instr_addr, fn, FN_LEN); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 228 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 229 | if (!found_file_line) { |
| 230 | VG_(strcpy)(file, "???"); |
| 231 | *line = 0; |
| 232 | } |
| 233 | if (!found_fn) { |
| 234 | VG_(strcpy)(fn, "???"); |
| 235 | } |
njn | f3b61d6 | 2007-09-17 00:41:07 +0000 | [diff] [blame] | 236 | |
| 237 | if (found_dirname) { |
| 238 | // +1 for the '/'. |
| 239 | tl_assert(VG_(strlen)(dir) + VG_(strlen)(file) + 1 < FILE_LEN); |
| 240 | VG_(strcat)(dir, "/"); // Append '/' |
| 241 | VG_(strcat)(dir, file); // Append file to dir |
| 242 | VG_(strcpy)(file, dir); // Move dir+file to file |
| 243 | } |
| 244 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 245 | if (found_file_line) { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 246 | if (found_fn) full_debugs++; |
| 247 | else file_line_debugs++; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 248 | } else { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 249 | if (found_fn) fn_debugs++; |
| 250 | else no_debugs++; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 251 | } |
| 252 | } |
| 253 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 254 | // Do a three step traversal: by file, then fn, then line. |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 255 | // Returns a pointer to the line CC, creates a new one if necessary. |
| 256 | static LineCC* get_lineCC(Addr origAddr) |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 257 | { |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 258 | HChar file[FILE_LEN], fn[FN_LEN]; |
| 259 | UInt line; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 260 | CodeLoc loc; |
| 261 | LineCC* lineCC; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 262 | |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 263 | get_debug_info(origAddr, file, fn, &line); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 264 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 265 | loc.file = file; |
| 266 | loc.fn = fn; |
| 267 | loc.line = line; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 268 | |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 269 | lineCC = VG_(OSetGen_Lookup)(CC_table, &loc); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 270 | if (!lineCC) { |
| 271 | // Allocate and zero a new node. |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 272 | lineCC = VG_(OSetGen_AllocNode)(CC_table, sizeof(LineCC)); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 273 | lineCC->loc.file = get_perm_string(loc.file); |
| 274 | lineCC->loc.fn = get_perm_string(loc.fn); |
| 275 | lineCC->loc.line = loc.line; |
njn | 0a8db5c | 2007-04-02 03:11:41 +0000 | [diff] [blame] | 276 | lineCC->Ir.a = 0; |
| 277 | lineCC->Ir.m1 = 0; |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 278 | lineCC->Ir.mL = 0; |
njn | 0a8db5c | 2007-04-02 03:11:41 +0000 | [diff] [blame] | 279 | lineCC->Dr.a = 0; |
| 280 | lineCC->Dr.m1 = 0; |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 281 | lineCC->Dr.mL = 0; |
njn | 0a8db5c | 2007-04-02 03:11:41 +0000 | [diff] [blame] | 282 | lineCC->Dw.a = 0; |
| 283 | lineCC->Dw.m1 = 0; |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 284 | lineCC->Dw.mL = 0; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 285 | lineCC->Bc.b = 0; |
| 286 | lineCC->Bc.mp = 0; |
| 287 | lineCC->Bi.b = 0; |
| 288 | lineCC->Bi.mp = 0; |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 289 | VG_(OSetGen_Insert)(CC_table, lineCC); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 290 | } |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 291 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 292 | return lineCC; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 293 | } |
| 294 | |
| 295 | /*------------------------------------------------------------*/ |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 296 | /*--- Cache simulation functions ---*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 297 | /*------------------------------------------------------------*/ |
| 298 | |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 299 | /* A common case for an instruction read event is that the |
| 300 | * bytes read belong to the same cache line in both L1I and LL |
| 301 | * (if cache line sizes of L1 and LL are the same). |
| 302 | * As this can be detected at instrumentation time, and results |
| 303 | * in faster simulation, special-casing is benefical. |
| 304 | * |
| 305 | * Abbrevations used in var/function names: |
| 306 | * IrNoX - instruction read does not cross cache lines |
| 307 | * IrGen - generic instruction read; not detected as IrNoX |
| 308 | * Ir - not known / not important whether it is an IrNoX |
| 309 | */ |
| 310 | |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 311 | // Only used with --cache-sim=no. |
| 312 | static VG_REGPARM(1) |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 313 | void log_1Ir(InstrInfo* n) |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 314 | { |
| 315 | n->parent->Ir.a++; |
| 316 | } |
| 317 | |
| 318 | // Only used with --cache-sim=no. |
| 319 | static VG_REGPARM(2) |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 320 | void log_2Ir(InstrInfo* n, InstrInfo* n2) |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 321 | { |
| 322 | n->parent->Ir.a++; |
| 323 | n2->parent->Ir.a++; |
| 324 | } |
| 325 | |
| 326 | // Only used with --cache-sim=no. |
| 327 | static VG_REGPARM(3) |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 328 | void log_3Ir(InstrInfo* n, InstrInfo* n2, InstrInfo* n3) |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 329 | { |
| 330 | n->parent->Ir.a++; |
| 331 | n2->parent->Ir.a++; |
| 332 | n3->parent->Ir.a++; |
| 333 | } |
| 334 | |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 335 | // Generic case for instruction reads: may cross cache lines. |
| 336 | // All other Ir handlers expect IrNoX instruction reads. |
njn | af839f5 | 2005-06-23 03:27:57 +0000 | [diff] [blame] | 337 | static VG_REGPARM(1) |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 338 | void log_1IrGen_0D_cache_access(InstrInfo* n) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 339 | { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 340 | //VG_(printf)("1IrGen_0D : CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n", |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 341 | // n, n->instr_addr, n->instr_len); |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 342 | cachesim_I1_doref_Gen(n->instr_addr, n->instr_len, |
| 343 | &n->parent->Ir.m1, &n->parent->Ir.mL); |
| 344 | n->parent->Ir.a++; |
| 345 | } |
| 346 | |
| 347 | static VG_REGPARM(1) |
| 348 | void log_1IrNoX_0D_cache_access(InstrInfo* n) |
| 349 | { |
| 350 | //VG_(printf)("1IrNoX_0D : CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n", |
| 351 | // n, n->instr_addr, n->instr_len); |
| 352 | cachesim_I1_doref_NoX(n->instr_addr, n->instr_len, |
| 353 | &n->parent->Ir.m1, &n->parent->Ir.mL); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 354 | n->parent->Ir.a++; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 355 | } |
| 356 | |
njn | af839f5 | 2005-06-23 03:27:57 +0000 | [diff] [blame] | 357 | static VG_REGPARM(2) |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 358 | void log_2IrNoX_0D_cache_access(InstrInfo* n, InstrInfo* n2) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 359 | { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 360 | //VG_(printf)("2IrNoX_0D : CC1addr=0x%010lx, i1addr=0x%010lx, i1size=%lu\n" |
| 361 | // " CC2addr=0x%010lx, i2addr=0x%010lx, i2size=%lu\n", |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 362 | // n, n->instr_addr, n->instr_len, |
| 363 | // n2, n2->instr_addr, n2->instr_len); |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 364 | cachesim_I1_doref_NoX(n->instr_addr, n->instr_len, |
| 365 | &n->parent->Ir.m1, &n->parent->Ir.mL); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 366 | n->parent->Ir.a++; |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 367 | cachesim_I1_doref_NoX(n2->instr_addr, n2->instr_len, |
| 368 | &n2->parent->Ir.m1, &n2->parent->Ir.mL); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 369 | n2->parent->Ir.a++; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 370 | } |
| 371 | |
| 372 | static VG_REGPARM(3) |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 373 | void log_3IrNoX_0D_cache_access(InstrInfo* n, InstrInfo* n2, InstrInfo* n3) |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 374 | { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 375 | //VG_(printf)("3IrNoX_0D : CC1addr=0x%010lx, i1addr=0x%010lx, i1size=%lu\n" |
| 376 | // " CC2addr=0x%010lx, i2addr=0x%010lx, i2size=%lu\n" |
| 377 | // " CC3addr=0x%010lx, i3addr=0x%010lx, i3size=%lu\n", |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 378 | // n, n->instr_addr, n->instr_len, |
| 379 | // n2, n2->instr_addr, n2->instr_len, |
| 380 | // n3, n3->instr_addr, n3->instr_len); |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 381 | cachesim_I1_doref_NoX(n->instr_addr, n->instr_len, |
| 382 | &n->parent->Ir.m1, &n->parent->Ir.mL); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 383 | n->parent->Ir.a++; |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 384 | cachesim_I1_doref_NoX(n2->instr_addr, n2->instr_len, |
| 385 | &n2->parent->Ir.m1, &n2->parent->Ir.mL); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 386 | n2->parent->Ir.a++; |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 387 | cachesim_I1_doref_NoX(n3->instr_addr, n3->instr_len, |
| 388 | &n3->parent->Ir.m1, &n3->parent->Ir.mL); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 389 | n3->parent->Ir.a++; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 390 | } |
| 391 | |
| 392 | static VG_REGPARM(3) |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 393 | void log_1IrNoX_1Dr_cache_access(InstrInfo* n, Addr data_addr, Word data_size) |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 394 | { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 395 | //VG_(printf)("1IrNoX_1Dr: CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n" |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 396 | // " daddr=0x%010lx, dsize=%lu\n", |
| 397 | // n, n->instr_addr, n->instr_len, data_addr, data_size); |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 398 | cachesim_I1_doref_NoX(n->instr_addr, n->instr_len, |
| 399 | &n->parent->Ir.m1, &n->parent->Ir.mL); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 400 | n->parent->Ir.a++; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 401 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 402 | cachesim_D1_doref(data_addr, data_size, |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 403 | &n->parent->Dr.m1, &n->parent->Dr.mL); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 404 | n->parent->Dr.a++; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 405 | } |
| 406 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 407 | static VG_REGPARM(3) |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 408 | void log_1IrNoX_1Dw_cache_access(InstrInfo* n, Addr data_addr, Word data_size) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 409 | { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 410 | //VG_(printf)("1IrNoX_1Dw: CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n" |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 411 | // " daddr=0x%010lx, dsize=%lu\n", |
| 412 | // n, n->instr_addr, n->instr_len, data_addr, data_size); |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 413 | cachesim_I1_doref_NoX(n->instr_addr, n->instr_len, |
| 414 | &n->parent->Ir.m1, &n->parent->Ir.mL); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 415 | n->parent->Ir.a++; |
| 416 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 417 | cachesim_D1_doref(data_addr, data_size, |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 418 | &n->parent->Dw.m1, &n->parent->Dw.mL); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 419 | n->parent->Dw.a++; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 420 | } |
| 421 | |
sewardj | cafe505 | 2013-01-17 14:24:35 +0000 | [diff] [blame] | 422 | /* Note that addEvent_D_guarded assumes that log_0Ir_1Dr_cache_access |
| 423 | and log_0Ir_1Dw_cache_access have exactly the same prototype. If |
| 424 | you change them, you must change addEvent_D_guarded too. */ |
njn | af839f5 | 2005-06-23 03:27:57 +0000 | [diff] [blame] | 425 | static VG_REGPARM(3) |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 426 | void log_0Ir_1Dr_cache_access(InstrInfo* n, Addr data_addr, Word data_size) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 427 | { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 428 | //VG_(printf)("0Ir_1Dr: CCaddr=0x%010lx, daddr=0x%010lx, dsize=%lu\n", |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 429 | // n, data_addr, data_size); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 430 | cachesim_D1_doref(data_addr, data_size, |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 431 | &n->parent->Dr.m1, &n->parent->Dr.mL); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 432 | n->parent->Dr.a++; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 433 | } |
| 434 | |
sewardj | cafe505 | 2013-01-17 14:24:35 +0000 | [diff] [blame] | 435 | /* See comment on log_0Ir_1Dr_cache_access. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 436 | static VG_REGPARM(3) |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 437 | void log_0Ir_1Dw_cache_access(InstrInfo* n, Addr data_addr, Word data_size) |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 438 | { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 439 | //VG_(printf)("0Ir_1Dw: CCaddr=0x%010lx, daddr=0x%010lx, dsize=%lu\n", |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 440 | // n, data_addr, data_size); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 441 | cachesim_D1_doref(data_addr, data_size, |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 442 | &n->parent->Dw.m1, &n->parent->Dw.mL); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 443 | n->parent->Dw.a++; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 444 | } |
| 445 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 446 | /* For branches, we consult two different predictors, one which |
| 447 | predicts taken/untaken for conditional branches, and the other |
| 448 | which predicts the branch target address for indirect branches |
| 449 | (jump-to-register style ones). */ |
| 450 | |
| 451 | static VG_REGPARM(2) |
| 452 | void log_cond_branch(InstrInfo* n, Word taken) |
| 453 | { |
| 454 | //VG_(printf)("cbrnch: CCaddr=0x%010lx, taken=0x%010lx\n", |
| 455 | // n, taken); |
| 456 | n->parent->Bc.b++; |
| 457 | n->parent->Bc.mp |
| 458 | += (1 & do_cond_branch_predict(n->instr_addr, taken)); |
| 459 | } |
| 460 | |
| 461 | static VG_REGPARM(2) |
| 462 | void log_ind_branch(InstrInfo* n, UWord actual_dst) |
| 463 | { |
| 464 | //VG_(printf)("ibrnch: CCaddr=0x%010lx, dst=0x%010lx\n", |
| 465 | // n, actual_dst); |
| 466 | n->parent->Bi.b++; |
| 467 | n->parent->Bi.mp |
| 468 | += (1 & do_ind_branch_predict(n->instr_addr, actual_dst)); |
| 469 | } |
| 470 | |
| 471 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 472 | /*------------------------------------------------------------*/ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 473 | /*--- Instrumentation types and structures ---*/ |
| 474 | /*------------------------------------------------------------*/ |
| 475 | |
| 476 | /* Maintain an ordered list of memory events which are outstanding, in |
| 477 | the sense that no IR has yet been generated to do the relevant |
| 478 | helper calls. The BB is scanned top to bottom and memory events |
| 479 | are added to the end of the list, merging with the most recent |
| 480 | notified event where possible (Dw immediately following Dr and |
| 481 | having the same size and EA can be merged). |
| 482 | |
| 483 | This merging is done so that for architectures which have |
| 484 | load-op-store instructions (x86, amd64), the insn is treated as if |
| 485 | it makes just one memory reference (a modify), rather than two (a |
| 486 | read followed by a write at the same address). |
| 487 | |
| 488 | At various points the list will need to be flushed, that is, IR |
| 489 | generated from it. That must happen before any possible exit from |
| 490 | the block (the end, or an IRStmt_Exit). Flushing also takes place |
| 491 | when there is no space to add a new event. |
| 492 | |
| 493 | If we require the simulation statistics to be up to date with |
| 494 | respect to possible memory exceptions, then the list would have to |
| 495 | be flushed before each memory reference. That would however lose |
| 496 | performance by inhibiting event-merging during flushing. |
| 497 | |
| 498 | Flushing the list consists of walking it start to end and emitting |
| 499 | instrumentation IR for each event, in the order in which they |
| 500 | appear. It may be possible to emit a single call for two adjacent |
| 501 | events in order to reduce the number of helper function calls made. |
| 502 | For example, it could well be profitable to handle two adjacent Ir |
| 503 | events with a single helper call. */ |
| 504 | |
| 505 | typedef |
| 506 | IRExpr |
| 507 | IRAtom; |
| 508 | |
| 509 | typedef |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 510 | enum { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 511 | Ev_IrNoX, // Instruction read not crossing cache lines |
| 512 | Ev_IrGen, // Generic Ir, not being detected as IrNoX |
| 513 | Ev_Dr, // Data read |
| 514 | Ev_Dw, // Data write |
| 515 | Ev_Dm, // Data modify (read then write) |
| 516 | Ev_Bc, // branch conditional |
| 517 | Ev_Bi // branch indirect (to unknown destination) |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 518 | } |
| 519 | EventTag; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 520 | |
| 521 | typedef |
| 522 | struct { |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 523 | EventTag tag; |
| 524 | InstrInfo* inode; |
| 525 | union { |
| 526 | struct { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 527 | } IrGen; |
| 528 | struct { |
| 529 | } IrNoX; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 530 | struct { |
| 531 | IRAtom* ea; |
| 532 | Int szB; |
| 533 | } Dr; |
| 534 | struct { |
| 535 | IRAtom* ea; |
| 536 | Int szB; |
| 537 | } Dw; |
| 538 | struct { |
| 539 | IRAtom* ea; |
| 540 | Int szB; |
| 541 | } Dm; |
| 542 | struct { |
| 543 | IRAtom* taken; /* :: Ity_I1 */ |
| 544 | } Bc; |
| 545 | struct { |
| 546 | IRAtom* dst; |
| 547 | } Bi; |
| 548 | } Ev; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 549 | } |
| 550 | Event; |
| 551 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 552 | static void init_Event ( Event* ev ) { |
| 553 | VG_(memset)(ev, 0, sizeof(Event)); |
| 554 | } |
| 555 | |
| 556 | static IRAtom* get_Event_dea ( Event* ev ) { |
| 557 | switch (ev->tag) { |
| 558 | case Ev_Dr: return ev->Ev.Dr.ea; |
| 559 | case Ev_Dw: return ev->Ev.Dw.ea; |
| 560 | case Ev_Dm: return ev->Ev.Dm.ea; |
| 561 | default: tl_assert(0); |
| 562 | } |
| 563 | } |
| 564 | |
| 565 | static Int get_Event_dszB ( Event* ev ) { |
| 566 | switch (ev->tag) { |
| 567 | case Ev_Dr: return ev->Ev.Dr.szB; |
| 568 | case Ev_Dw: return ev->Ev.Dw.szB; |
| 569 | case Ev_Dm: return ev->Ev.Dm.szB; |
| 570 | default: tl_assert(0); |
| 571 | } |
| 572 | } |
| 573 | |
| 574 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 575 | /* Up to this many unnotified events are allowed. Number is |
| 576 | arbitrary. Larger numbers allow more event merging to occur, but |
| 577 | potentially induce more spilling due to extending live ranges of |
| 578 | address temporaries. */ |
| 579 | #define N_EVENTS 16 |
| 580 | |
| 581 | |
| 582 | /* A struct which holds all the running state during instrumentation. |
| 583 | Mostly to avoid passing loads of parameters everywhere. */ |
| 584 | typedef |
| 585 | struct { |
| 586 | /* The current outstanding-memory-event list. */ |
| 587 | Event events[N_EVENTS]; |
| 588 | Int events_used; |
| 589 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 590 | /* The array of InstrInfo bins for the BB. */ |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 591 | SB_info* sbInfo; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 592 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 593 | /* Number InstrInfo bins 'used' so far. */ |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 594 | Int sbInfo_i; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 595 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 596 | /* The output SB being constructed. */ |
| 597 | IRSB* sbOut; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 598 | } |
| 599 | CgState; |
| 600 | |
| 601 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 602 | /*------------------------------------------------------------*/ |
| 603 | /*--- Instrumentation main ---*/ |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 604 | /*------------------------------------------------------------*/ |
| 605 | |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 606 | // Note that origAddr is the real origAddr, not the address of the first |
| 607 | // instruction in the block (they can be different due to redirection). |
nethercote | 564b2b0 | 2004-08-07 15:54:53 +0000 | [diff] [blame] | 608 | static |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 609 | SB_info* get_SB_info(IRSB* sbIn, Addr origAddr) |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 610 | { |
njn | 4bd67b5 | 2005-08-11 00:47:10 +0000 | [diff] [blame] | 611 | Int i, n_instrs; |
| 612 | IRStmt* st; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 613 | SB_info* sbInfo; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 614 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 615 | // Count number of original instrs in SB |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 616 | n_instrs = 0; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 617 | for (i = 0; i < sbIn->stmts_used; i++) { |
| 618 | st = sbIn->stmts[i]; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 619 | if (Ist_IMark == st->tag) n_instrs++; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 620 | } |
| 621 | |
njn | f7d2609 | 2005-10-12 16:45:17 +0000 | [diff] [blame] | 622 | // Check that we don't have an entry for this BB in the instr-info table. |
| 623 | // If this assertion fails, there has been some screwup: some |
| 624 | // translations must have been discarded but Cachegrind hasn't discarded |
| 625 | // the corresponding entries in the instr-info table. |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 626 | sbInfo = VG_(OSetGen_Lookup)(instrInfoTable, &origAddr); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 627 | tl_assert(NULL == sbInfo); |
sewardj | a3a29a5 | 2005-10-12 16:16:03 +0000 | [diff] [blame] | 628 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 629 | // BB never translated before (at this address, at least; could have |
| 630 | // been unloaded and then reloaded elsewhere in memory) |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 631 | sbInfo = VG_(OSetGen_AllocNode)(instrInfoTable, |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 632 | sizeof(SB_info) + n_instrs*sizeof(InstrInfo)); |
| 633 | sbInfo->SB_addr = origAddr; |
| 634 | sbInfo->n_instrs = n_instrs; |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 635 | VG_(OSetGen_Insert)( instrInfoTable, sbInfo ); |
sewardj | a3a29a5 | 2005-10-12 16:16:03 +0000 | [diff] [blame] | 636 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 637 | return sbInfo; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 638 | } |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 639 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 640 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 641 | static void showEvent ( Event* ev ) |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 642 | { |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 643 | switch (ev->tag) { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 644 | case Ev_IrGen: |
| 645 | VG_(printf)("IrGen %p\n", ev->inode); |
| 646 | break; |
| 647 | case Ev_IrNoX: |
| 648 | VG_(printf)("IrNoX %p\n", ev->inode); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 649 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 650 | case Ev_Dr: |
| 651 | VG_(printf)("Dr %p %d EA=", ev->inode, ev->Ev.Dr.szB); |
| 652 | ppIRExpr(ev->Ev.Dr.ea); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 653 | VG_(printf)("\n"); |
| 654 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 655 | case Ev_Dw: |
| 656 | VG_(printf)("Dw %p %d EA=", ev->inode, ev->Ev.Dw.szB); |
| 657 | ppIRExpr(ev->Ev.Dw.ea); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 658 | VG_(printf)("\n"); |
| 659 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 660 | case Ev_Dm: |
| 661 | VG_(printf)("Dm %p %d EA=", ev->inode, ev->Ev.Dm.szB); |
| 662 | ppIRExpr(ev->Ev.Dm.ea); |
| 663 | VG_(printf)("\n"); |
| 664 | break; |
| 665 | case Ev_Bc: |
| 666 | VG_(printf)("Bc %p GA=", ev->inode); |
| 667 | ppIRExpr(ev->Ev.Bc.taken); |
| 668 | VG_(printf)("\n"); |
| 669 | break; |
| 670 | case Ev_Bi: |
| 671 | VG_(printf)("Bi %p DST=", ev->inode); |
| 672 | ppIRExpr(ev->Ev.Bi.dst); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 673 | VG_(printf)("\n"); |
| 674 | break; |
| 675 | default: |
| 676 | tl_assert(0); |
| 677 | break; |
| 678 | } |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 679 | } |
| 680 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 681 | // Reserve and initialise an InstrInfo for the first mention of a new insn. |
| 682 | static |
| 683 | InstrInfo* setup_InstrInfo ( CgState* cgs, Addr instr_addr, UInt instr_len ) |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 684 | { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 685 | InstrInfo* i_node; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 686 | tl_assert(cgs->sbInfo_i >= 0); |
| 687 | tl_assert(cgs->sbInfo_i < cgs->sbInfo->n_instrs); |
| 688 | i_node = &cgs->sbInfo->instrs[ cgs->sbInfo_i ]; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 689 | i_node->instr_addr = instr_addr; |
| 690 | i_node->instr_len = instr_len; |
| 691 | i_node->parent = get_lineCC(instr_addr); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 692 | cgs->sbInfo_i++; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 693 | return i_node; |
| 694 | } |
sewardj | 17a56bf | 2005-03-21 01:35:02 +0000 | [diff] [blame] | 695 | |
sewardj | 17a56bf | 2005-03-21 01:35:02 +0000 | [diff] [blame] | 696 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 697 | /* Generate code for all outstanding memory events, and mark the queue |
| 698 | empty. Code is generated into cgs->bbOut, and this activity |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 699 | 'consumes' slots in cgs->sbInfo. */ |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 700 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 701 | static void flushEvents ( CgState* cgs ) |
| 702 | { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 703 | Int i, regparms; |
florian | ee90c8a | 2012-10-21 02:39:42 +0000 | [diff] [blame] | 704 | const HChar* helperName; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 705 | void* helperAddr; |
| 706 | IRExpr** argv; |
| 707 | IRExpr* i_node_expr; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 708 | IRDirty* di; |
njn | c285dca | 2005-10-15 22:07:28 +0000 | [diff] [blame] | 709 | Event* ev; |
| 710 | Event* ev2; |
| 711 | Event* ev3; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 712 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 713 | i = 0; |
| 714 | while (i < cgs->events_used) { |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 715 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 716 | helperName = NULL; |
| 717 | helperAddr = NULL; |
| 718 | argv = NULL; |
| 719 | regparms = 0; |
| 720 | |
| 721 | /* generate IR to notify event i and possibly the ones |
| 722 | immediately following it. */ |
| 723 | tl_assert(i >= 0 && i < cgs->events_used); |
njn | c285dca | 2005-10-15 22:07:28 +0000 | [diff] [blame] | 724 | |
| 725 | ev = &cgs->events[i]; |
| 726 | ev2 = ( i < cgs->events_used-1 ? &cgs->events[i+1] : NULL ); |
| 727 | ev3 = ( i < cgs->events_used-2 ? &cgs->events[i+2] : NULL ); |
| 728 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 729 | if (DEBUG_CG) { |
| 730 | VG_(printf)(" flush "); |
njn | c285dca | 2005-10-15 22:07:28 +0000 | [diff] [blame] | 731 | showEvent( ev ); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 732 | } |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 733 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 734 | i_node_expr = mkIRExpr_HWord( (HWord)ev->inode ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 735 | |
| 736 | /* Decide on helper fn to call and args to pass it, and advance |
| 737 | i appropriately. */ |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 738 | switch (ev->tag) { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 739 | case Ev_IrNoX: |
| 740 | /* Merge an IrNoX with a following Dr/Dm. */ |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 741 | if (ev2 && (ev2->tag == Ev_Dr || ev2->tag == Ev_Dm)) { |
| 742 | /* Why is this true? It's because we're merging an Ir |
| 743 | with a following Dr or Dm. The Ir derives from the |
| 744 | instruction's IMark and the Dr/Dm from data |
| 745 | references which follow it. In short it holds |
| 746 | because each insn starts with an IMark, hence an |
| 747 | Ev_Ir, and so these Dr/Dm must pertain to the |
| 748 | immediately preceding Ir. Same applies to analogous |
| 749 | assertions in the subsequent cases. */ |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 750 | tl_assert(ev2->inode == ev->inode); |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 751 | helperName = "log_1IrNoX_1Dr_cache_access"; |
| 752 | helperAddr = &log_1IrNoX_1Dr_cache_access; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 753 | argv = mkIRExprVec_3( i_node_expr, |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 754 | get_Event_dea(ev2), |
| 755 | mkIRExpr_HWord( get_Event_dszB(ev2) ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 756 | regparms = 3; |
| 757 | i += 2; |
| 758 | } |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 759 | /* Merge an IrNoX with a following Dw. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 760 | else |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 761 | if (ev2 && ev2->tag == Ev_Dw) { |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 762 | tl_assert(ev2->inode == ev->inode); |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 763 | helperName = "log_1IrNoX_1Dw_cache_access"; |
| 764 | helperAddr = &log_1IrNoX_1Dw_cache_access; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 765 | argv = mkIRExprVec_3( i_node_expr, |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 766 | get_Event_dea(ev2), |
| 767 | mkIRExpr_HWord( get_Event_dszB(ev2) ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 768 | regparms = 3; |
| 769 | i += 2; |
| 770 | } |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 771 | /* Merge an IrNoX with two following IrNoX's. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 772 | else |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 773 | if (ev2 && ev3 && ev2->tag == Ev_IrNoX && ev3->tag == Ev_IrNoX) |
njn | c285dca | 2005-10-15 22:07:28 +0000 | [diff] [blame] | 774 | { |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 775 | if (clo_cache_sim) { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 776 | helperName = "log_3IrNoX_0D_cache_access"; |
| 777 | helperAddr = &log_3IrNoX_0D_cache_access; |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 778 | } else { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 779 | helperName = "log_3Ir"; |
| 780 | helperAddr = &log_3Ir; |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 781 | } |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 782 | argv = mkIRExprVec_3( i_node_expr, |
| 783 | mkIRExpr_HWord( (HWord)ev2->inode ), |
| 784 | mkIRExpr_HWord( (HWord)ev3->inode ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 785 | regparms = 3; |
| 786 | i += 3; |
| 787 | } |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 788 | /* Merge an IrNoX with one following IrNoX. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 789 | else |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 790 | if (ev2 && ev2->tag == Ev_IrNoX) { |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 791 | if (clo_cache_sim) { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 792 | helperName = "log_2IrNoX_0D_cache_access"; |
| 793 | helperAddr = &log_2IrNoX_0D_cache_access; |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 794 | } else { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 795 | helperName = "log_2Ir"; |
| 796 | helperAddr = &log_2Ir; |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 797 | } |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 798 | argv = mkIRExprVec_2( i_node_expr, |
| 799 | mkIRExpr_HWord( (HWord)ev2->inode ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 800 | regparms = 2; |
| 801 | i += 2; |
| 802 | } |
| 803 | /* No merging possible; emit as-is. */ |
| 804 | else { |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 805 | if (clo_cache_sim) { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 806 | helperName = "log_1IrNoX_0D_cache_access"; |
| 807 | helperAddr = &log_1IrNoX_0D_cache_access; |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 808 | } else { |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 809 | helperName = "log_1Ir"; |
| 810 | helperAddr = &log_1Ir; |
njn | c52b932 | 2010-09-27 02:20:38 +0000 | [diff] [blame] | 811 | } |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 812 | argv = mkIRExprVec_1( i_node_expr ); |
| 813 | regparms = 1; |
| 814 | i++; |
| 815 | } |
| 816 | break; |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 817 | case Ev_IrGen: |
| 818 | if (clo_cache_sim) { |
| 819 | helperName = "log_1IrGen_0D_cache_access"; |
| 820 | helperAddr = &log_1IrGen_0D_cache_access; |
| 821 | } else { |
| 822 | helperName = "log_1Ir"; |
| 823 | helperAddr = &log_1Ir; |
| 824 | } |
| 825 | argv = mkIRExprVec_1( i_node_expr ); |
| 826 | regparms = 1; |
| 827 | i++; |
| 828 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 829 | case Ev_Dr: |
| 830 | case Ev_Dm: |
| 831 | /* Data read or modify */ |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 832 | helperName = "log_0Ir_1Dr_cache_access"; |
| 833 | helperAddr = &log_0Ir_1Dr_cache_access; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 834 | argv = mkIRExprVec_3( i_node_expr, |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 835 | get_Event_dea(ev), |
| 836 | mkIRExpr_HWord( get_Event_dszB(ev) ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 837 | regparms = 3; |
| 838 | i++; |
| 839 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 840 | case Ev_Dw: |
| 841 | /* Data write */ |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 842 | helperName = "log_0Ir_1Dw_cache_access"; |
| 843 | helperAddr = &log_0Ir_1Dw_cache_access; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 844 | argv = mkIRExprVec_3( i_node_expr, |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 845 | get_Event_dea(ev), |
| 846 | mkIRExpr_HWord( get_Event_dszB(ev) ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 847 | regparms = 3; |
| 848 | i++; |
| 849 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 850 | case Ev_Bc: |
| 851 | /* Conditional branch */ |
| 852 | helperName = "log_cond_branch"; |
| 853 | helperAddr = &log_cond_branch; |
| 854 | argv = mkIRExprVec_2( i_node_expr, ev->Ev.Bc.taken ); |
| 855 | regparms = 2; |
| 856 | i++; |
| 857 | break; |
| 858 | case Ev_Bi: |
| 859 | /* Branch to an unknown destination */ |
| 860 | helperName = "log_ind_branch"; |
| 861 | helperAddr = &log_ind_branch; |
| 862 | argv = mkIRExprVec_2( i_node_expr, ev->Ev.Bi.dst ); |
| 863 | regparms = 2; |
| 864 | i++; |
| 865 | break; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 866 | default: |
| 867 | tl_assert(0); |
| 868 | } |
| 869 | |
| 870 | /* Add the helper. */ |
| 871 | tl_assert(helperName); |
| 872 | tl_assert(helperAddr); |
| 873 | tl_assert(argv); |
sewardj | 5bb8682 | 2005-12-23 12:47:42 +0000 | [diff] [blame] | 874 | di = unsafeIRDirty_0_N( regparms, |
| 875 | helperName, VG_(fnptr_to_fnentry)( helperAddr ), |
| 876 | argv ); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 877 | addStmtToIRSB( cgs->sbOut, IRStmt_Dirty(di) ); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 878 | } |
| 879 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 880 | cgs->events_used = 0; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 881 | } |
njn | 14d01ce | 2004-11-26 11:30:14 +0000 | [diff] [blame] | 882 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 883 | static void addEvent_Ir ( CgState* cgs, InstrInfo* inode ) |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 884 | { |
| 885 | Event* evt; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 886 | if (cgs->events_used == N_EVENTS) |
| 887 | flushEvents(cgs); |
| 888 | tl_assert(cgs->events_used >= 0 && cgs->events_used < N_EVENTS); |
| 889 | evt = &cgs->events[cgs->events_used]; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 890 | init_Event(evt); |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 891 | evt->inode = inode; |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 892 | if (cachesim_is_IrNoX(inode->instr_addr, inode->instr_len)) { |
| 893 | evt->tag = Ev_IrNoX; |
| 894 | distinct_instrsNoX++; |
| 895 | } else { |
| 896 | evt->tag = Ev_IrGen; |
| 897 | distinct_instrsGen++; |
| 898 | } |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 899 | cgs->events_used++; |
| 900 | } |
| 901 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 902 | static |
| 903 | void addEvent_Dr ( CgState* cgs, InstrInfo* inode, Int datasize, IRAtom* ea ) |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 904 | { |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 905 | Event* evt; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 906 | tl_assert(isIRAtom(ea)); |
sewardj | 98763d5 | 2012-06-03 22:40:07 +0000 | [diff] [blame] | 907 | tl_assert(datasize >= 1 && datasize <= min_line_size); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 908 | if (!clo_cache_sim) |
| 909 | return; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 910 | if (cgs->events_used == N_EVENTS) |
| 911 | flushEvents(cgs); |
| 912 | tl_assert(cgs->events_used >= 0 && cgs->events_used < N_EVENTS); |
| 913 | evt = &cgs->events[cgs->events_used]; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 914 | init_Event(evt); |
| 915 | evt->tag = Ev_Dr; |
| 916 | evt->inode = inode; |
| 917 | evt->Ev.Dr.szB = datasize; |
| 918 | evt->Ev.Dr.ea = ea; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 919 | cgs->events_used++; |
| 920 | } |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 921 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 922 | static |
| 923 | void addEvent_Dw ( CgState* cgs, InstrInfo* inode, Int datasize, IRAtom* ea ) |
| 924 | { |
| 925 | Event* lastEvt; |
| 926 | Event* evt; |
| 927 | |
| 928 | tl_assert(isIRAtom(ea)); |
sewardj | 98763d5 | 2012-06-03 22:40:07 +0000 | [diff] [blame] | 929 | tl_assert(datasize >= 1 && datasize <= min_line_size); |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 930 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 931 | if (!clo_cache_sim) |
| 932 | return; |
| 933 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 934 | /* Is it possible to merge this write with the preceding read? */ |
| 935 | lastEvt = &cgs->events[cgs->events_used-1]; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 936 | if (cgs->events_used > 0 |
sewardj | cafe505 | 2013-01-17 14:24:35 +0000 | [diff] [blame] | 937 | && lastEvt->tag == Ev_Dr |
| 938 | && lastEvt->Ev.Dr.szB == datasize |
| 939 | && lastEvt->inode == inode |
| 940 | && eqIRAtom(lastEvt->Ev.Dr.ea, ea)) |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 941 | { |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 942 | lastEvt->tag = Ev_Dm; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 943 | return; |
| 944 | } |
| 945 | |
| 946 | /* No. Add as normal. */ |
| 947 | if (cgs->events_used == N_EVENTS) |
| 948 | flushEvents(cgs); |
| 949 | tl_assert(cgs->events_used >= 0 && cgs->events_used < N_EVENTS); |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 950 | evt = &cgs->events[cgs->events_used]; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 951 | init_Event(evt); |
| 952 | evt->tag = Ev_Dw; |
| 953 | evt->inode = inode; |
| 954 | evt->Ev.Dw.szB = datasize; |
| 955 | evt->Ev.Dw.ea = ea; |
| 956 | cgs->events_used++; |
| 957 | } |
| 958 | |
| 959 | static |
sewardj | cafe505 | 2013-01-17 14:24:35 +0000 | [diff] [blame] | 960 | void addEvent_D_guarded ( CgState* cgs, InstrInfo* inode, |
| 961 | Int datasize, IRAtom* ea, IRAtom* guard, |
| 962 | Bool isWrite ) |
| 963 | { |
| 964 | tl_assert(isIRAtom(ea)); |
| 965 | tl_assert(guard); |
| 966 | tl_assert(isIRAtom(guard)); |
| 967 | tl_assert(datasize >= 1 && datasize <= min_line_size); |
| 968 | |
| 969 | if (!clo_cache_sim) |
| 970 | return; |
| 971 | |
| 972 | /* Adding guarded memory actions and merging them with the existing |
| 973 | queue is too complex. Simply flush the queue and add this |
| 974 | action immediately. Since guarded loads and stores are pretty |
| 975 | rare, this is not thought likely to cause any noticeable |
| 976 | performance loss as a result of the loss of event-merging |
| 977 | opportunities. */ |
| 978 | tl_assert(cgs->events_used >= 0); |
| 979 | flushEvents(cgs); |
| 980 | tl_assert(cgs->events_used == 0); |
| 981 | /* Same as case Ev_Dw / case Ev_Dr in flushEvents, except with guard */ |
| 982 | IRExpr* i_node_expr; |
| 983 | const HChar* helperName; |
| 984 | void* helperAddr; |
| 985 | IRExpr** argv; |
| 986 | Int regparms; |
| 987 | IRDirty* di; |
| 988 | i_node_expr = mkIRExpr_HWord( (HWord)inode ); |
| 989 | helperName = isWrite ? "log_0Ir_1Dw_cache_access" |
| 990 | : "log_0Ir_1Dr_cache_access"; |
| 991 | helperAddr = isWrite ? &log_0Ir_1Dw_cache_access |
| 992 | : &log_0Ir_1Dr_cache_access; |
| 993 | argv = mkIRExprVec_3( i_node_expr, |
| 994 | ea, mkIRExpr_HWord( datasize ) ); |
| 995 | regparms = 3; |
| 996 | di = unsafeIRDirty_0_N( |
| 997 | regparms, |
| 998 | helperName, VG_(fnptr_to_fnentry)( helperAddr ), |
| 999 | argv ); |
| 1000 | di->guard = guard; |
| 1001 | addStmtToIRSB( cgs->sbOut, IRStmt_Dirty(di) ); |
| 1002 | } |
| 1003 | |
| 1004 | |
| 1005 | static |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1006 | void addEvent_Bc ( CgState* cgs, InstrInfo* inode, IRAtom* guard ) |
| 1007 | { |
| 1008 | Event* evt; |
| 1009 | tl_assert(isIRAtom(guard)); |
| 1010 | tl_assert(typeOfIRExpr(cgs->sbOut->tyenv, guard) |
| 1011 | == (sizeof(HWord)==4 ? Ity_I32 : Ity_I64)); |
| 1012 | if (!clo_branch_sim) |
| 1013 | return; |
| 1014 | if (cgs->events_used == N_EVENTS) |
| 1015 | flushEvents(cgs); |
| 1016 | tl_assert(cgs->events_used >= 0 && cgs->events_used < N_EVENTS); |
| 1017 | evt = &cgs->events[cgs->events_used]; |
| 1018 | init_Event(evt); |
| 1019 | evt->tag = Ev_Bc; |
| 1020 | evt->inode = inode; |
| 1021 | evt->Ev.Bc.taken = guard; |
| 1022 | cgs->events_used++; |
| 1023 | } |
| 1024 | |
| 1025 | static |
| 1026 | void addEvent_Bi ( CgState* cgs, InstrInfo* inode, IRAtom* whereTo ) |
| 1027 | { |
| 1028 | Event* evt; |
| 1029 | tl_assert(isIRAtom(whereTo)); |
| 1030 | tl_assert(typeOfIRExpr(cgs->sbOut->tyenv, whereTo) |
| 1031 | == (sizeof(HWord)==4 ? Ity_I32 : Ity_I64)); |
| 1032 | if (!clo_branch_sim) |
| 1033 | return; |
| 1034 | if (cgs->events_used == N_EVENTS) |
| 1035 | flushEvents(cgs); |
| 1036 | tl_assert(cgs->events_used >= 0 && cgs->events_used < N_EVENTS); |
| 1037 | evt = &cgs->events[cgs->events_used]; |
| 1038 | init_Event(evt); |
| 1039 | evt->tag = Ev_Bi; |
| 1040 | evt->inode = inode; |
| 1041 | evt->Ev.Bi.dst = whereTo; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1042 | cgs->events_used++; |
| 1043 | } |
| 1044 | |
| 1045 | //////////////////////////////////////////////////////////// |
| 1046 | |
| 1047 | |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 1048 | static |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1049 | IRSB* cg_instrument ( VgCallbackClosure* closure, |
| 1050 | IRSB* sbIn, |
sewardj | 461df9c | 2006-01-17 02:06:39 +0000 | [diff] [blame] | 1051 | VexGuestLayout* layout, |
| 1052 | VexGuestExtents* vge, |
florian | ca503be | 2012-10-07 21:59:42 +0000 | [diff] [blame] | 1053 | VexArchInfo* archinfo_host, |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 1054 | IRType gWordTy, IRType hWordTy ) |
njn | 14d01ce | 2004-11-26 11:30:14 +0000 | [diff] [blame] | 1055 | { |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1056 | Int i, isize; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1057 | IRStmt* st; |
| 1058 | Addr64 cia; /* address of current insn */ |
| 1059 | CgState cgs; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1060 | IRTypeEnv* tyenv = sbIn->tyenv; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1061 | InstrInfo* curr_inode = NULL; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1062 | |
sewardj | d54babf | 2005-03-21 00:55:49 +0000 | [diff] [blame] | 1063 | if (gWordTy != hWordTy) { |
| 1064 | /* We don't currently support this case. */ |
| 1065 | VG_(tool_panic)("host/guest word size mismatch"); |
| 1066 | } |
| 1067 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1068 | // Set up new SB |
| 1069 | cgs.sbOut = deepCopyIRSBExceptStmts(sbIn); |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1070 | |
sewardj | a9f538c | 2005-10-23 12:06:55 +0000 | [diff] [blame] | 1071 | // Copy verbatim any IR preamble preceding the first IMark |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1072 | i = 0; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1073 | while (i < sbIn->stmts_used && sbIn->stmts[i]->tag != Ist_IMark) { |
| 1074 | addStmtToIRSB( cgs.sbOut, sbIn->stmts[i] ); |
sewardj | a9f538c | 2005-10-23 12:06:55 +0000 | [diff] [blame] | 1075 | i++; |
| 1076 | } |
| 1077 | |
| 1078 | // Get the first statement, and initial cia from it |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1079 | tl_assert(sbIn->stmts_used > 0); |
| 1080 | tl_assert(i < sbIn->stmts_used); |
| 1081 | st = sbIn->stmts[i]; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1082 | tl_assert(Ist_IMark == st->tag); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1083 | |
| 1084 | cia = st->Ist.IMark.addr; |
| 1085 | isize = st->Ist.IMark.len; |
| 1086 | // If Vex fails to decode an instruction, the size will be zero. |
| 1087 | // Pretend otherwise. |
| 1088 | if (isize == 0) isize = VG_MIN_INSTR_SZB; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1089 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1090 | // Set up running state and get block info |
sewardj | 3a384b3 | 2006-01-22 01:12:51 +0000 | [diff] [blame] | 1091 | tl_assert(closure->readdr == vge->base[0]); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1092 | cgs.events_used = 0; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1093 | cgs.sbInfo = get_SB_info(sbIn, (Addr)closure->readdr); |
| 1094 | cgs.sbInfo_i = 0; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1095 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1096 | if (DEBUG_CG) |
| 1097 | VG_(printf)("\n\n---------- cg_instrument ----------\n"); |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1098 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1099 | // Traverse the block, initialising inodes, adding events and flushing as |
| 1100 | // necessary. |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1101 | for (/*use current i*/; i < sbIn->stmts_used; i++) { |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1102 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1103 | st = sbIn->stmts[i]; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1104 | tl_assert(isFlatIRStmt(st)); |
njn | b3507ea | 2005-08-02 23:07:02 +0000 | [diff] [blame] | 1105 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1106 | switch (st->tag) { |
| 1107 | case Ist_NoOp: |
| 1108 | case Ist_AbiHint: |
| 1109 | case Ist_Put: |
| 1110 | case Ist_PutI: |
sewardj | 72d7513 | 2007-11-09 23:06:35 +0000 | [diff] [blame] | 1111 | case Ist_MBE: |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1112 | break; |
njn | 20677cc | 2005-08-12 23:47:51 +0000 | [diff] [blame] | 1113 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1114 | case Ist_IMark: |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1115 | cia = st->Ist.IMark.addr; |
| 1116 | isize = st->Ist.IMark.len; |
| 1117 | |
| 1118 | // If Vex fails to decode an instruction, the size will be zero. |
| 1119 | // Pretend otherwise. |
| 1120 | if (isize == 0) isize = VG_MIN_INSTR_SZB; |
| 1121 | |
njn | a5ad9ba | 2005-11-10 15:20:37 +0000 | [diff] [blame] | 1122 | // Sanity-check size. |
| 1123 | tl_assert( (VG_MIN_INSTR_SZB <= isize && isize <= VG_MAX_INSTR_SZB) |
| 1124 | || VG_CLREQ_SZB == isize ); |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1125 | |
| 1126 | // Get space for and init the inode, record it as the current one. |
| 1127 | // Subsequent Dr/Dw/Dm events from the same instruction will |
| 1128 | // also use it. |
| 1129 | curr_inode = setup_InstrInfo(&cgs, cia, isize); |
| 1130 | |
| 1131 | addEvent_Ir( &cgs, curr_inode ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1132 | break; |
| 1133 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1134 | case Ist_WrTmp: { |
| 1135 | IRExpr* data = st->Ist.WrTmp.data; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1136 | if (data->tag == Iex_Load) { |
| 1137 | IRExpr* aexpr = data->Iex.Load.addr; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1138 | // Note also, endianness info is ignored. I guess |
| 1139 | // that's not interesting. |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1140 | addEvent_Dr( &cgs, curr_inode, sizeofIRType(data->Iex.Load.ty), |
| 1141 | aexpr ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1142 | } |
| 1143 | break; |
njn | b3507ea | 2005-08-02 23:07:02 +0000 | [diff] [blame] | 1144 | } |
| 1145 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1146 | case Ist_Store: { |
| 1147 | IRExpr* data = st->Ist.Store.data; |
| 1148 | IRExpr* aexpr = st->Ist.Store.addr; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1149 | addEvent_Dw( &cgs, curr_inode, |
| 1150 | sizeofIRType(typeOfIRExpr(tyenv, data)), aexpr ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1151 | break; |
| 1152 | } |
njn | b3507ea | 2005-08-02 23:07:02 +0000 | [diff] [blame] | 1153 | |
sewardj | cafe505 | 2013-01-17 14:24:35 +0000 | [diff] [blame] | 1154 | case Ist_StoreG: { |
| 1155 | IRStoreG* sg = st->Ist.StoreG.details; |
| 1156 | IRExpr* data = sg->data; |
| 1157 | IRExpr* addr = sg->addr; |
| 1158 | IRType type = typeOfIRExpr(tyenv, data); |
| 1159 | tl_assert(type != Ity_INVALID); |
| 1160 | addEvent_D_guarded( &cgs, curr_inode, |
| 1161 | sizeofIRType(type), addr, sg->guard, |
| 1162 | True/*isWrite*/ ); |
| 1163 | break; |
| 1164 | } |
| 1165 | |
| 1166 | case Ist_LoadG: { |
| 1167 | IRLoadG* lg = st->Ist.LoadG.details; |
| 1168 | IRType type = Ity_INVALID; /* loaded type */ |
| 1169 | IRType typeWide = Ity_INVALID; /* after implicit widening */ |
| 1170 | IRExpr* addr = lg->addr; |
| 1171 | typeOfIRLoadGOp(lg->cvt, &typeWide, &type); |
| 1172 | tl_assert(type != Ity_INVALID); |
| 1173 | addEvent_D_guarded( &cgs, curr_inode, |
| 1174 | sizeofIRType(type), addr, lg->guard, |
| 1175 | False/*!isWrite*/ ); |
| 1176 | break; |
| 1177 | } |
| 1178 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1179 | case Ist_Dirty: { |
| 1180 | Int dataSize; |
| 1181 | IRDirty* d = st->Ist.Dirty.details; |
| 1182 | if (d->mFx != Ifx_None) { |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1183 | /* This dirty helper accesses memory. Collect the details. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1184 | tl_assert(d->mAddr != NULL); |
| 1185 | tl_assert(d->mSize != 0); |
| 1186 | dataSize = d->mSize; |
| 1187 | // Large (eg. 28B, 108B, 512B on x86) data-sized |
| 1188 | // instructions will be done inaccurately, but they're |
| 1189 | // very rare and this avoids errors from hitting more |
| 1190 | // than two cache lines in the simulation. |
sewardj | 98763d5 | 2012-06-03 22:40:07 +0000 | [diff] [blame] | 1191 | if (dataSize > min_line_size) |
| 1192 | dataSize = min_line_size; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1193 | if (d->mFx == Ifx_Read || d->mFx == Ifx_Modify) |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1194 | addEvent_Dr( &cgs, curr_inode, dataSize, d->mAddr ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1195 | if (d->mFx == Ifx_Write || d->mFx == Ifx_Modify) |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1196 | addEvent_Dw( &cgs, curr_inode, dataSize, d->mAddr ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1197 | } else { |
| 1198 | tl_assert(d->mAddr == NULL); |
| 1199 | tl_assert(d->mSize == 0); |
| 1200 | } |
| 1201 | break; |
| 1202 | } |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1203 | |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 1204 | case Ist_CAS: { |
| 1205 | /* We treat it as a read and a write of the location. I |
| 1206 | think that is the same behaviour as it was before IRCAS |
| 1207 | was introduced, since prior to that point, the Vex |
| 1208 | front ends would translate a lock-prefixed instruction |
| 1209 | into a (normal) read followed by a (normal) write. */ |
| 1210 | Int dataSize; |
| 1211 | IRCAS* cas = st->Ist.CAS.details; |
| 1212 | tl_assert(cas->addr != NULL); |
| 1213 | tl_assert(cas->dataLo != NULL); |
| 1214 | dataSize = sizeofIRType(typeOfIRExpr(tyenv, cas->dataLo)); |
| 1215 | if (cas->dataHi != NULL) |
| 1216 | dataSize *= 2; /* since it's a doubleword-CAS */ |
| 1217 | /* I don't think this can ever happen, but play safe. */ |
sewardj | 98763d5 | 2012-06-03 22:40:07 +0000 | [diff] [blame] | 1218 | if (dataSize > min_line_size) |
| 1219 | dataSize = min_line_size; |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 1220 | addEvent_Dr( &cgs, curr_inode, dataSize, cas->addr ); |
| 1221 | addEvent_Dw( &cgs, curr_inode, dataSize, cas->addr ); |
| 1222 | break; |
| 1223 | } |
| 1224 | |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 1225 | case Ist_LLSC: { |
| 1226 | IRType dataTy; |
| 1227 | if (st->Ist.LLSC.storedata == NULL) { |
| 1228 | /* LL */ |
| 1229 | dataTy = typeOfIRTemp(tyenv, st->Ist.LLSC.result); |
| 1230 | addEvent_Dr( &cgs, curr_inode, |
| 1231 | sizeofIRType(dataTy), st->Ist.LLSC.addr ); |
weidendo | d405332 | 2012-11-26 18:16:58 +0000 | [diff] [blame] | 1232 | /* flush events before LL, should help SC to succeed */ |
| 1233 | flushEvents( &cgs ); |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 1234 | } else { |
| 1235 | /* SC */ |
| 1236 | dataTy = typeOfIRExpr(tyenv, st->Ist.LLSC.storedata); |
| 1237 | addEvent_Dw( &cgs, curr_inode, |
| 1238 | sizeofIRType(dataTy), st->Ist.LLSC.addr ); |
| 1239 | } |
| 1240 | break; |
| 1241 | } |
| 1242 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1243 | case Ist_Exit: { |
weidendo | 374a48f | 2010-09-02 17:06:49 +0000 | [diff] [blame] | 1244 | // call branch predictor only if this is a branch in guest code |
| 1245 | if ( (st->Ist.Exit.jk == Ijk_Boring) || |
| 1246 | (st->Ist.Exit.jk == Ijk_Call) || |
| 1247 | (st->Ist.Exit.jk == Ijk_Ret) ) |
| 1248 | { |
| 1249 | /* Stuff to widen the guard expression to a host word, so |
| 1250 | we can pass it to the branch predictor simulation |
| 1251 | functions easily. */ |
| 1252 | Bool inverted; |
| 1253 | Addr64 nia, sea; |
| 1254 | IRConst* dst; |
| 1255 | IRType tyW = hWordTy; |
| 1256 | IROp widen = tyW==Ity_I32 ? Iop_1Uto32 : Iop_1Uto64; |
| 1257 | IROp opXOR = tyW==Ity_I32 ? Iop_Xor32 : Iop_Xor64; |
| 1258 | IRTemp guard1 = newIRTemp(cgs.sbOut->tyenv, Ity_I1); |
| 1259 | IRTemp guardW = newIRTemp(cgs.sbOut->tyenv, tyW); |
| 1260 | IRTemp guard = newIRTemp(cgs.sbOut->tyenv, tyW); |
| 1261 | IRExpr* one = tyW==Ity_I32 ? IRExpr_Const(IRConst_U32(1)) |
| 1262 | : IRExpr_Const(IRConst_U64(1)); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1263 | |
weidendo | 374a48f | 2010-09-02 17:06:49 +0000 | [diff] [blame] | 1264 | /* First we need to figure out whether the side exit got |
| 1265 | inverted by the ir optimiser. To do that, figure out |
| 1266 | the next (fallthrough) instruction's address and the |
| 1267 | side exit address and see if they are the same. */ |
| 1268 | nia = cia + (Addr64)isize; |
| 1269 | if (tyW == Ity_I32) |
| 1270 | nia &= 0xFFFFFFFFULL; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1271 | |
weidendo | 374a48f | 2010-09-02 17:06:49 +0000 | [diff] [blame] | 1272 | /* Side exit address */ |
| 1273 | dst = st->Ist.Exit.dst; |
| 1274 | if (tyW == Ity_I32) { |
| 1275 | tl_assert(dst->tag == Ico_U32); |
| 1276 | sea = (Addr64)(UInt)dst->Ico.U32; |
| 1277 | } else { |
| 1278 | tl_assert(tyW == Ity_I64); |
| 1279 | tl_assert(dst->tag == Ico_U64); |
| 1280 | sea = dst->Ico.U64; |
| 1281 | } |
| 1282 | |
| 1283 | inverted = nia == sea; |
| 1284 | |
| 1285 | /* Widen the guard expression. */ |
| 1286 | addStmtToIRSB( cgs.sbOut, |
| 1287 | IRStmt_WrTmp( guard1, st->Ist.Exit.guard )); |
| 1288 | addStmtToIRSB( cgs.sbOut, |
| 1289 | IRStmt_WrTmp( guardW, |
| 1290 | IRExpr_Unop(widen, |
| 1291 | IRExpr_RdTmp(guard1))) ); |
| 1292 | /* If the exit is inverted, invert the sense of the guard. */ |
| 1293 | addStmtToIRSB( |
| 1294 | cgs.sbOut, |
| 1295 | IRStmt_WrTmp( |
| 1296 | guard, |
| 1297 | inverted ? IRExpr_Binop(opXOR, IRExpr_RdTmp(guardW), one) |
| 1298 | : IRExpr_RdTmp(guardW) |
| 1299 | )); |
| 1300 | /* And post the event. */ |
| 1301 | addEvent_Bc( &cgs, curr_inode, IRExpr_RdTmp(guard) ); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1302 | } |
| 1303 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1304 | /* We may never reach the next statement, so need to flush |
| 1305 | all outstanding transactions now. */ |
| 1306 | flushEvents( &cgs ); |
| 1307 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1308 | } |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1309 | |
| 1310 | default: |
sewardj | cafe505 | 2013-01-17 14:24:35 +0000 | [diff] [blame] | 1311 | ppIRStmt(st); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1312 | tl_assert(0); |
| 1313 | break; |
njn | b3507ea | 2005-08-02 23:07:02 +0000 | [diff] [blame] | 1314 | } |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1315 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1316 | /* Copy the original statement */ |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1317 | addStmtToIRSB( cgs.sbOut, st ); |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1318 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1319 | if (DEBUG_CG) { |
| 1320 | ppIRStmt(st); |
| 1321 | VG_(printf)("\n"); |
| 1322 | } |
| 1323 | } |
| 1324 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1325 | /* Deal with branches to unknown destinations. Except ignore ones |
| 1326 | which are function returns as we assume the return stack |
| 1327 | predictor never mispredicts. */ |
weidendo | 374a48f | 2010-09-02 17:06:49 +0000 | [diff] [blame] | 1328 | if ((sbIn->jumpkind == Ijk_Boring) || (sbIn->jumpkind == Ijk_Call)) { |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1329 | if (0) { ppIRExpr( sbIn->next ); VG_(printf)("\n"); } |
| 1330 | switch (sbIn->next->tag) { |
| 1331 | case Iex_Const: |
| 1332 | break; /* boring - branch to known address */ |
| 1333 | case Iex_RdTmp: |
| 1334 | /* looks like an indirect branch (branch to unknown) */ |
| 1335 | addEvent_Bi( &cgs, curr_inode, sbIn->next ); |
| 1336 | break; |
| 1337 | default: |
| 1338 | /* shouldn't happen - if the incoming IR is properly |
| 1339 | flattened, should only have tmp and const cases to |
| 1340 | consider. */ |
| 1341 | tl_assert(0); |
| 1342 | } |
| 1343 | } |
| 1344 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1345 | /* At the end of the bb. Flush outstandings. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1346 | flushEvents( &cgs ); |
| 1347 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1348 | /* done. stay sane ... */ |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1349 | tl_assert(cgs.sbInfo_i == cgs.sbInfo->n_instrs); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1350 | |
| 1351 | if (DEBUG_CG) { |
| 1352 | VG_(printf)( "goto {"); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1353 | ppIRJumpKind(sbIn->jumpkind); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1354 | VG_(printf)( "} "); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1355 | ppIRExpr( sbIn->next ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1356 | VG_(printf)( "}\n"); |
| 1357 | } |
| 1358 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1359 | return cgs.sbOut; |
njn | 14d01ce | 2004-11-26 11:30:14 +0000 | [diff] [blame] | 1360 | } |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1361 | |
| 1362 | /*------------------------------------------------------------*/ |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 1363 | /*--- Cache configuration ---*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1364 | /*------------------------------------------------------------*/ |
| 1365 | |
sewardj | b5f6f51 | 2005-03-10 23:59:00 +0000 | [diff] [blame] | 1366 | #define UNDEFINED_CACHE { -1, -1, -1 } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1367 | |
| 1368 | static cache_t clo_I1_cache = UNDEFINED_CACHE; |
| 1369 | static cache_t clo_D1_cache = UNDEFINED_CACHE; |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1370 | static cache_t clo_LL_cache = UNDEFINED_CACHE; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1371 | |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1372 | /*------------------------------------------------------------*/ |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1373 | /*--- cg_fini() and related function ---*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1374 | /*------------------------------------------------------------*/ |
| 1375 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1376 | // Total reads/writes/misses. Calculated during CC traversal at the end. |
| 1377 | // All auto-zeroed. |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1378 | static CacheCC Ir_total; |
| 1379 | static CacheCC Dr_total; |
| 1380 | static CacheCC Dw_total; |
| 1381 | static BranchCC Bc_total; |
| 1382 | static BranchCC Bi_total; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1383 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1384 | static void fprint_CC_table_and_calc_totals(void) |
| 1385 | { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1386 | Int i, fd; |
sewardj | 9264559 | 2005-07-23 09:18:34 +0000 | [diff] [blame] | 1387 | SysRes sres; |
florian | dbb3584 | 2012-10-27 18:39:11 +0000 | [diff] [blame] | 1388 | HChar buf[512]; |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 1389 | HChar *currFile = NULL, *currFn = NULL; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1390 | LineCC* lineCC; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1391 | |
njn | 7064fb2 | 2008-05-29 23:09:52 +0000 | [diff] [blame] | 1392 | // Setup output filename. Nb: it's important to do this now, ie. as late |
| 1393 | // as possible. If we do it at start-up and the program forks and the |
| 1394 | // output file format string contains a %p (pid) specifier, both the |
| 1395 | // parent and child will incorrectly write to the same file; this |
| 1396 | // happened in 3.3.0. |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 1397 | HChar* cachegrind_out_file = |
njn | 7064fb2 | 2008-05-29 23:09:52 +0000 | [diff] [blame] | 1398 | VG_(expand_file_name)("--cachegrind-out-file", clo_cachegrind_out_file); |
| 1399 | |
sewardj | 9264559 | 2005-07-23 09:18:34 +0000 | [diff] [blame] | 1400 | sres = VG_(open)(cachegrind_out_file, VKI_O_CREAT|VKI_O_TRUNC|VKI_O_WRONLY, |
| 1401 | VKI_S_IRUSR|VKI_S_IWUSR); |
njn | cda2f0f | 2009-05-18 02:12:08 +0000 | [diff] [blame] | 1402 | if (sr_isError(sres)) { |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1403 | // If the file can't be opened for whatever reason (conflict |
| 1404 | // between multiple cachegrinded processes?), give up now. |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1405 | VG_(umsg)("error: can't open cache simulation output file '%s'\n", |
| 1406 | cachegrind_out_file ); |
| 1407 | VG_(umsg)(" ... so simulation results will be missing.\n"); |
njn | 7064fb2 | 2008-05-29 23:09:52 +0000 | [diff] [blame] | 1408 | VG_(free)(cachegrind_out_file); |
sewardj | 0744b6c | 2002-12-11 00:45:42 +0000 | [diff] [blame] | 1409 | return; |
sewardj | 9264559 | 2005-07-23 09:18:34 +0000 | [diff] [blame] | 1410 | } else { |
njn | cda2f0f | 2009-05-18 02:12:08 +0000 | [diff] [blame] | 1411 | fd = sr_Res(sres); |
njn | 7064fb2 | 2008-05-29 23:09:52 +0000 | [diff] [blame] | 1412 | VG_(free)(cachegrind_out_file); |
sewardj | 0744b6c | 2002-12-11 00:45:42 +0000 | [diff] [blame] | 1413 | } |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1414 | |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1415 | // "desc:" lines (giving I1/D1/LL cache configuration). The spaces after |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1416 | // the 2nd colon makes cg_annotate's output look nicer. |
| 1417 | VG_(sprintf)(buf, "desc: I1 cache: %s\n" |
| 1418 | "desc: D1 cache: %s\n" |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1419 | "desc: LL cache: %s\n", |
| 1420 | I1.desc_line, D1.desc_line, LL.desc_line); |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1421 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1422 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1423 | // "cmd:" line |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1424 | VG_(strcpy)(buf, "cmd:"); |
| 1425 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
sewardj | 45f4e7c | 2005-09-27 19:20:21 +0000 | [diff] [blame] | 1426 | if (VG_(args_the_exename)) { |
| 1427 | VG_(write)(fd, " ", 1); |
| 1428 | VG_(write)(fd, VG_(args_the_exename), |
| 1429 | VG_(strlen)( VG_(args_the_exename) )); |
| 1430 | } |
sewardj | 14c7cc5 | 2007-02-25 15:08:24 +0000 | [diff] [blame] | 1431 | for (i = 0; i < VG_(sizeXA)( VG_(args_for_client) ); i++) { |
| 1432 | HChar* arg = * (HChar**) VG_(indexXA)( VG_(args_for_client), i ); |
| 1433 | if (arg) { |
sewardj | 45f4e7c | 2005-09-27 19:20:21 +0000 | [diff] [blame] | 1434 | VG_(write)(fd, " ", 1); |
sewardj | 14c7cc5 | 2007-02-25 15:08:24 +0000 | [diff] [blame] | 1435 | VG_(write)(fd, arg, VG_(strlen)( arg )); |
sewardj | 45f4e7c | 2005-09-27 19:20:21 +0000 | [diff] [blame] | 1436 | } |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1437 | } |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1438 | // "events:" line |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1439 | if (clo_cache_sim && clo_branch_sim) { |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1440 | VG_(sprintf)(buf, "\nevents: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw " |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1441 | "Bc Bcm Bi Bim\n"); |
| 1442 | } |
| 1443 | else if (clo_cache_sim && !clo_branch_sim) { |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1444 | VG_(sprintf)(buf, "\nevents: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw " |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1445 | "\n"); |
| 1446 | } |
| 1447 | else if (!clo_cache_sim && clo_branch_sim) { |
| 1448 | VG_(sprintf)(buf, "\nevents: Ir " |
| 1449 | "Bc Bcm Bi Bim\n"); |
| 1450 | } |
njn | e90711c | 2010-09-27 01:04:20 +0000 | [diff] [blame] | 1451 | else { |
| 1452 | VG_(sprintf)(buf, "\nevents: Ir\n"); |
| 1453 | } |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1454 | |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1455 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
| 1456 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1457 | // Traverse every lineCC |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1458 | VG_(OSetGen_ResetIter)(CC_table); |
| 1459 | while ( (lineCC = VG_(OSetGen_Next)(CC_table)) ) { |
njn | 4311fe6 | 2005-12-08 23:18:50 +0000 | [diff] [blame] | 1460 | Bool just_hit_a_new_file = False; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1461 | // If we've hit a new file, print a "fl=" line. Note that because |
| 1462 | // each string is stored exactly once in the string table, we can use |
| 1463 | // pointer comparison rather than strcmp() to test for equality, which |
| 1464 | // is good because most of the time the comparisons are equal and so |
njn | 4311fe6 | 2005-12-08 23:18:50 +0000 | [diff] [blame] | 1465 | // the whole strings would have to be checked. |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1466 | if ( lineCC->loc.file != currFile ) { |
| 1467 | currFile = lineCC->loc.file; |
| 1468 | VG_(sprintf)(buf, "fl=%s\n", currFile); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1469 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1470 | distinct_files++; |
njn | 4311fe6 | 2005-12-08 23:18:50 +0000 | [diff] [blame] | 1471 | just_hit_a_new_file = True; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1472 | } |
njn | 4311fe6 | 2005-12-08 23:18:50 +0000 | [diff] [blame] | 1473 | // If we've hit a new function, print a "fn=" line. We know to do |
| 1474 | // this when the function name changes, and also every time we hit a |
| 1475 | // new file (in which case the new function name might be the same as |
| 1476 | // in the old file, hence the just_hit_a_new_file test). |
| 1477 | if ( just_hit_a_new_file || lineCC->loc.fn != currFn ) { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1478 | currFn = lineCC->loc.fn; |
| 1479 | VG_(sprintf)(buf, "fn=%s\n", currFn); |
| 1480 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
| 1481 | distinct_fns++; |
| 1482 | } |
| 1483 | |
| 1484 | // Print the LineCC |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1485 | if (clo_cache_sim && clo_branch_sim) { |
| 1486 | VG_(sprintf)(buf, "%u %llu %llu %llu" |
| 1487 | " %llu %llu %llu" |
| 1488 | " %llu %llu %llu" |
| 1489 | " %llu %llu %llu %llu\n", |
| 1490 | lineCC->loc.line, |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1491 | lineCC->Ir.a, lineCC->Ir.m1, lineCC->Ir.mL, |
| 1492 | lineCC->Dr.a, lineCC->Dr.m1, lineCC->Dr.mL, |
| 1493 | lineCC->Dw.a, lineCC->Dw.m1, lineCC->Dw.mL, |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1494 | lineCC->Bc.b, lineCC->Bc.mp, |
| 1495 | lineCC->Bi.b, lineCC->Bi.mp); |
| 1496 | } |
| 1497 | else if (clo_cache_sim && !clo_branch_sim) { |
| 1498 | VG_(sprintf)(buf, "%u %llu %llu %llu" |
| 1499 | " %llu %llu %llu" |
| 1500 | " %llu %llu %llu\n", |
| 1501 | lineCC->loc.line, |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1502 | lineCC->Ir.a, lineCC->Ir.m1, lineCC->Ir.mL, |
| 1503 | lineCC->Dr.a, lineCC->Dr.m1, lineCC->Dr.mL, |
| 1504 | lineCC->Dw.a, lineCC->Dw.m1, lineCC->Dw.mL); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1505 | } |
| 1506 | else if (!clo_cache_sim && clo_branch_sim) { |
| 1507 | VG_(sprintf)(buf, "%u %llu" |
| 1508 | " %llu %llu %llu %llu\n", |
| 1509 | lineCC->loc.line, |
| 1510 | lineCC->Ir.a, |
| 1511 | lineCC->Bc.b, lineCC->Bc.mp, |
| 1512 | lineCC->Bi.b, lineCC->Bi.mp); |
| 1513 | } |
njn | e90711c | 2010-09-27 01:04:20 +0000 | [diff] [blame] | 1514 | else { |
| 1515 | VG_(sprintf)(buf, "%u %llu\n", |
| 1516 | lineCC->loc.line, |
| 1517 | lineCC->Ir.a); |
| 1518 | } |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1519 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1520 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
| 1521 | |
| 1522 | // Update summary stats |
| 1523 | Ir_total.a += lineCC->Ir.a; |
| 1524 | Ir_total.m1 += lineCC->Ir.m1; |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1525 | Ir_total.mL += lineCC->Ir.mL; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1526 | Dr_total.a += lineCC->Dr.a; |
| 1527 | Dr_total.m1 += lineCC->Dr.m1; |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1528 | Dr_total.mL += lineCC->Dr.mL; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1529 | Dw_total.a += lineCC->Dw.a; |
| 1530 | Dw_total.m1 += lineCC->Dw.m1; |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1531 | Dw_total.mL += lineCC->Dw.mL; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1532 | Bc_total.b += lineCC->Bc.b; |
| 1533 | Bc_total.mp += lineCC->Bc.mp; |
| 1534 | Bi_total.b += lineCC->Bi.b; |
| 1535 | Bi_total.mp += lineCC->Bi.mp; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1536 | |
| 1537 | distinct_lines++; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1538 | } |
| 1539 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1540 | // Summary stats must come after rest of table, since we calculate them |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1541 | // during traversal. */ |
| 1542 | if (clo_cache_sim && clo_branch_sim) { |
| 1543 | VG_(sprintf)(buf, "summary:" |
| 1544 | " %llu %llu %llu" |
| 1545 | " %llu %llu %llu" |
| 1546 | " %llu %llu %llu" |
| 1547 | " %llu %llu %llu %llu\n", |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1548 | Ir_total.a, Ir_total.m1, Ir_total.mL, |
| 1549 | Dr_total.a, Dr_total.m1, Dr_total.mL, |
| 1550 | Dw_total.a, Dw_total.m1, Dw_total.mL, |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1551 | Bc_total.b, Bc_total.mp, |
| 1552 | Bi_total.b, Bi_total.mp); |
| 1553 | } |
| 1554 | else if (clo_cache_sim && !clo_branch_sim) { |
| 1555 | VG_(sprintf)(buf, "summary:" |
| 1556 | " %llu %llu %llu" |
| 1557 | " %llu %llu %llu" |
| 1558 | " %llu %llu %llu\n", |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1559 | Ir_total.a, Ir_total.m1, Ir_total.mL, |
| 1560 | Dr_total.a, Dr_total.m1, Dr_total.mL, |
| 1561 | Dw_total.a, Dw_total.m1, Dw_total.mL); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1562 | } |
| 1563 | else if (!clo_cache_sim && clo_branch_sim) { |
| 1564 | VG_(sprintf)(buf, "summary:" |
| 1565 | " %llu" |
| 1566 | " %llu %llu %llu %llu\n", |
| 1567 | Ir_total.a, |
| 1568 | Bc_total.b, Bc_total.mp, |
| 1569 | Bi_total.b, Bi_total.mp); |
| 1570 | } |
njn | e90711c | 2010-09-27 01:04:20 +0000 | [diff] [blame] | 1571 | else { |
| 1572 | VG_(sprintf)(buf, "summary:" |
| 1573 | " %llu\n", |
| 1574 | Ir_total.a); |
| 1575 | } |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1576 | |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1577 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
| 1578 | VG_(close)(fd); |
| 1579 | } |
| 1580 | |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1581 | static UInt ULong_width(ULong n) |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1582 | { |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1583 | UInt w = 0; |
| 1584 | while (n > 0) { |
| 1585 | n = n / 10; |
| 1586 | w++; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1587 | } |
sewardj | 46c59b1 | 2005-11-01 02:20:19 +0000 | [diff] [blame] | 1588 | if (w == 0) w = 1; |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1589 | return w + (w-1)/3; // add space for commas |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1590 | } |
| 1591 | |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1592 | static void cg_fini(Int exitcode) |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1593 | { |
florian | dbb3584 | 2012-10-27 18:39:11 +0000 | [diff] [blame] | 1594 | static HChar buf1[128], buf2[128], buf3[128], buf4[123]; |
florian | ee90c8a | 2012-10-21 02:39:42 +0000 | [diff] [blame] | 1595 | static HChar fmt[128]; |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1596 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1597 | CacheCC D_total; |
| 1598 | BranchCC B_total; |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1599 | ULong LL_total_m, LL_total_mr, LL_total_mw, |
| 1600 | LL_total, LL_total_r, LL_total_w; |
njn | 4c245e5 | 2009-03-15 23:25:38 +0000 | [diff] [blame] | 1601 | Int l1, l2, l3; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1602 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1603 | fprint_CC_table_and_calc_totals(); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1604 | |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1605 | if (VG_(clo_verbosity) == 0) |
| 1606 | return; |
| 1607 | |
njn | f76d27a | 2009-05-28 01:53:07 +0000 | [diff] [blame] | 1608 | // Nb: this isn't called "MAX" because that overshadows a global on Darwin. |
| 1609 | #define CG_MAX(a, b) ((a) >= (b) ? (a) : (b)) |
njn | 4c245e5 | 2009-03-15 23:25:38 +0000 | [diff] [blame] | 1610 | |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1611 | /* I cache results. Use the I_refs value to determine the first column |
| 1612 | * width. */ |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1613 | l1 = ULong_width(Ir_total.a); |
njn | f76d27a | 2009-05-28 01:53:07 +0000 | [diff] [blame] | 1614 | l2 = ULong_width(CG_MAX(Dr_total.a, Bc_total.b)); |
| 1615 | l3 = ULong_width(CG_MAX(Dw_total.a, Bi_total.b)); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1616 | |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1617 | /* Make format string, getting width right for numbers */ |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1618 | VG_(sprintf)(fmt, "%%s %%,%dllu\n", l1); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1619 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1620 | /* Always print this */ |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1621 | VG_(umsg)(fmt, "I refs: ", Ir_total.a); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1622 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1623 | /* If cache profiling is enabled, show D access numbers and all |
| 1624 | miss numbers */ |
| 1625 | if (clo_cache_sim) { |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1626 | VG_(umsg)(fmt, "I1 misses: ", Ir_total.m1); |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1627 | VG_(umsg)(fmt, "LLi misses: ", Ir_total.mL); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1628 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1629 | if (0 == Ir_total.a) Ir_total.a = 1; |
| 1630 | VG_(percentify)(Ir_total.m1, Ir_total.a, 2, l1+1, buf1); |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1631 | VG_(umsg)("I1 miss rate: %s\n", buf1); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1632 | |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1633 | VG_(percentify)(Ir_total.mL, Ir_total.a, 2, l1+1, buf1); |
| 1634 | VG_(umsg)("LLi miss rate: %s\n", buf1); |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1635 | VG_(umsg)("\n"); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1636 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1637 | /* D cache results. Use the D_refs.rd and D_refs.wr values to |
| 1638 | * determine the width of columns 2 & 3. */ |
| 1639 | D_total.a = Dr_total.a + Dw_total.a; |
| 1640 | D_total.m1 = Dr_total.m1 + Dw_total.m1; |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1641 | D_total.mL = Dr_total.mL + Dw_total.mL; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1642 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1643 | /* Make format string, getting width right for numbers */ |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1644 | VG_(sprintf)(fmt, "%%s %%,%dllu (%%,%dllu rd + %%,%dllu wr)\n", |
| 1645 | l1, l2, l3); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1646 | |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1647 | VG_(umsg)(fmt, "D refs: ", |
| 1648 | D_total.a, Dr_total.a, Dw_total.a); |
| 1649 | VG_(umsg)(fmt, "D1 misses: ", |
| 1650 | D_total.m1, Dr_total.m1, Dw_total.m1); |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1651 | VG_(umsg)(fmt, "LLd misses: ", |
| 1652 | D_total.mL, Dr_total.mL, Dw_total.mL); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1653 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1654 | if (0 == D_total.a) D_total.a = 1; |
| 1655 | if (0 == Dr_total.a) Dr_total.a = 1; |
| 1656 | if (0 == Dw_total.a) Dw_total.a = 1; |
| 1657 | VG_(percentify)( D_total.m1, D_total.a, 1, l1+1, buf1); |
| 1658 | VG_(percentify)(Dr_total.m1, Dr_total.a, 1, l2+1, buf2); |
| 1659 | VG_(percentify)(Dw_total.m1, Dw_total.a, 1, l3+1, buf3); |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1660 | VG_(umsg)("D1 miss rate: %s (%s + %s )\n", buf1, buf2,buf3); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1661 | |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1662 | VG_(percentify)( D_total.mL, D_total.a, 1, l1+1, buf1); |
| 1663 | VG_(percentify)(Dr_total.mL, Dr_total.a, 1, l2+1, buf2); |
| 1664 | VG_(percentify)(Dw_total.mL, Dw_total.a, 1, l3+1, buf3); |
| 1665 | VG_(umsg)("LLd miss rate: %s (%s + %s )\n", buf1, buf2,buf3); |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1666 | VG_(umsg)("\n"); |
njn | 1d021fa | 2002-05-02 13:56:34 +0000 | [diff] [blame] | 1667 | |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1668 | /* LL overall results */ |
njn | 1d021fa | 2002-05-02 13:56:34 +0000 | [diff] [blame] | 1669 | |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1670 | LL_total = Dr_total.m1 + Dw_total.m1 + Ir_total.m1; |
| 1671 | LL_total_r = Dr_total.m1 + Ir_total.m1; |
| 1672 | LL_total_w = Dw_total.m1; |
| 1673 | VG_(umsg)(fmt, "LL refs: ", |
| 1674 | LL_total, LL_total_r, LL_total_w); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1675 | |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1676 | LL_total_m = Dr_total.mL + Dw_total.mL + Ir_total.mL; |
| 1677 | LL_total_mr = Dr_total.mL + Ir_total.mL; |
| 1678 | LL_total_mw = Dw_total.mL; |
| 1679 | VG_(umsg)(fmt, "LL misses: ", |
| 1680 | LL_total_m, LL_total_mr, LL_total_mw); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1681 | |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1682 | VG_(percentify)(LL_total_m, (Ir_total.a + D_total.a), 1, l1+1, buf1); |
| 1683 | VG_(percentify)(LL_total_mr, (Ir_total.a + Dr_total.a), 1, l2+1, buf2); |
| 1684 | VG_(percentify)(LL_total_mw, Dw_total.a, 1, l3+1, buf3); |
| 1685 | VG_(umsg)("LL miss rate: %s (%s + %s )\n", buf1, buf2,buf3); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1686 | } |
| 1687 | |
| 1688 | /* If branch profiling is enabled, show branch overall results. */ |
| 1689 | if (clo_branch_sim) { |
| 1690 | /* Make format string, getting width right for numbers */ |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1691 | VG_(sprintf)(fmt, "%%s %%,%dllu (%%,%dllu cond + %%,%dllu ind)\n", |
| 1692 | l1, l2, l3); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1693 | |
| 1694 | if (0 == Bc_total.b) Bc_total.b = 1; |
| 1695 | if (0 == Bi_total.b) Bi_total.b = 1; |
| 1696 | B_total.b = Bc_total.b + Bi_total.b; |
| 1697 | B_total.mp = Bc_total.mp + Bi_total.mp; |
| 1698 | |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1699 | VG_(umsg)("\n"); |
| 1700 | VG_(umsg)(fmt, "Branches: ", |
| 1701 | B_total.b, Bc_total.b, Bi_total.b); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1702 | |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1703 | VG_(umsg)(fmt, "Mispredicts: ", |
| 1704 | B_total.mp, Bc_total.mp, Bi_total.mp); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1705 | |
| 1706 | VG_(percentify)(B_total.mp, B_total.b, 1, l1+1, buf1); |
| 1707 | VG_(percentify)(Bc_total.mp, Bc_total.b, 1, l2+1, buf2); |
| 1708 | VG_(percentify)(Bi_total.mp, Bi_total.b, 1, l3+1, buf3); |
| 1709 | |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1710 | VG_(umsg)("Mispred rate: %s (%s + %s )\n", buf1, buf2,buf3); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1711 | } |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1712 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1713 | // Various stats |
sewardj | 2d9e874 | 2009-08-07 15:46:56 +0000 | [diff] [blame] | 1714 | if (VG_(clo_stats)) { |
njn | 1baf7db | 2006-04-18 22:34:48 +0000 | [diff] [blame] | 1715 | Int debug_lookups = full_debugs + fn_debugs + |
| 1716 | file_line_debugs + no_debugs; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1717 | |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1718 | VG_(dmsg)("\n"); |
weidendo | 6fc0de0 | 2012-10-30 00:28:29 +0000 | [diff] [blame] | 1719 | VG_(dmsg)("cachegrind: distinct files : %d\n", distinct_files); |
| 1720 | VG_(dmsg)("cachegrind: distinct functions : %d\n", distinct_fns); |
| 1721 | VG_(dmsg)("cachegrind: distinct lines : %d\n", distinct_lines); |
| 1722 | VG_(dmsg)("cachegrind: distinct instrs NoX: %d\n", distinct_instrsNoX); |
| 1723 | VG_(dmsg)("cachegrind: distinct instrs Gen: %d\n", distinct_instrsGen); |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1724 | VG_(dmsg)("cachegrind: debug lookups : %d\n", debug_lookups); |
njn | 1baf7db | 2006-04-18 22:34:48 +0000 | [diff] [blame] | 1725 | |
| 1726 | VG_(percentify)(full_debugs, debug_lookups, 1, 6, buf1); |
| 1727 | VG_(percentify)(file_line_debugs, debug_lookups, 1, 6, buf2); |
| 1728 | VG_(percentify)(fn_debugs, debug_lookups, 1, 6, buf3); |
| 1729 | VG_(percentify)(no_debugs, debug_lookups, 1, 6, buf4); |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1730 | VG_(dmsg)("cachegrind: with full info:%s (%d)\n", |
| 1731 | buf1, full_debugs); |
| 1732 | VG_(dmsg)("cachegrind: with file/line info:%s (%d)\n", |
| 1733 | buf2, file_line_debugs); |
| 1734 | VG_(dmsg)("cachegrind: with fn name info:%s (%d)\n", |
| 1735 | buf3, fn_debugs); |
| 1736 | VG_(dmsg)("cachegrind: with zero info:%s (%d)\n", |
| 1737 | buf4, no_debugs); |
njn | 1baf7db | 2006-04-18 22:34:48 +0000 | [diff] [blame] | 1738 | |
sewardj | b2c985b | 2009-07-15 14:51:17 +0000 | [diff] [blame] | 1739 | VG_(dmsg)("cachegrind: string table size: %lu\n", |
| 1740 | VG_(OSetGen_Size)(stringTable)); |
| 1741 | VG_(dmsg)("cachegrind: CC table size: %lu\n", |
| 1742 | VG_(OSetGen_Size)(CC_table)); |
| 1743 | VG_(dmsg)("cachegrind: InstrInfo table size: %lu\n", |
| 1744 | VG_(OSetGen_Size)(instrInfoTable)); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1745 | } |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1746 | } |
| 1747 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1748 | /*--------------------------------------------------------------------*/ |
| 1749 | /*--- Discarding BB info ---*/ |
| 1750 | /*--------------------------------------------------------------------*/ |
sewardj | 18d7513 | 2002-05-16 11:06:21 +0000 | [diff] [blame] | 1751 | |
sewardj | a3a29a5 | 2005-10-12 16:16:03 +0000 | [diff] [blame] | 1752 | // Called when a translation is removed from the translation cache for |
| 1753 | // any reason at all: to free up space, because the guest code was |
| 1754 | // unmapped or modified, or for any arbitrary reason. |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 1755 | static |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1756 | void cg_discard_superblock_info ( Addr64 orig_addr64, VexGuestExtents vge ) |
sewardj | 18d7513 | 2002-05-16 11:06:21 +0000 | [diff] [blame] | 1757 | { |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1758 | SB_info* sbInfo; |
sewardj | 3a384b3 | 2006-01-22 01:12:51 +0000 | [diff] [blame] | 1759 | Addr orig_addr = (Addr)vge.base[0]; |
njn | 4294fd4 | 2002-06-05 14:41:10 +0000 | [diff] [blame] | 1760 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1761 | tl_assert(vge.n_used > 0); |
| 1762 | |
| 1763 | if (DEBUG_CG) |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 1764 | VG_(printf)( "discard_basic_block_info: %p, %p, %llu\n", |
| 1765 | (void*)(Addr)orig_addr, |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1766 | (void*)(Addr)vge.base[0], (ULong)vge.len[0]); |
njn | 4294fd4 | 2002-06-05 14:41:10 +0000 | [diff] [blame] | 1767 | |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 1768 | // Get BB info, remove from table, free BB info. Simple! Note that we |
| 1769 | // use orig_addr, not the first instruction address in vge. |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1770 | sbInfo = VG_(OSetGen_Remove)(instrInfoTable, &orig_addr); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1771 | tl_assert(NULL != sbInfo); |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1772 | VG_(OSetGen_FreeNode)(instrInfoTable, sbInfo); |
sewardj | 18d7513 | 2002-05-16 11:06:21 +0000 | [diff] [blame] | 1773 | } |
| 1774 | |
| 1775 | /*--------------------------------------------------------------------*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1776 | /*--- Command line processing ---*/ |
| 1777 | /*--------------------------------------------------------------------*/ |
| 1778 | |
florian | 19f91bb | 2012-11-10 22:29:54 +0000 | [diff] [blame] | 1779 | static Bool cg_process_cmd_line_option(const HChar* arg) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1780 | { |
weidendo | 2364227 | 2011-09-06 19:08:31 +0000 | [diff] [blame] | 1781 | if (VG_(str_clo_cache_opt)(arg, |
| 1782 | &clo_I1_cache, |
| 1783 | &clo_D1_cache, |
| 1784 | &clo_LL_cache)) {} |
njn | 83df0b6 | 2009-02-25 01:01:05 +0000 | [diff] [blame] | 1785 | |
| 1786 | else if VG_STR_CLO( arg, "--cachegrind-out-file", clo_cachegrind_out_file) {} |
| 1787 | else if VG_BOOL_CLO(arg, "--cache-sim", clo_cache_sim) {} |
| 1788 | else if VG_BOOL_CLO(arg, "--branch-sim", clo_branch_sim) {} |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1789 | else |
| 1790 | return False; |
| 1791 | |
| 1792 | return True; |
| 1793 | } |
| 1794 | |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1795 | static void cg_print_usage(void) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1796 | { |
weidendo | 2364227 | 2011-09-06 19:08:31 +0000 | [diff] [blame] | 1797 | VG_(print_cache_clo_opts)(); |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1798 | VG_(printf)( |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1799 | " --cache-sim=yes|no [yes] collect cache stats?\n" |
| 1800 | " --branch-sim=yes|no [no] collect branch prediction stats?\n" |
njn | 374a36d | 2007-11-23 01:41:32 +0000 | [diff] [blame] | 1801 | " --cachegrind-out-file=<file> output file name [cachegrind.out.%%p]\n" |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1802 | ); |
| 1803 | } |
| 1804 | |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1805 | static void cg_print_debug_usage(void) |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1806 | { |
| 1807 | VG_(printf)( |
| 1808 | " (none)\n" |
| 1809 | ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1810 | } |
| 1811 | |
| 1812 | /*--------------------------------------------------------------------*/ |
| 1813 | /*--- Setup ---*/ |
| 1814 | /*--------------------------------------------------------------------*/ |
| 1815 | |
sewardj | e1216cb | 2007-02-07 19:55:30 +0000 | [diff] [blame] | 1816 | static void cg_post_clo_init(void); /* just below */ |
| 1817 | |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1818 | static void cg_pre_clo_init(void) |
| 1819 | { |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1820 | VG_(details_name) ("Cachegrind"); |
| 1821 | VG_(details_version) (NULL); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1822 | VG_(details_description) ("a cache and branch-prediction profiler"); |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1823 | VG_(details_copyright_author)( |
sewardj | 0f157dd | 2013-10-18 14:27:36 +0000 | [diff] [blame] | 1824 | "Copyright (C) 2002-2013, and GNU GPL'd, by Nicholas Nethercote et al."); |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1825 | VG_(details_bug_reports_to) (VG_BUGS_TO); |
sewardj | e808930 | 2006-10-17 02:15:17 +0000 | [diff] [blame] | 1826 | VG_(details_avg_translation_sizeB) ( 500 ); |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1827 | |
philippe | 5b240c2 | 2012-08-14 22:28:31 +0000 | [diff] [blame] | 1828 | VG_(clo_vex_control).iropt_register_updates |
| 1829 | = VexRegUpdSpAtMemAccess; // overridable by the user. |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1830 | VG_(basic_tool_funcs) (cg_post_clo_init, |
| 1831 | cg_instrument, |
| 1832 | cg_fini); |
| 1833 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1834 | VG_(needs_superblock_discards)(cg_discard_superblock_info); |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1835 | VG_(needs_command_line_options)(cg_process_cmd_line_option, |
| 1836 | cg_print_usage, |
| 1837 | cg_print_debug_usage); |
sewardj | e1216cb | 2007-02-07 19:55:30 +0000 | [diff] [blame] | 1838 | } |
| 1839 | |
| 1840 | static void cg_post_clo_init(void) |
| 1841 | { |
njn | 2d853a1 | 2010-10-06 22:46:31 +0000 | [diff] [blame] | 1842 | cache_t I1c, D1c, LLc; |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1843 | |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1844 | CC_table = |
| 1845 | VG_(OSetGen_Create)(offsetof(LineCC, loc), |
| 1846 | cmp_CodeLoc_LineCC, |
sewardj | 9c606bd | 2008-09-18 18:12:50 +0000 | [diff] [blame] | 1847 | VG_(malloc), "cg.main.cpci.1", |
| 1848 | VG_(free)); |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1849 | instrInfoTable = |
| 1850 | VG_(OSetGen_Create)(/*keyOff*/0, |
| 1851 | NULL, |
sewardj | 9c606bd | 2008-09-18 18:12:50 +0000 | [diff] [blame] | 1852 | VG_(malloc), "cg.main.cpci.2", |
| 1853 | VG_(free)); |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1854 | stringTable = |
| 1855 | VG_(OSetGen_Create)(/*keyOff*/0, |
| 1856 | stringCmp, |
sewardj | 9c606bd | 2008-09-18 18:12:50 +0000 | [diff] [blame] | 1857 | VG_(malloc), "cg.main.cpci.3", |
| 1858 | VG_(free)); |
sewardj | e1216cb | 2007-02-07 19:55:30 +0000 | [diff] [blame] | 1859 | |
weidendo | 2364227 | 2011-09-06 19:08:31 +0000 | [diff] [blame] | 1860 | VG_(post_clo_init_configure_caches)(&I1c, &D1c, &LLc, |
| 1861 | &clo_I1_cache, |
| 1862 | &clo_D1_cache, |
| 1863 | &clo_LL_cache); |
sewardj | e1216cb | 2007-02-07 19:55:30 +0000 | [diff] [blame] | 1864 | |
sewardj | 98763d5 | 2012-06-03 22:40:07 +0000 | [diff] [blame] | 1865 | // min_line_size is used to make sure that we never feed |
| 1866 | // accesses to the simulator straddling more than two |
| 1867 | // cache lines at any cache level |
| 1868 | min_line_size = (I1c.line_size < D1c.line_size) ? I1c.line_size : D1c.line_size; |
| 1869 | min_line_size = (LLc.line_size < min_line_size) ? LLc.line_size : min_line_size; |
| 1870 | |
| 1871 | Int largest_load_or_store_size |
| 1872 | = VG_(machine_get_size_of_largest_guest_register)(); |
| 1873 | if (min_line_size < largest_load_or_store_size) { |
| 1874 | /* We can't continue, because the cache simulation might |
| 1875 | straddle more than 2 lines, and it will assert. So let's |
| 1876 | just stop before we start. */ |
| 1877 | VG_(umsg)("Cachegrind: cannot continue: the minimum line size (%d)\n", |
| 1878 | (Int)min_line_size); |
| 1879 | VG_(umsg)(" must be equal to or larger than the maximum register size (%d)\n", |
| 1880 | largest_load_or_store_size ); |
| 1881 | VG_(umsg)(" but it is not. Exiting now.\n"); |
| 1882 | VG_(exit)(1); |
| 1883 | } |
| 1884 | |
weidendo | c1e9426 | 2012-10-05 23:58:17 +0000 | [diff] [blame] | 1885 | cachesim_initcaches(I1c, D1c, LLc); |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1886 | } |
| 1887 | |
sewardj | 45f4e7c | 2005-09-27 19:20:21 +0000 | [diff] [blame] | 1888 | VG_DETERMINE_INTERFACE_VERSION(cg_pre_clo_init) |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1889 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1890 | /*--------------------------------------------------------------------*/ |
njn | f69f945 | 2005-07-03 17:53:11 +0000 | [diff] [blame] | 1891 | /*--- end ---*/ |
sewardj | 18d7513 | 2002-05-16 11:06:21 +0000 | [diff] [blame] | 1892 | /*--------------------------------------------------------------------*/ |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1893 | |