msmtitanium: Add code for SDHCI support and setup MMU mapping.
Add code for SDHCI initialization and support.
Add code for init mmu_section_table and setup MMU mapping.
Add stub code for target detect and baseband detect.
Enable Reboot module.
Enable Secapp Loader module.
Change-Id: I38690461bfa18fc79f70e508d7afc5d2139edeff
diff --git a/platform/msmtitanium/include/platform/iomap.h b/platform/msmtitanium/include/platform/iomap.h
index c429f35..f23aa9c 100755
--- a/platform/msmtitanium/include/platform/iomap.h
+++ b/platform/msmtitanium/include/platform/iomap.h
@@ -43,6 +43,7 @@
#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
#define APPS_SS_BASE 0x0B000000
+#define APPS_SS_END 0x0B200000
#define MSM_GIC_DIST_BASE APPS_SS_BASE
#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
diff --git a/platform/msmtitanium/platform.c b/platform/msmtitanium/platform.c
index 6e851b1..2168570 100755
--- a/platform/msmtitanium/platform.c
+++ b/platform/msmtitanium/platform.c
@@ -40,6 +40,34 @@
#include <boot_stats.h>
#include <platform.h>
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+#define APPS_SS_SIZE ((APPS_SS_END - APPS_SS_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ { APPS_SS_BASE, APPS_SS_BASE, APPS_SS_SIZE, IOMAP_MEMORY},
+ { MSM_SHARED_IMEM_BASE, MSM_SHARED_IMEM_BASE, 1, COMMON_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, 512, SCRATCH_MEMORY},
+};
+
void platform_early_init(void)
{
board_init();
@@ -72,5 +100,71 @@
int platform_use_identity_mmu_mappings(void)
{
/* Use only the mappings specified in this file. */
- return 1;
+ return 0;
+}
+
+/* Setup MMU mapping for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+ uint32_t ddr_start = get_ddr_start();
+ uint32_t smem_addr = platform_get_smem_base_addr();
+
+ /*Mapping the ddr start address for loading the kernel about 90 MB*/
+ sections = 90;
+ while(sections--)
+ {
+ arm_mmu_map_section(ddr_start + sections * MB, ddr_start + sections* MB, COMMON_MEMORY);
+ }
+
+
+ /* Mapping the SMEM addr */
+ arm_mmu_map_section(smem_addr, smem_addr, COMMON_MEMORY);
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return phys_addr;
+}
+
+/* DYNAMIC SMEM REGION feature enables LK to dynamically
+ * read the SMEM addr info from TCSR_TZ_WONCE register.
+ * The first word read, if indicates a MAGIC number, then
+ * Dynamic SMEM is assumed to be enabled. Read the remaining
+ * SMEM info for SMEM Size and Phy_addr from the other bytes.
+ */
+uint32_t platform_get_smem_base_addr()
+{
+ struct smem_addr_info *smem_info = NULL;
+
+ smem_info = (struct smem_addr_info *)readl(TCSR_TZ_WONCE);
+ if(smem_info && (smem_info->identifier == SMEM_TARGET_INFO_IDENTIFIER))
+ return smem_info->phy_addr;
+ else
+ return MSM_SHARED_BASE;
}
diff --git a/platform/msmtitanium/rules.mk b/platform/msmtitanium/rules.mk
index 2734fb6..96b14d5 100755
--- a/platform/msmtitanium/rules.mk
+++ b/platform/msmtitanium/rules.mk
@@ -7,9 +7,11 @@
DEFINES += ARM_CPU_CORE_A7
DEFINES += ARM_CORE_V8
+MMC_SLOT := 1
DEFINES += PERIPH_BLK_BLSP=1
-DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+ MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
diff --git a/project/msmtitanium.mk b/project/msmtitanium.mk
index fd4c29b..d1449a5 100755
--- a/project/msmtitanium.mk
+++ b/project/msmtitanium.mk
@@ -13,6 +13,7 @@
endif
EMMC_BOOT := 1
+ENABLE_SECAPP_LOADER := 1
ENABLE_SMD_SUPPORT := 1
#ENABLE_PWM_SUPPORT := true
@@ -69,4 +70,4 @@
DEFINES += USE_TARGET_HS200_DELAY=1
#Enable the external reboot functions
-#ENABLE_REBOOT_MODULE := 1
+ENABLE_REBOOT_MODULE := 1
diff --git a/target/msmtitanium/init.c b/target/msmtitanium/init.c
old mode 100644
new mode 100755
index 5f76517..8a80a8c
--- a/target/msmtitanium/init.c
+++ b/target/msmtitanium/init.c
@@ -37,17 +37,21 @@
#include <dev/keys.h>
#include <spmi_v2.h>
#include <pm8x41.h>
+#include <pm8x41_hw.h>
#include <board.h>
#include <baseband.h>
#include <hsusb.h>
#include <scm.h>
-#include <platform/gpio.h>
-#include <platform/gpio.h>
#include <platform/irqs.h>
#include <platform/clock.h>
+#include <platform/timer.h>
#include <crypto5_wrapper.h>
#include <partition_parser.h>
#include <stdlib.h>
+#include <rpm-smd.h>
+#include <spmi.h>
+#include <sdhci_msm.h>
+#include <clock.h>
#if LONG_PRESS_POWER_ON
#include <shutdown_detect.h>
@@ -60,9 +64,16 @@
#define FASTBOOT_MODE 0x77665500
#define PON_SOFT_RB_SPARE 0x88F
-static uint32_t mmc_sdc_base[] =
+struct mmc_device *dev;
+
+static uint32_t mmc_pwrctl_base[] =
{ MSM_SDC1_BASE, MSM_SDC2_BASE };
+static uint32_t mmc_sdhci_base[] =
+ { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
+
+static uint32_t mmc_sdc_pwrctl_irq[] =
+ { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
void target_early_init(void)
{
@@ -71,12 +82,68 @@
#endif
}
-void target_mmc_caps(struct mmc_host *host)
+static void set_sdc_power_ctrl()
{
- host->caps.ddr_mode = 0;
- host->caps.hs200_mode = 0;
- host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
- host->caps.hs_clk_rate = MMC_CLK_50MHZ;
+ /* Drive strength configs for sdc pins */
+ struct tlmm_cfgs sdc1_hdrv_cfg[] =
+ {
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, 0},
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, 0},
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK , 0},
+ };
+
+ /* Pull configs for sdc pins */
+ struct tlmm_cfgs sdc1_pull_cfg[] =
+ {
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, 0},
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0},
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0},
+ };
+
+ struct tlmm_cfgs sdc1_rclk_cfg[] =
+ {
+ { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, 0},
+ };
+
+ /* Set the drive strength & pull control values */
+ tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+ tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+ tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
+}
+
+void target_sdc_init()
+{
+ struct mmc_config_data config;
+
+ /* Set drive strength & pull ctrl values */
+ set_sdc_power_ctrl();
+
+ config.slot = MMC_SLOT;
+ config.bus_width = DATA_BUS_WIDTH_8BIT;
+ config.max_clk_rate = MMC_CLK_192MHZ;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.hs400_support = 1;
+
+ if (!(dev = mmc_init(&config))) {
+ /* Try different config. values */
+ config.max_clk_rate = MMC_CLK_200MHZ;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.hs400_support = 0;
+
+ if (!(dev = mmc_init(&config))) {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
+ }
+}
+
+void *target_mmc_device()
+{
+ return (void *) dev;
}
/* Return 1 if vol_up pressed */
@@ -114,48 +181,21 @@
keys_post_event(KEY_VOLUMEUP, 1);
}
-/* Configure PMIC and Drop PS_HOLD for shutdown */
-void shutdown_device()
-{
- dprintf(CRITICAL, "Going down for shutdown.\n");
-
- /* Configure PMIC for shutdown */
- pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
-
- /* Drop PS_HOLD for MSM */
- writel(0x00, MPM2_MPM_PS_HOLD);
-
- mdelay(5000);
-
- dprintf(CRITICAL, "shutdown failed\n");
-
- ASSERT(0);
-}
-
-
void target_init(void)
{
- uint32_t base_addr;
- uint8_t slot;
-
dprintf(INFO, "target_init()\n");
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
target_keystatus();
- /* Trying Slot 1*/
- slot = 1;
- base_addr = mmc_sdc_base[slot - 1];
- if (mmc_boot_main(slot, base_addr)) {
- /* Trying Slot 2 next */
- slot = 2;
- base_addr = mmc_sdc_base[slot - 1];
- if (mmc_boot_main(slot, base_addr)) {
- dprintf(CRITICAL, "mmc init failed!");
- ASSERT(0);
- }
+ target_sdc_init();
+ if (partition_read_table())
+ {
+ dprintf(CRITICAL, "Error reading the partition table info\n");
+ ASSERT(0);
}
+
#if LONG_PRESS_POWER_ON
shutdown_detect();
#endif
@@ -172,6 +212,29 @@
unsigned board_machtype(void)
{
+ return LINUX_MACHTYPE_UNKNOWN;
+}
+
+/* Detect the target type */
+void target_detect(struct board_data *board)
+{
+ /* This is already filled as part of board.c */
+}
+
+void target_baseband_detect(struct board_data *board)
+{
+ uint32_t platform;
+
+ platform = board->platform;
+
+ switch(platform) {
+ case MSMTITANIUM:
+ board->baseband = BASEBAND_MSM;
+ break;
+ default:
+ dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+ ASSERT(0);
+ };
}
int set_download_mode(enum dload_mode mode)
@@ -250,3 +313,15 @@
{
return "dwc";
}
+
+
+crypto_engine_type board_ce_type(void)
+{
+ return CRYPTO_ENGINE_TYPE_HW;
+}
+
+
+void pmic_reset_configure(uint8_t reset_type)
+{
+ pm8x41_reset_configure(reset_type);
+}