msm8974: Enable UART
Add clock and gpio support needed for UART on 8974.
Change-Id: I277941c8fa4c1dad8cf241e638dde71d156c6fb4
diff --git a/platform/copper/acpuclock.c b/platform/copper/acpuclock.c
index 3911572..8a9f96d 100644
--- a/platform/copper/acpuclock.c
+++ b/platform/copper/acpuclock.c
@@ -153,11 +153,15 @@
{
int ret;
- /* Enable blsp_uart_clk */
- /* TODO: Find out correct frequency and UART_DM_CLK_RX_TX_BIT_RATE
- * combination for generating 115200 baud rate.
- */
- ret = clk_get_set_enable("uart1_core_clk", 7372800, 1);
+
+ ret = clk_get_set_enable("uart2_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("uart2_core_clk", 7372800, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret);
diff --git a/platform/copper/copper-clock.c b/platform/copper/copper-clock.c
index 7fd15bb..ed7ace2 100644
--- a/platform/copper/copper-clock.c
+++ b/platform/copper/copper-clock.c
@@ -77,6 +77,11 @@
.is_enabled = pll_vote_clk_is_enabled,
};
+static struct clk_ops clk_ops_vote =
+{
+ .enable = clock_lib2_vote_clk_enable,
+ .disable = clock_lib2_vote_clk_disable,
+};
/* Clock Sources */
static struct fixed_clk cxo_clk_src =
@@ -176,61 +181,43 @@
F_END
};
-static struct rcg_clk blsp1_uart1_apps_clk_src =
+static struct rcg_clk blsp1_uart2_apps_clk_src =
{
- .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP1_UART1_APPS_M,
- .n_reg = (uint32_t *) BLSP1_UART1_APPS_N,
- .d_reg = (uint32_t *) BLSP1_UART1_APPS_D,
+ .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
- .dbg_name = "blsp1_uart1_apps_clk",
+ .dbg_name = "blsp1_uart2_apps_clk",
.ops = &clk_ops_rcg_mnd,
},
};
-static struct rcg_clk blsp1_uart3_apps_clk_src =
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
{
- .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR,
- .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR,
- .m_reg = (uint32_t *) BLSP1_UART3_APPS_M,
- .n_reg = (uint32_t *) BLSP1_UART3_APPS_N,
- .d_reg = (uint32_t *) BLSP1_UART3_APPS_D,
-
- .set_rate = clock_lib2_rcg_set_rate_mnd,
- .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
- .current_freq = &rcg_dummy_freq,
+ .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+ .parent = &blsp1_uart2_apps_clk_src.c,
.c = {
- .dbg_name = "blsp1_uart3_apps_clk",
- .ops = &clk_ops_rcg_mnd,
- },
-};
-
-static struct branch_clk gcc_blsp1_uart1_apps_clk =
-{
- .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR,
- .parent = &blsp1_uart1_apps_clk_src.c,
-
- .c = {
- .dbg_name = "gcc_blsp1_uart1_apps_clk",
+ .dbg_name = "gcc_blsp1_uart2_apps_clk",
.ops = &clk_ops_branch,
},
};
-static struct branch_clk gcc_blsp1_uart3_apps_clk =
-{
- .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR,
- .parent = &blsp1_uart3_apps_clk_src.c,
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(17),
.c = {
- .dbg_name = "gcc_blsp1_uart3_apps_clk",
- .ops = &clk_ops_branch,
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
},
};
@@ -285,8 +272,8 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
- CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c),
- CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c),
+ CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
diff --git a/platform/copper/gpio.c b/platform/copper/gpio.c
index 86b9e40..806aab4 100644
--- a/platform/copper/gpio.c
+++ b/platform/copper/gpio.c
@@ -54,9 +54,11 @@
/* Configure gpio for blsp uart 2 */
void gpio_config_uart_dm(uint8_t id)
{
- gpio_tlmm_config(0, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ /* configure rx gpio */
+ gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
- gpio_tlmm_config(1, 2, GPIO_INPUT, GPIO_NO_PULL,
+ /* configure tx gpio */
+ gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
}
diff --git a/platform/copper/include/platform/clock.h b/platform/copper/include/platform/clock.h
index 0aa8604..7d59b0c 100644
--- a/platform/copper/include/platform/clock.h
+++ b/platform/copper/include/platform/clock.h
@@ -32,7 +32,7 @@
#include <clock.h>
#include <clock_lib2.h>
-#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
void platform_clock_init(void);
diff --git a/platform/copper/include/platform/iomap.h b/platform/copper/include/platform/iomap.h
index d48c7c9..c26f1b5 100644
--- a/platform/copper/include/platform/iomap.h
+++ b/platform/copper/include/platform/iomap.h
@@ -83,7 +83,7 @@
#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
#define SPMI_PIC_BASE (SPMI_BASE + 0xB000)
-#define TLMM_BASE_ADDR 0xFD500000
+#define TLMM_BASE_ADDR 0xFD510000
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
@@ -93,6 +93,7 @@
/* GPLL */
#define GPLL0_STATUS (CLK_CTL_BASE + 0x001C)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
/* SDCC */
#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
@@ -106,19 +107,13 @@
#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
/* UART */
-#define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x684)
-#define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x68C)
-#define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x690)
-#define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x694)
-#define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x698)
-#define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x69C)
-
-#define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x784)
-#define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x78C)
-#define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x790)
-#define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x794)
-#define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x798)
-#define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x79C)
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
+#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704)
+#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C)
+#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710)
+#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714)
+#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718)
+#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C)
/* USB */
#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
diff --git a/platform/msm_shared/clock_lib2.c b/platform/msm_shared/clock_lib2.c
index 0aa405c..645755c 100644
--- a/platform/msm_shared/clock_lib2.c
+++ b/platform/msm_shared/clock_lib2.c
@@ -191,3 +191,39 @@
clock_lib2_rcg_update_config(rclk);
}
+
+/*=============== Vote clock ops =============*/
+
+/* Vote clock enable */
+int clock_lib2_vote_clk_enable(struct clk *c)
+{
+ uint32_t vote_regval;
+ uint32_t val;
+ struct vote_clk *vclk = to_local_vote_clk(c);
+
+ vote_regval = readl(vclk->vote_reg);
+ vote_regval |= vclk->en_mask;
+ writel_relaxed(vote_regval, vclk->vote_reg);
+ do {
+ val = readl(vclk->cbcr_reg);
+ val &= BRANCH_CHECK_MASK;
+ }
+ /* wait until status shows it is enabled */
+ while((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
+
+ return 0;
+}
+
+/* Vote clock disable */
+void clock_lib2_vote_clk_disable(struct clk *c)
+{
+ uint32_t vote_regval;
+ struct vote_clk *vclk = to_local_vote_clk(c);
+
+ vote_regval = readl(vclk->vote_reg);
+ vote_regval &= ~vclk->en_mask;
+ writel_relaxed(vote_regval, vclk->vote_reg);
+
+ /* wait until status shows it is disabled */
+ while(!(readl(vclk->cbcr_reg) & CBCR_BRANCH_OFF_BIT));
+}
diff --git a/platform/msm_shared/include/clock_lib2.h b/platform/msm_shared/include/clock_lib2.h
index 0a82c51..2f6deb7 100644
--- a/platform/msm_shared/include/clock_lib2.h
+++ b/platform/msm_shared/include/clock_lib2.h
@@ -62,6 +62,9 @@
/* Branch Clock Bits */
#define CBCR_BRANCH_ENABLE_BIT BIT(0)
#define CBCR_BRANCH_OFF_BIT BIT(31)
+#define BRANCH_CHECK_MASK BM(31, 28)
+#define BRANCH_ON_VAL BVAL(31, 28, 0x0)
+#define BRANCH_NOC_FSM_ON_VAL BVAL(31, 28, 0x2)
/* Root Clock Bits */
#define CMD_UPDATE_BIT BIT(0)
@@ -138,6 +141,16 @@
struct clk c;
};
+/* Vote Clock */
+struct vote_clk {
+
+ uint32_t *const cbcr_reg;
+ uint32_t *const vote_reg;
+ uint32_t en_mask;
+
+ struct clk c;
+};
+
static inline struct rcg_clk *to_rcg_clk(struct clk *clk)
{
return container_of(clk, struct rcg_clk, c);
@@ -148,6 +161,11 @@
return container_of(clk, struct branch_clk, c);
}
+static inline struct vote_clk *to_local_vote_clk(struct clk *clk)
+{
+ return container_of(clk, struct vote_clk, c);
+}
+
/* RCG clock functions */
int clock_lib2_rcg_enable(struct clk *c);
int clock_lib2_rcg_set_rate(struct clk *c, unsigned rate);
@@ -163,4 +181,7 @@
void clock_lib2_branch_clk_disable(struct clk *clk);
int clock_lib2_branch_set_rate(struct clk *c, unsigned rate);
+/* Vote clock functions*/
+int clock_lib2_vote_clk_enable(struct clk *c);
+void clock_lib2_vote_clk_disable(struct clk *c);
#endif
diff --git a/project/copper.mk b/project/copper.mk
index 79681f0..35e2c15 100644
--- a/project/copper.mk
+++ b/project/copper.mk
@@ -9,7 +9,7 @@
DEBUG := 1
#DEFINES += WITH_DEBUG_DCC=1
-#DEFINES += WITH_DEBUG_UART=1
+DEFINES += WITH_DEBUG_UART=1
#DEFINES += WITH_DEBUG_FBCON=1
DEFINES += DEVICE_TREE=1
#DEFINES += MMC_BOOT_BAM=1
diff --git a/target/copper/init.c b/target/copper/init.c
index b5922c3..56acf93 100644
--- a/target/copper/init.c
+++ b/target/copper/init.c
@@ -54,7 +54,7 @@
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(0, 0, BLSP1_UART0_BASE);
+ uart_dm_init(1, 0, BLSP1_UART1_BASE);
#endif
}