Dhaval Patel | ce0d60c | 2014-01-02 16:43:54 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
Deepa Dinamani | a63c518 | 2013-01-30 12:39:34 -0800 | [diff] [blame] | 29 | #ifndef _PLATFORM_MSM8226_IOMAP_H_ |
| 30 | #define _PLATFORM_MSM8226_IOMAP_H_ |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 31 | |
| 32 | #define MSM_IOMAP_BASE 0xF9000000 |
| 33 | #define MSM_IOMAP_END 0xFEFFFFFF |
| 34 | |
| 35 | #define SDRAM_START_ADDR 0x00000000 |
| 36 | |
| 37 | #define MSM_SHARED_BASE 0x0FA00000 |
Sundarajan Srinivasan | c4e1a99 | 2014-03-28 16:45:21 -0700 | [diff] [blame] | 38 | #define MSM_DYNAMIC_SHARED_BASE 0xFE802FF8 |
| 39 | |
| 40 | #define SMEM_TARGET_INFO_ADDR 0xFE802FF0 |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 41 | |
| 42 | #define APPS_SS_BASE 0xF9000000 |
| 43 | |
Deepa Dinamani | 595d6f9 | 2013-02-26 13:58:03 -0800 | [diff] [blame] | 44 | #define SYSTEM_IMEM_BASE 0xFE800000 |
Pavel Nedev | 16f4923 | 2013-04-29 16:15:36 +0300 | [diff] [blame] | 45 | #define MSM_SHARED_IMEM_BASE 0xFE805000 |
| 46 | |
| 47 | #define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C) |
Pavel Nedev | a4c9d3a | 2013-05-15 14:42:34 +0300 | [diff] [blame] | 48 | #define DLOAD_MODE_ADDR (MSM_SHARED_IMEM_BASE + 0x0) |
| 49 | #define EMERGENCY_DLOAD_MODE_ADDR (MSM_SHARED_IMEM_BASE + 0xFE0) |
Deepa Dinamani | 595d6f9 | 2013-02-26 13:58:03 -0800 | [diff] [blame] | 50 | |
sundarajan srinivasan | 432010b | 2013-05-10 14:24:53 -0700 | [diff] [blame] | 51 | #define BS_INFO_OFFSET (0x6B0) |
| 52 | #define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET) |
| 53 | #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000 |
| 54 | |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 55 | #define MSM_GIC_DIST_BASE APPS_SS_BASE |
| 56 | #define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000) |
| 57 | #define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000) |
| 58 | #define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000) |
| 59 | #define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE |
| 60 | |
| 61 | #define PERIPH_SS_BASE 0xF9800000 |
| 62 | |
| 63 | #define MSM_SDC1_BAM_BASE (PERIPH_SS_BASE + 0x00004000) |
| 64 | #define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000) |
Channagoud Kadabi | 2a4e6f9 | 2013-05-02 17:07:13 -0700 | [diff] [blame] | 65 | #define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900) |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 66 | #define MSM_SDC1_DML_BASE (PERIPH_SS_BASE + 0x00024800) |
| 67 | #define MSM_SDC3_BAM_BASE (PERIPH_SS_BASE + 0x00044000) |
| 68 | #define MSM_SDC3_BASE (PERIPH_SS_BASE + 0x00064000) |
Channagoud Kadabi | 2a4e6f9 | 2013-05-02 17:07:13 -0700 | [diff] [blame] | 69 | #define MSM_SDC3_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900) |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 70 | #define MSM_SDC3_DML_BASE (PERIPH_SS_BASE + 0x00064800) |
| 71 | #define MSM_SDC2_BAM_BASE (PERIPH_SS_BASE + 0x00084000) |
| 72 | #define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000) |
| 73 | #define MSM_SDC2_DML_BASE (PERIPH_SS_BASE + 0x000A4800) |
Channagoud Kadabi | 2a4e6f9 | 2013-05-02 17:07:13 -0700 | [diff] [blame] | 74 | #define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900) |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 75 | |
| 76 | #define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000) |
| 77 | #define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000) |
| 78 | #define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000) |
| 79 | #define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000) |
| 80 | #define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000) |
| 81 | #define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000) |
| 82 | #define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000) |
| 83 | |
| 84 | #define CLK_CTL_BASE 0xFC400000 |
| 85 | |
| 86 | #define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780) |
| 87 | |
| 88 | #define USB_HS_BCR (CLK_CTL_BASE + 0x480) |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 89 | |
| 90 | #define SPMI_BASE 0xFC4C0000 |
| 91 | #define SPMI_GENI_BASE (SPMI_BASE + 0xA000) |
| 92 | #define SPMI_PIC_BASE (SPMI_BASE + 0xB000) |
| 93 | |
| 94 | #define MSM_CE1_BAM_BASE 0xFD404000 |
| 95 | #define MSM_CE1_BASE 0xFD41A000 |
| 96 | |
| 97 | #define TLMM_BASE_ADDR 0xFD510000 |
| 98 | #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) |
| 99 | #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10) |
Ray Zhang | 3bd5bd1 | 2013-04-19 18:14:09 +0800 | [diff] [blame] | 100 | #define GPIO_OUT_SET_ADDR(x) (TLMM_BASE_ADDR + 0x3040 + (x/32)*0x04) |
| 101 | #define GPIO_OUT_CLR_ADDR(x) (TLMM_BASE_ADDR + 0x3020 + (x/32)*0x04) |
| 102 | #define GPIO_OUT_VAL(x) (1 << (x - (x/32)*32)) |
| 103 | #define GPIO_OUT_OE_SET_ADDR(x) (TLMM_BASE_ADDR + 0x3120 + (x/32)*0x04) |
| 104 | #define GPIO_OUT_OE_VAL(x) (1 << (x - (x/32)*32)) |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 105 | |
| 106 | #define MPM2_MPM_CTRL_BASE 0xFC4A1000 |
| 107 | #define MPM2_MPM_PS_HOLD 0xFC4AB000 |
| 108 | |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 109 | /* GPLL */ |
Deepa Dinamani | 0a6c48c | 2013-02-04 15:45:01 -0800 | [diff] [blame] | 110 | #define GPLL0_MODE CLK_CTL_BASE |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 111 | #define GPLL0_STATUS (CLK_CTL_BASE + 0x001C) |
| 112 | #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480) |
| 113 | #define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484) |
| 114 | |
Deepa Dinamani | c51ad20 | 2013-04-02 14:58:56 -0700 | [diff] [blame] | 115 | /* CE 1 */ |
| 116 | #define GCC_CE1_BCR (CLK_CTL_BASE + 0x1040) |
| 117 | #define GCC_CE1_CMD_RCGR (CLK_CTL_BASE + 0x1050) |
| 118 | #define GCC_CE1_CFG_RCGR (CLK_CTL_BASE + 0x1054) |
| 119 | #define GCC_CE1_CBCR (CLK_CTL_BASE + 0x1044) |
| 120 | #define GCC_CE1_AXI_CBCR (CLK_CTL_BASE + 0x1048) |
| 121 | #define GCC_CE1_AHB_CBCR (CLK_CTL_BASE + 0x104C) |
| 122 | |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 123 | /* SDCC */ |
| 124 | #define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */ |
| 125 | #define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */ |
| 126 | #define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8) |
| 127 | #define SDCC1_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x4CC) |
| 128 | #define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */ |
| 129 | #define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */ |
| 130 | #define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */ |
| 131 | #define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */ |
| 132 | #define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */ |
| 133 | |
Channagoud Kadabi | 6b9205d | 2013-05-14 13:22:35 -0700 | [diff] [blame] | 134 | /* SDCC2 */ |
| 135 | #define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */ |
| 136 | #define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */ |
| 137 | #define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x508) |
| 138 | #define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C) |
| 139 | #define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x510) /* cmd */ |
| 140 | #define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x514) /* cfg */ |
| 141 | #define SDCC2_M (CLK_CTL_BASE + 0x518) /* m */ |
| 142 | #define SDCC2_N (CLK_CTL_BASE + 0x51C) /* n */ |
| 143 | #define SDCC2_D (CLK_CTL_BASE + 0x520) /* d */ |
| 144 | |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 145 | /* UART */ |
| 146 | #define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4) |
Deepa Dinamani | 0a6c48c | 2013-02-04 15:45:01 -0800 | [diff] [blame] | 147 | #define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x784) |
| 148 | #define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x78C) |
| 149 | #define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x790) |
| 150 | #define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x794) |
| 151 | #define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x798) |
| 152 | #define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x79C) |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 153 | |
| 154 | /* USB */ |
| 155 | #define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484) |
| 156 | #define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488) |
| 157 | #define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490) |
| 158 | #define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494) |
| 159 | |
Channagoud Kadabi | 2a4e6f9 | 2013-05-02 17:07:13 -0700 | [diff] [blame] | 160 | /* SDHCI */ |
Channagoud Kadabi | 6b9205d | 2013-05-14 13:22:35 -0700 | [diff] [blame] | 161 | #define SDCC_MCI_HC_MODE (0x00000078) |
| 162 | #define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC) |
| 163 | #define SDCC_HC_PWRCTL_MASK_REG (0x000000E0) |
| 164 | #define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4) |
| 165 | #define SDCC_HC_PWRCTL_CTL_REG (0x000000E8) |
Channagoud Kadabi | 2a4e6f9 | 2013-05-02 17:07:13 -0700 | [diff] [blame] | 166 | |
| 167 | /* DRV strength for sdcc */ |
| 168 | #define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044) |
Ray Zhang | 955c55f | 2013-05-25 23:07:50 +0800 | [diff] [blame] | 169 | |
| 170 | /* MDSS */ |
| 171 | #define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000 |
| 172 | #define MIPI_DSI_BASE (0xFD922800) |
| 173 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 174 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
Padmanabhan Komanduru | 0e9a09b | 2014-03-25 19:53:01 +0530 | [diff] [blame] | 175 | #define DSI0_PHY_BASE (0xFD922B00) |
| 176 | #define DSI1_PHY_BASE DSI0_PHY_BASE |
| 177 | #define DSI0_PLL_BASE (0xFD922A00) |
| 178 | #define DSI1_PLL_BASE DSI0_PLL_BASE |
Ray Zhang | 955c55f | 2013-05-25 23:07:50 +0800 | [diff] [blame] | 179 | #define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off)) |
| 180 | #define MDP_BASE (0xfd900000) |
| 181 | #define REG_MDP(off) (MDP_BASE + (off)) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame^] | 182 | #define MDP_VP_0_VIG_0_BASE REG_MDP(0x1200) |
| 183 | #define MDP_VP_0_VIG_1_BASE REG_MDP(0x1600) |
| 184 | #define MDP_VP_0_RGB_0_BASE REG_MDP(0x1E00) |
| 185 | #define MDP_VP_0_RGB_1_BASE REG_MDP(0x2200) |
| 186 | #define MDP_VP_0_DMA_0_BASE REG_MDP(0x2A00) |
| 187 | #define MDP_VP_0_DMA_1_BASE REG_MDP(0x2E00) |
| 188 | #define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3200) |
| 189 | #define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3600) |
Ray Zhang | 955c55f | 2013-05-25 23:07:50 +0800 | [diff] [blame] | 190 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 191 | #define SOFT_RESET 0x118 |
| 192 | #define CLK_CTRL 0x11C |
| 193 | #define TRIG_CTRL 0x084 |
| 194 | #define CTRL 0x004 |
| 195 | #define COMMAND_MODE_DMA_CTRL 0x03C |
Dhaval Patel | ce0d60c | 2014-01-02 16:43:54 -0800 | [diff] [blame] | 196 | #define COMMAND_MODE_MDP_CTRL 0x040 |
| 197 | #define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044 |
| 198 | #define COMMAND_MODE_MDP_STREAM0_CTRL 0x058 |
| 199 | #define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C |
| 200 | #define COMMAND_MODE_MDP_STREAM1_CTRL 0x060 |
| 201 | #define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064 |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 202 | #define ERR_INT_MASK0 0x10C |
| 203 | |
| 204 | #define LANE_SWAP_CTL 0x0B0 |
| 205 | #define TIMING_CTL 0x0C4 |
| 206 | |
| 207 | #define VIDEO_MODE_ACTIVE_H 0x024 |
| 208 | #define VIDEO_MODE_ACTIVE_V 0x028 |
| 209 | #define VIDEO_MODE_TOTAL 0x02C |
| 210 | #define VIDEO_MODE_HSYNC 0x030 |
| 211 | #define VIDEO_MODE_VSYNC 0x034 |
| 212 | #define VIDEO_MODE_VSYNC_VPOS 0x038 |
| 213 | |
| 214 | #define DMA_CMD_OFFSET 0x048 |
| 215 | #define DMA_CMD_LENGTH 0x04C |
| 216 | |
| 217 | #define INT_CTRL 0x110 |
| 218 | #define CMD_MODE_DMA_SW_TRIGGER 0x090 |
| 219 | |
Siddhartha Agrawal | a0ff680 | 2014-02-26 11:02:58 -0800 | [diff] [blame] | 220 | #define EOT_PACKET_CTRL 0x0CC |
Dhaval Patel | ce0d60c | 2014-01-02 16:43:54 -0800 | [diff] [blame] | 221 | #define MISR_CMD_CTRL 0x0A0 |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 222 | #define MISR_VIDEO_CTRL 0x0A4 |
| 223 | #define VIDEO_MODE_CTRL 0x010 |
| 224 | #define HS_TIMER_CTRL 0x0BC |
| 225 | |
Deepa Dinamani | 645e9b1 | 2012-12-21 14:23:40 -0800 | [diff] [blame] | 226 | #endif |