Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame^] | 1 | /* at91sam7s.h -- AT91SAM7S hardware definitions |
| 2 | ** |
| 3 | ** Copyright 2006, Brian Swetland. All rights reserved. |
| 4 | ** See provided LICENSE file or http://frotz.net/LICENSE for details. |
| 5 | */ |
| 6 | |
| 7 | #ifndef __PLATFORM_AT91SAM7_H__ |
| 8 | #define __PLATFORM_AT91SAM7_H__ |
| 9 | |
| 10 | #if !defined(AT91_SAM7X) && !defined(AT91_SAM7S) |
| 11 | #error Unspecified Architecture - AT91SAM7S or AT91SAM7X must be defined |
| 12 | #endif |
| 13 | |
| 14 | /* peripheral ids */ |
| 15 | #define PID_AIC_FIQ 0 |
| 16 | #define PID_SYSIRQ 1 |
| 17 | #define PID_PIOA 2 |
| 18 | #define PID_USART0 6 |
| 19 | #define PID_USART1 7 |
| 20 | #define PID_SSC 8 |
| 21 | #define PID_TWI 9 |
| 22 | #define PID_PWMC 10 |
| 23 | #define PID_UDP 11 |
| 24 | #define PID_TC0 12 |
| 25 | #define PID_TC1 13 |
| 26 | #define PID_TC2 14 |
| 27 | #if AT91_SAM7X |
| 28 | #define PID_PIOB 3 |
| 29 | #define PID_SPI0 4 |
| 30 | #define PID_SPI1 5 |
| 31 | #define PID_CAN 15 |
| 32 | #define PID_EMAC 16 |
| 33 | #define PID_ADC 17 |
| 34 | #define PID_AIC_IRQ0 30 |
| 35 | #define PID_AIC_IRQ1 31 |
| 36 | #else |
| 37 | #define PID_ADC 4 |
| 38 | #define PID_SPI0 5 |
| 39 | #define PID_AIC_IRQ 30 |
| 40 | #endif |
| 41 | |
| 42 | #define BASE_FLASH 0x00100000 |
| 43 | #define BASE_SRAM 0x00200000 |
| 44 | #define BASE_TC 0xFFFA0000 |
| 45 | #define BASE_UDP 0xFFFB0000 |
| 46 | #define BASE_TWI 0xFFFB8000 |
| 47 | #define BASE_USART0 0xFFFC0000 |
| 48 | #define BASE_USART1 0xFFFC4000 |
| 49 | #define BASE_PWMC 0xFFFCC000 |
| 50 | #define BASE_SSC 0xFFFD4000 |
| 51 | #define BASE_ADC 0xFFFD8000 |
| 52 | #define BASE_SPI0 0xFFFE0000 |
| 53 | |
| 54 | #define BASE_AIC 0xFFFFF000 |
| 55 | #define BASE_DBGU 0xFFFFF200 |
| 56 | #define BASE_PIOA 0xFFFFF400 |
| 57 | #define BASE_PMC 0xFFFFFC00 |
| 58 | #define BASE_RSTC 0xFFFFFD00 |
| 59 | #define BASE_RTT 0xFFFFFD20 |
| 60 | #define BASE_PIT 0xFFFFFD30 |
| 61 | #define BASE_WDT 0xFFFFFD40 |
| 62 | #define BASE_VREG 0xFFFFFD60 |
| 63 | #define BASE_MC 0xFFFFFF00 |
| 64 | |
| 65 | #if AT91_SAM7X |
| 66 | #define BASE_CAN 0xFFFD0000 |
| 67 | #define BASE_EMAC 0xFFFDC000 |
| 68 | #define BASE_SPI1 0xFFFE4000 |
| 69 | #define BASE_PIOB 0xFFFFF600 |
| 70 | #endif |
| 71 | |
| 72 | |
| 73 | typedef volatile unsigned int vu4; |
| 74 | |
| 75 | typedef struct |
| 76 | { |
| 77 | vu4 MR; |
| 78 | vu4 SR; |
| 79 | vu4 PIVR; |
| 80 | vu4 PIIR; |
| 81 | } AT91PIT; |
| 82 | |
| 83 | /* MR */ |
| 84 | #define PIT_PITEN (1 << 24) |
| 85 | #define PIT_PITIEN (1 << 25) |
| 86 | |
| 87 | /* SR */ |
| 88 | #define PIT_PITS (1) |
| 89 | |
| 90 | /* PIxR */ |
| 91 | #define PIT_PICNT(x) (x >> 20) |
| 92 | #define PIT_CPIV(x) (x & 0x000fffff) |
| 93 | |
| 94 | #define AT91PIT_ADDR ((AT91PIT*) BASE_PIT) |
| 95 | |
| 96 | typedef struct |
| 97 | { |
| 98 | vu4 CR; |
| 99 | vu4 MR; |
| 100 | vu4 IER; |
| 101 | vu4 IDR; |
| 102 | vu4 IMR; |
| 103 | vu4 SR; |
| 104 | vu4 RHR; |
| 105 | vu4 THR; |
| 106 | vu4 BRGR; |
| 107 | vu4 __0[7]; |
| 108 | vu4 CIDR; |
| 109 | vu4 EXID; |
| 110 | vu4 FNR; |
| 111 | } AT91DBGU; |
| 112 | |
| 113 | /* CR bits */ |
| 114 | #define DBGU_RSTRX 0x00000004 |
| 115 | #define DBGU_RSTTX 0x00000008 |
| 116 | #define DBGU_RXEN 0x00000010 |
| 117 | #define DBGU_RXDIS 0x00000020 |
| 118 | #define DBGU_TXEN 0x00000040 |
| 119 | #define DBGU_TXDIS 0x00000080 |
| 120 | #define DBGU_RSTSTA 0x00000100 |
| 121 | |
| 122 | /* MR bits */ |
| 123 | #define DBGU_PAR_EVEN 0x00000000 |
| 124 | #define DBGU_PAR_ODD 0x00000200 |
| 125 | #define DBGU_PAR_SPACE 0x00000400 |
| 126 | #define DBGU_PAR_MARK 0x00000600 |
| 127 | #define DBGU_PAR_NONE 0x00000800 |
| 128 | |
| 129 | #define DBGU_MODE_NORMAL 0x00000000 |
| 130 | #define DBGU_MODE_ECHO 0x0000C000 |
| 131 | #define DBGU_MODE_LLOOP 0x00008000 |
| 132 | #define DBGU_MODE_RLOOP 0x00004000 |
| 133 | |
| 134 | /* IER, IDR, IMR, and SR bits */ |
| 135 | #define DBGU_RXRDY 0x00000001 |
| 136 | #define DBGU_TXRDY 0x00000002 |
| 137 | #define DBGU_ENDRX 0x00000008 |
| 138 | #define DBGU_ENDTX 0x00000010 |
| 139 | #define DBGU_OVRE 0x00000020 |
| 140 | #define DBGU_FRAME 0x00000040 |
| 141 | #define DBGU_PARE 0x00000080 |
| 142 | #define DBGU_TXEMPTY 0x00000200 |
| 143 | #define DBGU_TXBUFE 0x00000800 |
| 144 | #define DBGU_RXBUFF 0x00001000 |
| 145 | #define DBGU_COMMTX 0x40000000 |
| 146 | #define DBGU_COMMRX 0x80000000 |
| 147 | |
| 148 | #define AT91DBGU_ADDR ((AT91DBGU*) BASE_DBGU) |
| 149 | |
| 150 | typedef struct |
| 151 | { |
| 152 | vu4 pio_enable; |
| 153 | vu4 pio_disable; |
| 154 | vu4 pio_status; |
| 155 | vu4 __0; |
| 156 | vu4 output_enable; |
| 157 | vu4 output_disable; |
| 158 | vu4 output_status; |
| 159 | vu4 __1; |
| 160 | vu4 filter_enable; |
| 161 | vu4 filter_disable; |
| 162 | vu4 filter_status; |
| 163 | vu4 __2; |
| 164 | vu4 data_set; |
| 165 | vu4 data_clear; |
| 166 | vu4 data_status; |
| 167 | vu4 pin_status; |
| 168 | vu4 irq_enable; |
| 169 | vu4 irq_disable; |
| 170 | vu4 irq_mask; |
| 171 | vu4 irq_status; |
| 172 | vu4 multidriver_enable; |
| 173 | vu4 multidriver_disable; |
| 174 | vu4 multidriver_status; |
| 175 | vu4 __3; |
| 176 | vu4 pullup_disable; |
| 177 | vu4 pullup_enable; |
| 178 | vu4 pullup_status; |
| 179 | vu4 __4; |
| 180 | vu4 select_a; |
| 181 | vu4 select_b; |
| 182 | vu4 select_status; |
| 183 | vu4 __5[9]; |
| 184 | vu4 write_enable; |
| 185 | vu4 write_disable; |
| 186 | vu4 write_status; |
| 187 | } AT91PIO; |
| 188 | |
| 189 | #define AT91PIOA_ADDR ((AT91PIO*) BASE_PIOA) |
| 190 | #if AT91_SAM7X |
| 191 | #define AT91PIOB_ADDR ((AT91PIO*) BASE_PIOB) |
| 192 | #endif |
| 193 | |
| 194 | typedef struct |
| 195 | { |
| 196 | vu4 SCER; |
| 197 | vu4 SCDR; |
| 198 | vu4 SCSR; |
| 199 | vu4 __0; |
| 200 | vu4 PCER; |
| 201 | vu4 PCDR; |
| 202 | vu4 PCSR; |
| 203 | vu4 __1; |
| 204 | vu4 MOR; |
| 205 | vu4 MCFR; |
| 206 | vu4 __2; |
| 207 | vu4 PLLR; |
| 208 | vu4 MCKR; |
| 209 | vu4 __3[2]; |
| 210 | vu4 PCK0; |
| 211 | vu4 PCK1; |
| 212 | vu4 PCK2; |
| 213 | } AT91PMC; |
| 214 | |
| 215 | #define AT91PMC_ADDR ((AT91PMC*) BASE_PMC) |
| 216 | |
| 217 | /* PMC_SCER/SCDR */ |
| 218 | #define PMC_PCK 0x00000001 |
| 219 | #define PMC_UDP 0x00000080 |
| 220 | #define PMC_PCK0 0x00000100 |
| 221 | #define PMC_PCK1 0x00000200 |
| 222 | #define PMC_PCK2 0x00000400 |
| 223 | |
| 224 | typedef struct |
| 225 | { |
| 226 | vu4 CR; |
| 227 | vu4 MR; |
| 228 | vu4 RDR; |
| 229 | vu4 TDR; |
| 230 | vu4 SR; |
| 231 | vu4 IER; |
| 232 | vu4 IDR; |
| 233 | vu4 IMR; |
| 234 | vu4 __0[4]; |
| 235 | vu4 CSR0; |
| 236 | vu4 CSR1; |
| 237 | vu4 CSR2; |
| 238 | vu4 CSR3; |
| 239 | } AT91SPI; |
| 240 | |
| 241 | #define AT91SPI0_ADDR ((AT91SPI*) BASE_SPI0) |
| 242 | #if AT91_SAM7X |
| 243 | #define AT91SPI1_ADDR ((AT91SPI*) BASE_SPI0) |
| 244 | #endif |
| 245 | |
| 246 | /* CR bits */ |
| 247 | #define SPI_SPIEN 0x00000001 |
| 248 | #define SPI_SPIDIS 0x00000002 |
| 249 | #define SPI_SWRST 0x00000080 |
| 250 | #define SPI_LASTXFER 0x01000000 |
| 251 | |
| 252 | /* MR bits */ |
| 253 | #define SPI_MSTR 0x00000001 |
| 254 | #define SPI_PS 0x00000002 |
| 255 | #define SPI_PCSDEC 0x00000004 |
| 256 | #define SPI_MODFDIS 0x00000010 |
| 257 | #define SPI_LLB 0x00000080 |
| 258 | #define SPI_DLYBCS(n) (((n) & 0xff) << 24) |
| 259 | #define SPI_PCS0 0x000e0000 |
| 260 | #define SPI_PCS1 0x000d0000 |
| 261 | #define SPI_PCS2 0x000b0000 |
| 262 | #define SPI_PCS3 0x00070000 |
| 263 | |
| 264 | /* SR bits */ |
| 265 | #define SPI_RDRF 0x00000001 /* recv data reg full */ |
| 266 | #define SPI_TDRE 0x00000002 /* xmit data reg empty */ |
| 267 | #define SPI_MODF 0x00000004 /* mode fault error */ |
| 268 | #define SPI_OVRES 0x00000008 /* overrun error */ |
| 269 | #define SPI_ENDRX 0x00000010 /* end of rx buffer */ |
| 270 | #define SPI_ENDTX 0x00000020 /* end of tx buffer */ |
| 271 | #define SPI_RXBUFF 0x00000040 /* rx buffer full */ |
| 272 | #define SPI_TXBUFE 0x00000080 /* tx buffer empty */ |
| 273 | #define SPI_NSSR 0x00000100 /* rising edge on NSS */ |
| 274 | #define SPI_TXEMPTY 0x00000200 /* transmission regs empty */ |
| 275 | #define SPI_SPIENS 0x00010000 |
| 276 | |
| 277 | typedef struct |
| 278 | { |
| 279 | vu4 FRM_NUM; |
| 280 | vu4 GLB_STAT; |
| 281 | vu4 FADDR; |
| 282 | vu4 __0; |
| 283 | vu4 IER; |
| 284 | vu4 IDR; |
| 285 | vu4 IMR; |
| 286 | vu4 ISR; |
| 287 | vu4 ICR; |
| 288 | vu4 __1; |
| 289 | vu4 RST_EP; |
| 290 | vu4 __2; |
| 291 | vu4 CSR0; |
| 292 | vu4 CSR1; |
| 293 | vu4 CSR2; |
| 294 | vu4 CSR3; |
| 295 | vu4 __3[4]; |
| 296 | vu4 FDR0; |
| 297 | vu4 FDR1; |
| 298 | vu4 FDR2; |
| 299 | vu4 FDR3; |
| 300 | vu4 __4[5]; |
| 301 | vu4 TXVC; |
| 302 | } AT91UDP; |
| 303 | |
| 304 | #define AT91UDP_ADDR ((AT91UDP*) BASE_UDP) |
| 305 | |
| 306 | // GLB_STAT bits |
| 307 | #define UDP_FADDEN 0x00000001 |
| 308 | #define UDP_CONFG 0x00000002 |
| 309 | #define UDP_ESR 0x00000004 |
| 310 | #define UDP_RSMINPR 0x00000008 |
| 311 | #define UDP_RMWUPE 0x00000010 |
| 312 | |
| 313 | // FADDR bits |
| 314 | #define UDP_FEN 0x00000100 |
| 315 | |
| 316 | // interrupt bits |
| 317 | #define UDP_EP0INT 0x00000001 |
| 318 | #define UDP_EP1INT 0x00000002 |
| 319 | #define UDP_EP2INT 0x00000004 |
| 320 | #define UDP_EP3INT 0x00000008 |
| 321 | #define UDP_RXSUSP 0x00000100 |
| 322 | #define UDP_RXRSM 0x00000200 |
| 323 | #define UDP_EXTRSM 0x00000400 |
| 324 | #define UDP_SOFINT 0x00000800 |
| 325 | #define UDP_ENDBUSRES 0x00001000 |
| 326 | #define UDP_WAKEUP 0x00002000 |
| 327 | |
| 328 | // RST_EP bits |
| 329 | #define UDP_EP0 0x00000001 |
| 330 | #define UDP_EP1 0x00000002 |
| 331 | #define UDP_EP2 0x00000004 |
| 332 | #define UDP_EP3 0x00000008 |
| 333 | |
| 334 | // CSR bits |
| 335 | #define UDP_TXCOMP 0x00000001 |
| 336 | #define UDP_RX_DATA_BK0 0x00000002 |
| 337 | #define UDP_RXSETUP 0x00000004 |
| 338 | #define UDP_STALLSENT 0x00000008 |
| 339 | #define UDP_ISOERROR 0x00000008 |
| 340 | #define UDP_TXPKTRDY 0x00000010 |
| 341 | #define UDP_FORCESTALL 0x00000020 |
| 342 | #define UDP_RX_DATA_BK1 0x00000040 |
| 343 | #define UDP_DIR 0x00000080 |
| 344 | |
| 345 | #define UDP_DTGL 0x00000800 |
| 346 | #define UDP_EPEDS 0x00008000 |
| 347 | |
| 348 | #define UDP_TYPE_CONTROL 0x00000000 |
| 349 | #define UDP_TYPE_ISOCH_OUT 0x00000100 |
| 350 | #define UDP_TYPE_BULK_OUT 0x00000200 |
| 351 | #define UDP_TYPE_INT_OUT 0x00000300 |
| 352 | #define UDP_TYPE_ISOCH_IN 0x00000500 |
| 353 | #define UDP_TYPE_BULK_IN 0x00000600 |
| 354 | #define UDP_TYPE_INT_IN 0x00000700 |
| 355 | |
| 356 | typedef struct |
| 357 | { |
| 358 | vu4 SMR[32]; |
| 359 | vu4 SVR[32]; |
| 360 | vu4 IVR; |
| 361 | vu4 FVR; |
| 362 | vu4 ISR; |
| 363 | vu4 IPR; |
| 364 | vu4 IMR; |
| 365 | vu4 CISR; |
| 366 | vu4 __0[2]; |
| 367 | vu4 IECR; |
| 368 | vu4 IDCR; |
| 369 | vu4 ICCR; |
| 370 | vu4 ISCR; |
| 371 | vu4 EOICR; |
| 372 | vu4 SPU; |
| 373 | vu4 DCR; |
| 374 | vu4 __1; |
| 375 | vu4 FFER; |
| 376 | vu4 FFDR; |
| 377 | vu4 FFSR; |
| 378 | } AT91AIC; |
| 379 | |
| 380 | #define AT91AIC_ADDR ((AT91AIC*) BASE_AIC) |
| 381 | |
| 382 | |
| 383 | typedef struct |
| 384 | { |
| 385 | vu4 CR; |
| 386 | vu4 MR; |
| 387 | vu4 IER; |
| 388 | vu4 IDR; |
| 389 | vu4 IMD; |
| 390 | vu4 CSR; |
| 391 | vu4 RHR; |
| 392 | vu4 THR; |
| 393 | vu4 BRGR; |
| 394 | vu4 RTOR; |
| 395 | vu4 TTGR; |
| 396 | vu4 __0[5]; |
| 397 | vu4 FIDI; |
| 398 | vu4 NER; |
| 399 | vu4 __1; |
| 400 | vu4 IF; |
| 401 | vu4 MAN; |
| 402 | } AT91USART; |
| 403 | |
| 404 | #define AT91USART0_ADDR ((AT91USART*) 0xFFFC0000) |
| 405 | #define AT91USART1_ADDR ((AT91USART*) 0xFFFC4000) |
| 406 | |
| 407 | /* CR */ |
| 408 | #define USART_RSTRX 0x00000004 |
| 409 | #define USART_RSTTX 0x00000008 |
| 410 | #define USART_RXEN 0x00000010 |
| 411 | #define USART_RXDIS 0x00000020 |
| 412 | #define USART_TXEN 0x00000040 |
| 413 | #define USART_TXDIS 0x00000080 |
| 414 | #define USART_RSTSTA 0x00000100 |
| 415 | #define USART_STTBRK 0x00000200 |
| 416 | #define USART_STPBRK 0x00000400 |
| 417 | #define USART_STTTO 0x00000800 |
| 418 | #define USART_SENDA 0x00001000 |
| 419 | #define USART_RSTIT 0x00002000 |
| 420 | #define USART_RSTNACK 0x00004000 |
| 421 | #define USART_RETTO 0x00008000 |
| 422 | #define USART_DTREN 0x00010000 |
| 423 | #define USART_DTRDIS 0x00020000 |
| 424 | #define USART_RTSEN 0x00040000 |
| 425 | #define USART_RTSDIS 0x00080000 |
| 426 | |
| 427 | /* MR */ |
| 428 | #define USART_MODE_NORMAL 0x00000000 |
| 429 | #define USART_MODE_RS485 0x00000001 |
| 430 | #define USART_MODE_HWHS 0x00000002 |
| 431 | #define USART_MODE_MODEM 0x00000003 |
| 432 | #define USART_MODE_ISO7816T0 0x00000004 |
| 433 | #define USART_MODE_ISO7816T1 0x00000006 |
| 434 | #define USART_MODE_IRDA 0x00000008 |
| 435 | |
| 436 | #define USART_CLK_MCK 0x00000000 |
| 437 | #define USART_CLK_MCK_DIV 0x00000010 |
| 438 | #define USART_CLK_SCK 0x00000030 |
| 439 | |
| 440 | #define USART_CHRL_5BITS 0x00000000 |
| 441 | #define USART_CHRL_6BITS 0x00000040 |
| 442 | #define USART_CHRL_7BITS 0x00000080 |
| 443 | #define USART_CHRL_8BITS 0x000000C0 |
| 444 | |
| 445 | #define USART_SYNCHRONOUS 0x00000100 |
| 446 | |
| 447 | #define USART_PARITY_EVEN 0x00000000 |
| 448 | #define USART_PARITY_ODD 0x00000200 |
| 449 | #define USART_PARITY_SPACE 0x00000400 |
| 450 | #define USART_PARITY_MARK 0x00000600 |
| 451 | #define USART_PARITY_NONE 0x00000800 |
| 452 | #define USART_PARITY_MULTIDROP 0x00000C00 |
| 453 | |
| 454 | #define USART_1STOP 0x00000000 |
| 455 | #define USART_1X5STOP 0x00001000 |
| 456 | #define USART_2STOP 0x00002000 |
| 457 | |
| 458 | #define USART_CHMODE_NORMAL 0x00000000 |
| 459 | #define USART_CHMODE_ECHO 0x00004000 |
| 460 | #define USART_CHMODE_LLOOP 0x00008000 |
| 461 | #define USART_CHMODE_RLOOP 0x0000C000 |
| 462 | |
| 463 | #define USART_MSBF 0x00010000 |
| 464 | #define USART_MODE9 0x00020000 |
| 465 | #define USART_CLKO 0x00040000 |
| 466 | #define USART_OVER 0x00080000 |
| 467 | #define USART_INACK 0x00100000 |
| 468 | #define USART_DSNACK 0x00200000 |
| 469 | #define USART_VAR_SYNC 0x00400000 |
| 470 | |
| 471 | #define USART_FILTER 0x10000000 |
| 472 | #define USART_MAN 0x20000000 |
| 473 | #define USART_ONEBIT 0x80000000 |
| 474 | |
| 475 | /* CSR */ |
| 476 | #define USART_RXRDY 0x00000001 |
| 477 | #define USART_TXRDY 0x00000002 |
| 478 | #define USART_RXBRK 0x00000004 |
| 479 | #define USART_ENDRX 0x00000008 |
| 480 | #define USART_ENDTX 0x00000010 |
| 481 | #define USART_OVRE 0x00000020 |
| 482 | #define USART_FRAME 0x00000040 |
| 483 | #define USART_PARE 0x00000080 |
| 484 | #define USART_TIMEOUT 0x00000100 |
| 485 | #define USART_TXEMPTY 0x00000200 |
| 486 | #define USART_ITERATION 0x00000400 |
| 487 | #define USART_TXBUFE 0x00000800 |
| 488 | #define USART_RXBUFF 0x00001000 |
| 489 | #define USART_NACK 0x00002000 |
| 490 | |
| 491 | |
| 492 | typedef struct |
| 493 | { |
| 494 | vu4 CR; |
| 495 | vu4 SR; |
| 496 | vu4 MR; |
| 497 | } AT91RSTC; |
| 498 | |
| 499 | #define RSTC_KEY 0xA5000000 |
| 500 | |
| 501 | /* cr */ |
| 502 | #define RSTC_PROCRST 0x00000001 |
| 503 | #define RSTC_PERRST 0x00000004 |
| 504 | #define RSTC_EXTRST 0x00000008 |
| 505 | |
| 506 | /* sr */ |
| 507 | #define RSTC_URSTS 0x00000001 |
| 508 | #define RSTC_BODSTS 0x00000002 |
| 509 | #define RSTC_RSTTYP_MASK 0x00000070 |
| 510 | #define RSTC_RSTTYP_COLD 0x00000000 |
| 511 | #define RSTC_RSTTYP_WATCHDOG 0x00000020 |
| 512 | #define RSTC_RSTTYP_SOFTWARE 0x00000030 |
| 513 | #define RSTC_RSTTYP_NRST_PIN 0x00000040 |
| 514 | #define RSTC_RSTTYP_BROWNOUT 0x00000060 |
| 515 | #define RSTC_NRSTL 0x00010000 |
| 516 | #define RSTC_SRCMP 0x00020000 |
| 517 | |
| 518 | /* mr */ |
| 519 | #define RSTC_URSTEN 0x00000001 |
| 520 | #define RSTC_URSTIEN 0x00000010 |
| 521 | #define RSTC_ERSTL(n) (((n) & 0xf) << 8) |
| 522 | #define RSTC_BODIEN 0x00010000 |
| 523 | |
| 524 | #define AT91RSTC_ADDR ((AT91RSTC*) BASE_RSTC) |
| 525 | |
| 526 | #if AT91_SAM7X |
| 527 | |
| 528 | typedef struct |
| 529 | { |
| 530 | vu4 NCR; |
| 531 | vu4 NCFG; |
| 532 | vu4 NSR; |
| 533 | vu4 __0; |
| 534 | |
| 535 | vu4 __1; |
| 536 | vu4 TSR; |
| 537 | vu4 RBQP; |
| 538 | vu4 TBQP; |
| 539 | |
| 540 | vu4 RSR; |
| 541 | vu4 ISR; |
| 542 | vu4 IER; |
| 543 | vu4 IDR; |
| 544 | |
| 545 | vu4 IMR; |
| 546 | vu4 MAN; |
| 547 | vu4 PTR; |
| 548 | vu4 PFR; |
| 549 | |
| 550 | vu4 FTO; |
| 551 | vu4 SCF; |
| 552 | vu4 MCF; |
| 553 | vu4 FRO; |
| 554 | |
| 555 | vu4 FCSE; |
| 556 | vu4 ALE; |
| 557 | vu4 DTF; |
| 558 | vu4 LCOL; |
| 559 | |
| 560 | vu4 ECOL; |
| 561 | vu4 TUND; |
| 562 | vu4 CSE; |
| 563 | vu4 RRE; |
| 564 | |
| 565 | vu4 ROV; |
| 566 | vu4 RSE; |
| 567 | vu4 ELE; |
| 568 | vu4 RJA; |
| 569 | |
| 570 | vu4 USF; |
| 571 | vu4 STE; |
| 572 | vu4 RLE; |
| 573 | vu4 __2; |
| 574 | |
| 575 | vu4 HRB; |
| 576 | vu4 HRT; |
| 577 | vu4 SA1B; |
| 578 | vu4 SA1T; |
| 579 | |
| 580 | vu4 SA2B; |
| 581 | vu4 SA2T; |
| 582 | vu4 SA3B; |
| 583 | vu4 SA3T; |
| 584 | |
| 585 | vu4 SA4B; |
| 586 | vu4 SA5T; |
| 587 | vu4 TID; |
| 588 | vu4 __3; |
| 589 | |
| 590 | vu4 USRIO; |
| 591 | } AT91EMAC; |
| 592 | |
| 593 | |
| 594 | #define NCR_LB 0x00000001 |
| 595 | #define NCR_LLB 0x00000002 |
| 596 | #define NCR_RE 0x00000004 |
| 597 | #define NCR_TE 0x00000008 |
| 598 | #define NCR_MPE 0x00000010 |
| 599 | #define NCR_CLRSTAT 0x00000020 |
| 600 | #define NCR_INCSTAT 0x00000040 |
| 601 | #define NCR_WESTAT 0x00000080 |
| 602 | #define NCR_BP 0x00000100 |
| 603 | #define NCR_TSTART 0x00000200 |
| 604 | #define NCR_THALT 0x00000400 |
| 605 | |
| 606 | #define NCFG_SPD 0x00000001 |
| 607 | #define NCFG_FD 0x00000002 |
| 608 | #define NCFG_JFRAME 0x00000008 |
| 609 | #define NCFG_CAF 0x00000010 |
| 610 | #define NCFG_NBC 0x00000020 |
| 611 | #define NCFG_MTI 0x00000040 |
| 612 | #define NCFG_UNI 0x00000080 |
| 613 | #define NCFG_BIG 0x00000100 |
| 614 | #define NCFG_CLK_d8 0x00000000 |
| 615 | #define NCFG_CLK_d16 0x00000400 |
| 616 | #define NCFG_CLK_d32 0x00000800 |
| 617 | #define NCFG_CLK_d64 0x00000C00 |
| 618 | #define NCFG_RTY 0x00001000 |
| 619 | #define NCFG_PAE 0x00002000 |
| 620 | #define NCFG_RBOF_0 0x00000000 |
| 621 | #define NCFG_RBOF_1 0x00004000 |
| 622 | #define NCFG_RBOF_2 0x00008000 |
| 623 | #define NCFG_RBOF_3 0x0000C000 |
| 624 | #define NCFG_RLCE 0x00010000 |
| 625 | #define NCFG_DRFCS 0x00020000 |
| 626 | #define NCFG_EFRHD 0x00040000 |
| 627 | #define NCFG_IRXFCS 0x00080000 |
| 628 | |
| 629 | #define NSR_MDIO 0x00000002 |
| 630 | #define NSR_IDLE 0x00000004 |
| 631 | |
| 632 | #define TSR_UBR 0x00000001 |
| 633 | #define TSR_COL 0x00000002 |
| 634 | #define TSR_RLE 0x00000004 |
| 635 | #define TSR_TGO 0x00000008 |
| 636 | #define TSR_BEX 0x00000010 |
| 637 | #define TSR_COMP 0x00000020 |
| 638 | #define TSR_UND 0x00000040 |
| 639 | |
| 640 | #define RSR_BNA 0x00000001 |
| 641 | #define RSR_REC 0x00000002 |
| 642 | #define RSR_OVR 0x00000004 |
| 643 | |
| 644 | #define ISR_MFD 0x00000001 |
| 645 | #define ISR_RCOMP 0x00000002 |
| 646 | #define ISR_RXUBR 0x00000004 |
| 647 | #define ISR_TXUBR 0x00000008 |
| 648 | #define ISR_TUND 0x00000010 |
| 649 | #define ISR_RLE 0x00000020 |
| 650 | #define ISR_TXERR 0x00000040 |
| 651 | #define ISR_TCOMP 0x00000080 |
| 652 | #define ISR_ROVR 0x00000400 |
| 653 | #define ISR_HRESP 0x00000800 |
| 654 | #define ISR_PFR 0x00001000 |
| 655 | #define ISR_PTZ 0x00002000 |
| 656 | |
| 657 | #define USRIO_RMII 0x00000001 |
| 658 | #define USRIO_CLKEN 0x00000002 |
| 659 | |
| 660 | #define AT91EMAC_ADDR ((AT91EMAC*) BASE_EMAC) |
| 661 | |
| 662 | |
| 663 | typedef struct |
| 664 | { |
| 665 | vu4 addr; |
| 666 | vu4 info; |
| 667 | } emac_xmit_entry; |
| 668 | |
| 669 | #define XMIT_USED 0x80000000 |
| 670 | #define XMIT_WRAP 0x40000000 |
| 671 | #define XMIT_ERR_RETRY 0x20000000 |
| 672 | #define XMIT_ERR_UNDERRUN 0x10000000 |
| 673 | #define XMIT_ERR_EXHAUSTED 0x08000000 |
| 674 | #define XMIT_NO_CRC 0x00010000 |
| 675 | #define XMIT_LAST 0x00008000 |
| 676 | #define XMIT_LENGTH(n) ((n) & 0x3FF) |
| 677 | |
| 678 | |
| 679 | /* CAN Registers */ |
| 680 | |
| 681 | |
| 682 | typedef struct |
| 683 | { |
| 684 | vu4 MMR; /* Mailbox Mode Register */ |
| 685 | vu4 MAM; /* Mailbox Acceptance Mask Register */ |
| 686 | vu4 MID; /* Mailbox ID Register */ |
| 687 | vu4 MFID; /* Mailbox Family ID Register */ |
| 688 | vu4 MSR; /* Mailbox Status Register */ |
| 689 | vu4 MDL; /* Mailbox Data Low Register */ |
| 690 | vu4 MDH; /* Mailbox Data High Register */ |
| 691 | vu4 MCR; /* Mailbox Control Register */ |
| 692 | } AT91CAN_MAILBOX; |
| 693 | |
| 694 | typedef struct |
| 695 | { |
| 696 | vu4 MR; /* Mode Register */ |
| 697 | vu4 IER; /* Interrupt Enable Register */ |
| 698 | vu4 IDR; /* Interrupt Disable Register */ |
| 699 | vu4 IMR; /* Interrupt Mask Register */ |
| 700 | vu4 SR; /* Status Register */ |
| 701 | vu4 BR; /* Baudrate Register */ |
| 702 | vu4 TIM; /* Timer Register */ |
| 703 | vu4 TIMESTP; /* Timestamp Register */ |
| 704 | vu4 ECR; /* Error Counter Register */ |
| 705 | vu4 TCR; /* Transfer Command Register */ |
| 706 | vu4 ACR; /* Abort Command Register */ |
| 707 | |
| 708 | vu4 __0[53]; /* 0x002c - 0x0100 is undefined */ |
| 709 | vu4 __1[63]; /* 0x0200 - 0x01fc is reserved */ |
| 710 | AT91CAN_MAILBOX Mailbox[8]; |
| 711 | } AT91CAN; |
| 712 | |
| 713 | #define CAN_CANEN 0x00000001 /* CAN Controller Enable */ |
| 714 | #define CAN_LPM 0x00000002 /* Enable Low Power Mode */ |
| 715 | #define CAN_ABM 0x00000004 /* Enable Autoband/Listen Mode */ |
| 716 | #define CAN_OVL 0x00000008 /* Enable Overload Frame */ |
| 717 | #define CAN_TEOF 0x00000010 /* Timestamp Messages at each Frame */ |
| 718 | #define CAN_TTM 0x00000020 /* Enable Time Trigger Mode */ |
| 719 | #define CAN_TIMFRZ 0x00000040 /* Enable Timer Freeze */ |
| 720 | #define CAN_DRPT 0x00000080 /* Disable Repeat */ |
| 721 | |
| 722 | #define CAN_MB(x) (0x00000001 << x) /* Enable Interrupt Enable */ |
| 723 | #define CAN_ERRA 0x00010000 /* Enable Error Active Mode Interrupt */ |
| 724 | #define CAN_WARN 0x00020000 /* Enable Warning Limit Interrupt */ |
| 725 | #define CAN_ERRP 0x00040000 /* Enable Passive mode interrupt */ |
| 726 | #define CAN_BOFF 0x00080000 /* Enable Bus-off mode interrupt */ |
| 727 | #define CAN_SLEEP 0x00100000 /* Enable Sleep Interrupt */ |
| 728 | #define CAN_WAKEUP 0x00200000 /* Enable Wakeup Interrupt */ |
| 729 | #define CAN_TOVF 0x00400000 /* Enable Timer Overflow Interrupt */ |
| 730 | #define CAN_TSTP 0x00800000 /* Enable TimeStamp Interrupt */ |
| 731 | #define CAN_CERR 0x01000000 /* Enable CRC Error Interrupt */ |
| 732 | #define CAN_SERR 0x02000000 /* Enable Stuffing Error Interrupt */ |
| 733 | #define CAN_AERR 0x04000000 /* Enable Acknowledgement Error Int */ |
| 734 | #define CAN_FERR 0x08000000 /* Enable Form Error Interrupt */ |
| 735 | #define CAN_BERR 0x10000000 /* Enable Bit Error Interrupt */ |
| 736 | |
| 737 | #define CAN_RBSY 0x20000000 /* Receiver Busy */ |
| 738 | #define CAN_TBSY 0x40000000 /* Transmitter Busy */ |
| 739 | #define CAN_OVLSY 0x80000000 /* Overload Busy */ |
| 740 | |
| 741 | /* Can Baudrate Regiister */ |
| 742 | |
| 743 | #define CAN_PHASE2(x) (x) |
| 744 | #define CAN_PHASE2_MASK 0x07 |
| 745 | #define CAN_PHASE1(x) (x<<4) |
| 746 | #define CAN_PHASE1_MASK (0x07 << 4) |
| 747 | #define CAN_PROPAG(x) (x<<8) |
| 748 | #define CAN_PROPAG_MASK (0x07 << 8) |
| 749 | #define CAN_SJW(x) (x<<12) |
| 750 | #define CAN_SJW_MASK(x) (0x03 << 12) |
| 751 | #define CAN_BRP(x) (x<<16) |
| 752 | #define CAN_BRP_MASK (0x7f << 16) |
| 753 | #define CAN_SMP 0x01000000 /* Sampling Mode */ |
| 754 | |
| 755 | /* CAN Transfer Command Register */ |
| 756 | |
| 757 | #define TCR_TIMRST 0x80000000 /* Timer Reset */ |
| 758 | |
| 759 | /* CAN Message Mode Register */ |
| 760 | |
| 761 | #define CAN_MTIMEMARK(x) (0x0000001 << x) |
| 762 | #define CAN_PRIOR(x) (x << 16) |
| 763 | #define CAN_MOT(x) (x << 24) |
| 764 | |
| 765 | #define CAN_MIDVB(x) (x) |
| 766 | #define CAN_MIDVA(x) (x << 18) |
| 767 | #define CAN_MIDE 0x20000000 |
| 768 | |
| 769 | |
| 770 | /* CAN MSRx */ |
| 771 | |
| 772 | /* These are receive, so pass in the value of the register... */ |
| 773 | |
| 774 | #define CAN_MTIMESTAMP(x) (x & 0x0000ffff) |
| 775 | #define CAN_MDLC(x) ( (x >> 16) & 0x0f) /* Mailbox code length */ |
| 776 | #define CAN_MRTR 0x00100000 /* Mailbox Remote Trx Request*/ |
| 777 | #define CAN_MABT 0x00400000 /* Mailbox Message Abort */ |
| 778 | #define CAN_MRDY 0x00800000 /* Mailbox Ready */ |
| 779 | #define CAN_MMI 0x01000000 /* Mailbox Message Ignored */ |
| 780 | |
| 781 | /* Message Control Register */ |
| 782 | |
| 783 | //#define CAN_MDLC(x) (x<<16) /* Mailbox Data Length Code */ |
| 784 | #define CAN_MACR (0x01 << 22) /* Abort Request */ |
| 785 | #define CAN_MTCR (0x01 << 23) /* Mailbox Transfer Command */ |
| 786 | |
| 787 | |
| 788 | #define AT91CAN_ADDR ((AT91CAN*) BASE_CAN) |
| 789 | |
| 790 | |
| 791 | |
| 792 | #endif |
| 793 | |
| 794 | #endif |