Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <mipi_dsi.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 32 | #include <platform/iomap.h> |
| 33 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 34 | #if (DISPLAY_TYPE_MDSS == 0) |
| 35 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 36 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
| 37 | #endif |
| 38 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 39 | #define MMSS_DSI_CLKOUT_TIMING_CTRL 0x0c4 |
| 40 | #define MMSS_DSI_PHY_TIMING_CTRL_0 0x0140 |
| 41 | #define MMSS_DSI_PHY_CTRL_0 0x0170 |
| 42 | #define MMSS_DSI_PHY_CTRL_1 0x0174 |
| 43 | #define MMSS_DSI_PHY_CTRL_2 0x0178 |
| 44 | #define MMSS_DSI_PHY_STRENGTH_CTRL_0 0x0184 |
| 45 | #define MMSS_DSI_PHY_STRENGTH_CTRL_1 0x0188 |
| 46 | #define MMSS_DSI_PHY_BIST_CTRL_0 0x01b4 |
| 47 | #define MMSS_DSI_PHY_GLBL_TEST_CTRL 0x01d4 |
| 48 | #define MMSS_DSI_PHY_LDO_CTRL 0x01dc |
| 49 | |
| 50 | #define TOTAL_TIMING_CTRL_CONFIG 12 |
| 51 | #define TOTAL_BIST_CTRL_CONFIG 6 |
| 52 | /* 4 data lanes and 1 clock lanes */ |
| 53 | #define TOTAL_LANE_COUNT 5 |
| 54 | #define CONFIG_REG_FOR_EACH_LANE 9 |
| 55 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 56 | static void mipi_dsi_calibration(void) |
| 57 | { |
| 58 | uint32_t i = 0; |
| 59 | uint32_t term_cnt = 5000; |
| 60 | int32_t cal_busy = readl(MIPI_DSI_BASE + 0x550); |
| 61 | |
| 62 | /* DSI1_DSIPHY_REGULATOR_CAL_PWR_CFG */ |
| 63 | writel(0x01, MIPI_DSI_BASE + 0x0518); |
| 64 | |
| 65 | /* DSI1_DSIPHY_CAL_SW_CFG2 */ |
| 66 | writel(0x0, MIPI_DSI_BASE + 0x0534); |
| 67 | /* DSI1_DSIPHY_CAL_HW_CFG1 */ |
| 68 | writel(0x5a, MIPI_DSI_BASE + 0x053c); |
| 69 | /* DSI1_DSIPHY_CAL_HW_CFG3 */ |
| 70 | writel(0x10, MIPI_DSI_BASE + 0x0544); |
| 71 | /* DSI1_DSIPHY_CAL_HW_CFG4 */ |
| 72 | writel(0x01, MIPI_DSI_BASE + 0x0548); |
| 73 | /* DSI1_DSIPHY_CAL_HW_CFG0 */ |
| 74 | writel(0x01, MIPI_DSI_BASE + 0x0538); |
| 75 | |
| 76 | /* DSI1_DSIPHY_CAL_HW_TRIGGER */ |
| 77 | writel(0x01, MIPI_DSI_BASE + 0x0528); |
| 78 | |
| 79 | /* DSI1_DSIPHY_CAL_HW_TRIGGER */ |
| 80 | writel(0x00, MIPI_DSI_BASE + 0x0528); |
| 81 | |
| 82 | cal_busy = readl(MIPI_DSI_BASE + 0x550); |
| 83 | while (cal_busy & 0x10) { |
| 84 | i++; |
| 85 | if (i > term_cnt) { |
| 86 | dprintf(CRITICAL, "DSI1 PHY REGULATOR NOT READY," |
| 87 | "exceeded polling TIMEOUT!\n"); |
| 88 | break; |
| 89 | } |
| 90 | cal_busy = readl(MIPI_DSI_BASE + 0x550); |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo) |
| 95 | { |
| 96 | struct mipi_dsi_phy_ctrl *pd; |
| 97 | uint32_t i, off = 0; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 98 | int mdp_rev; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 99 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 100 | mdp_rev = mdp_get_revision(); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 101 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 102 | if (MDP_REV_303 == mdp_rev || MDP_REV_41 == mdp_rev) { |
| 103 | writel(0x00000001, DSIPHY_SW_RESET); |
| 104 | writel(0x00000000, DSIPHY_SW_RESET); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 105 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 106 | pd = (pinfo->dsi_phy_config); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 107 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 108 | off = 0x02cc; /* regulator ctrl 0 */ |
| 109 | for (i = 0; i < 4; i++) { |
| 110 | writel(pd->regulator[i], MIPI_DSI_BASE + off); |
| 111 | off += 4; |
| 112 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 113 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 114 | off = 0x0260; /* phy timig ctrl 0 */ |
| 115 | for (i = 0; i < 11; i++) { |
| 116 | writel(pd->timing[i], MIPI_DSI_BASE + off); |
| 117 | off += 4; |
| 118 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 119 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 120 | /* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing |
| 121 | length should > data lane HS timing length */ |
| 122 | writel(0xa1e, DSI_CLKOUT_TIMING_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 123 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 124 | off = 0x0290; /* ctrl 0 */ |
| 125 | for (i = 0; i < 4; i++) { |
| 126 | writel(pd->ctrl[i], MIPI_DSI_BASE + off); |
| 127 | off += 4; |
| 128 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 129 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 130 | off = 0x02a0; /* strength 0 */ |
| 131 | for (i = 0; i < 4; i++) { |
| 132 | writel(pd->strength[i], MIPI_DSI_BASE + off); |
| 133 | off += 4; |
| 134 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 135 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 136 | if (1 == pinfo->num_of_lanes) |
| 137 | pd->pll[10] |= 0x8; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 138 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 139 | off = 0x0204; /* pll ctrl 1, skip 0 */ |
| 140 | for (i = 1; i < 21; i++) { |
| 141 | writel(pd->pll[i], MIPI_DSI_BASE + off); |
| 142 | off += 4; |
| 143 | } |
| 144 | |
| 145 | /* pll ctrl 0 */ |
| 146 | writel(pd->pll[0], MIPI_DSI_BASE + 0x200); |
| 147 | writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200); |
| 148 | /* lane swp ctrol */ |
| 149 | if (pinfo->lane_swap) |
| 150 | writel(pinfo->lane_swap, MIPI_DSI_BASE + 0xac); |
| 151 | } else { |
| 152 | writel(0x0001, MIPI_DSI_BASE + 0x128); /* start phy sw reset */ |
| 153 | writel(0x0000, MIPI_DSI_BASE + 0x128); /* end phy w reset */ |
| 154 | writel(0x0003, MIPI_DSI_BASE + 0x500); /* regulator_ctrl_0 */ |
| 155 | writel(0x0001, MIPI_DSI_BASE + 0x504); /* regulator_ctrl_1 */ |
| 156 | writel(0x0001, MIPI_DSI_BASE + 0x508); /* regulator_ctrl_2 */ |
| 157 | writel(0x0000, MIPI_DSI_BASE + 0x50c); /* regulator_ctrl_3 */ |
| 158 | writel(0x0100, MIPI_DSI_BASE + 0x510); /* regulator_ctrl_4 */ |
| 159 | |
| 160 | pd = (pinfo->dsi_phy_config); |
| 161 | |
| 162 | off = 0x0480; /* strength 0 - 2 */ |
| 163 | for (i = 0; i < 3; i++) { |
| 164 | writel(pd->strength[i], MIPI_DSI_BASE + off); |
| 165 | off += 4; |
| 166 | } |
| 167 | |
| 168 | off = 0x0470; /* ctrl 0 - 3 */ |
| 169 | for (i = 0; i < 4; i++) { |
| 170 | writel(pd->ctrl[i], MIPI_DSI_BASE + off); |
| 171 | off += 4; |
| 172 | } |
| 173 | |
| 174 | off = 0x0500; /* regulator ctrl 0 - 4 */ |
| 175 | for (i = 0; i < 5; i++) { |
| 176 | writel(pd->regulator[i], MIPI_DSI_BASE + off); |
| 177 | off += 4; |
| 178 | } |
| 179 | mipi_dsi_calibration(); |
| 180 | |
| 181 | off = 0x0204; /* pll ctrl 1 - 19, skip 0 */ |
| 182 | for (i = 1; i < 20; i++) { |
| 183 | writel(pd->pll[i], MIPI_DSI_BASE + off); |
| 184 | off += 4; |
| 185 | } |
| 186 | |
| 187 | /* pll ctrl 0 */ |
| 188 | writel(pd->pll[0], MIPI_DSI_BASE + 0x200); |
| 189 | writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200); |
| 190 | |
| 191 | /* Check that PHY is ready */ |
| 192 | while (!(readl(DSIPHY_PLL_RDY) & 0x01)) |
| 193 | udelay(1); |
| 194 | |
| 195 | writel(0x202D, DSI_CLKOUT_TIMING_CTRL); |
| 196 | |
| 197 | off = 0x0440; /* phy timing ctrl 0 - 11 */ |
| 198 | for (i = 0; i < 12; i++) { |
| 199 | writel(pd->timing[i], MIPI_DSI_BASE + off); |
| 200 | off += 4; |
| 201 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 202 | } |
| 203 | return 0; |
| 204 | } |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 205 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 206 | void mdss_dsi_phy_sw_reset(uint32_t ctl_base) |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 207 | { |
| 208 | /* start phy sw reset */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 209 | writel(0x0001, ctl_base + 0x012c); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 210 | udelay(1000); |
| 211 | |
| 212 | /* end phy sw reset */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 213 | writel(0x0000, ctl_base + 0x012c); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 214 | udelay(100); |
| 215 | } |
| 216 | |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame^] | 217 | int mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, uint32_t phy_base) |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 218 | { |
| 219 | /* DSI0 and DSI1 have a common regulator */ |
| 220 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 221 | uint32_t off = 0x0280; /* phy regulator ctrl settings */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 222 | |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame^] | 223 | if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) { |
| 224 | /* Regulator ctrl 0 */ |
| 225 | writel(0x00, DSI0_PHY_BASE + off + (4 * 0)); |
| 226 | /* Regulator ctrl - CAL_PWD_CFG */ |
| 227 | writel(pd->regulator[6], DSI0_PHY_BASE + off + (4 * 6)); |
| 228 | /* Add h/w recommended delay */ |
| 229 | udelay(1000); |
| 230 | /* Regulator ctrl - TEST */ |
| 231 | writel(pd->regulator[5], DSI0_PHY_BASE + off + (4 * 5)); |
| 232 | /* Regulator ctrl 3 */ |
| 233 | writel(pd->regulator[3], DSI0_PHY_BASE + off + (4 * 3)); |
| 234 | /* Regulator ctrl 2 */ |
| 235 | writel(pd->regulator[2], DSI0_PHY_BASE + off + (4 * 2)); |
| 236 | /* Regulator ctrl 1 */ |
| 237 | writel(pd->regulator[1], DSI0_PHY_BASE + off + (4 * 1)); |
| 238 | /* Regulator ctrl 4 */ |
| 239 | writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4)); |
| 240 | /* LDO ctrl */ |
| 241 | if (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103_1) /* 8916/8939 */ |
| 242 | writel(0x05, phy_base + 0x01dc); |
| 243 | else if (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103) /* 8994 */ |
| 244 | writel(0x1d, phy_base + 0x01dc); |
| 245 | else |
| 246 | writel(0x0d, phy_base + 0x01dc); |
| 247 | dmb(); |
| 248 | } else { |
| 249 | /* Regulator ctrl 0 */ |
| 250 | writel(0x00, DSI0_PHY_BASE + off + (4 * 0)); |
| 251 | /* Regulator ctrl - CAL_PWD_CFG */ |
| 252 | writel(pd->regulator[6], DSI0_PHY_BASE + off + (4 * 6)); |
| 253 | /* Add h/w recommended delay */ |
| 254 | udelay(1000); |
| 255 | /* Regulator ctrl 1 */ |
| 256 | writel(pd->regulator[1], DSI0_PHY_BASE + off + (4 * 1)); |
| 257 | /* Regulator ctrl 2 */ |
| 258 | writel(pd->regulator[2], DSI0_PHY_BASE + off + (4 * 2)); |
| 259 | /* Regulator ctrl 3 */ |
| 260 | writel(pd->regulator[3], DSI0_PHY_BASE + off + (4 * 3)); |
| 261 | /* Regulator ctrl 4 */ |
| 262 | writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4)); |
| 263 | /* LDO ctrl */ |
| 264 | writel(0x00, phy_base + 0x01dc); |
| 265 | /* Regulator ctrl 0 */ |
| 266 | writel(pd->regulator[0], DSI0_PHY_BASE + off + (4 * 0)); |
| 267 | dmb(); |
| 268 | } |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 269 | } |
| 270 | |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 271 | int mdss_dsi_v2_phy_init(struct mipi_dsi_panel_config *pinfo, uint32_t ctl_base) |
| 272 | { |
| 273 | struct mdss_dsi_phy_ctrl *pd; |
| 274 | uint32_t i, ln, off = 0, offset; |
| 275 | |
| 276 | pd = pinfo->mdss_dsi_phy_config; |
| 277 | /* DSI PHY configuration */ |
| 278 | off = 0x480; |
| 279 | writel(pd->strength[0], ctl_base + off + (4 * 0)); |
| 280 | writel(pd->strength[1], ctl_base + off + (4 * 2)); |
| 281 | |
| 282 | off = 0x470; |
| 283 | writel(0x10, ctl_base + off + (4 * 3)); |
| 284 | writel(0x5F, ctl_base + off + (4 * 0)); |
| 285 | |
| 286 | off = 0x500; |
Xiaoming Zhou | 7c9e1ee | 2013-07-18 10:51:41 -0400 | [diff] [blame] | 287 | /* use LDO mode */ |
| 288 | writel(0x25, ctl_base + 0x4B0); |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 289 | for (i = 0; i < 5; i++) |
| 290 | writel(pd->regulator[i], ctl_base + off + (4 * i)); |
| 291 | |
| 292 | mipi_dsi_calibration(); |
| 293 | |
| 294 | /* 4 lanes + clk lane configuration */ |
| 295 | /* lane config n * (0 - 4) & DataPath setup */ |
| 296 | for (ln = 0; ln < 5; ln++) { |
| 297 | off = 0x0300 + (ln * 0x40); |
| 298 | for (i = 0; i < 9; i++) { |
| 299 | offset = i + (ln * 9); |
| 300 | writel(pd->laneCfg[offset], ctl_base + off); |
| 301 | dmb(); |
| 302 | off += 4; |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | off = 0x440; |
| 307 | for (i = 0; i < 12; i++) |
| 308 | writel(pd->timing[i], ctl_base + off + (4 * i)); |
| 309 | |
| 310 | if (1 == pinfo->num_of_lanes) |
| 311 | writel(0x8, ctl_base + 0x200 + (4 * 11)); |
| 312 | |
| 313 | |
| 314 | if (pinfo->lane_swap) |
| 315 | writel(pinfo->lane_swap, ctl_base + 0x0ac); |
| 316 | |
| 317 | /* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing |
| 318 | length should > data lane HS timing length */ |
| 319 | writel(0x41b, ctl_base + 0x0c0); |
| 320 | return 0; |
| 321 | } |
| 322 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 323 | static int mdss_dsi_phy_28nm_init(struct mipi_dsi_panel_config *pinfo, |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 324 | uint32_t ctl_base, uint32_t phy_base) |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 325 | { |
| 326 | struct mdss_dsi_phy_ctrl *pd; |
| 327 | uint32_t i, off = 0, ln, offset; |
| 328 | |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 329 | if (mdp_get_revision() == MDP_REV_304) |
| 330 | return mdss_dsi_v2_phy_init(pinfo, ctl_base); |
| 331 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 332 | pd = (pinfo->mdss_dsi_phy_config); |
| 333 | |
| 334 | /* Strength ctrl 0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 335 | writel(pd->strength[0], phy_base + 0x0184); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 336 | |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame^] | 337 | mdss_dsi_phy_regulator_init(pd, phy_base); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 338 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 339 | off = 0x0140; /* phy timing ctrl 0 - 11 */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 340 | for (i = 0; i < 12; i++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 341 | writel(pd->timing[i], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 342 | dmb(); |
| 343 | off += 4; |
| 344 | } |
| 345 | |
| 346 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 347 | writel(0x00, phy_base + 0x0174); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 348 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 349 | writel(0x5f, phy_base + 0x0170); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 350 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 351 | dmb(); |
| 352 | /* 4 lanes + clk lane configuration */ |
| 353 | /* lane config n * (0 - 4) & DataPath setup */ |
| 354 | for (ln = 0; ln < 5; ln++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 355 | off = (ln * 0x40); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 356 | for (i = 0; i < 9; i++) { |
| 357 | offset = i + (ln * 9); |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 358 | writel(pd->laneCfg[offset], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 359 | dmb(); |
| 360 | off += 4; |
| 361 | } |
| 362 | } |
| 363 | |
| 364 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 365 | writel(0x5f, phy_base + 0x0170); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 366 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 367 | /* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */ |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 368 | if (phy_base == DSI0_PHY_BASE || |
| 369 | (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103_1)) |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 370 | writel(0x01, phy_base + 0x01d4); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 371 | else |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 372 | writel(0x00, phy_base + 0x01d4); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 373 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 374 | dmb(); |
| 375 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 376 | off = 0x01b4; /* phy BIST ctrl 0 - 5 */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 377 | for (i = 0; i < 6; i++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 378 | writel(pd->bistCtrl[i], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 379 | off += 4; |
| 380 | } |
| 381 | dmb(); |
| 382 | |
| 383 | /* DSI_0_CLKOUT_TIMING_CTRL */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 384 | writel(0x41b, ctl_base + 0x0c4); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 385 | dmb(); |
| 386 | |
| 387 | } |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 388 | |
| 389 | void mdss_dsi_phy_contention_detection( |
| 390 | struct mipi_dsi_panel_config *pinfo, |
| 391 | uint32_t phy_base) |
| 392 | { |
| 393 | struct mdss_dsi_phy_ctrl *pd; |
| 394 | |
| 395 | if (mdp_get_revision() == MDP_REV_304) |
| 396 | return; |
| 397 | |
| 398 | pd = (pinfo->mdss_dsi_phy_config); |
| 399 | writel(pd->strength[1], phy_base + 0x0188); |
| 400 | dmb(); |
| 401 | } |
| 402 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 403 | static int mdss_dsi_phy_20nm_init(struct mipi_dsi_panel_config *pinfo, |
| 404 | uint32_t ctl_base, uint32_t phy_base) |
| 405 | { |
| 406 | struct mdss_dsi_phy_ctrl *pd = pinfo->mdss_dsi_phy_config; |
| 407 | uint32_t i, off = 0, ln, offset; |
| 408 | |
| 409 | /* Strength ctrl 0 */ |
| 410 | writel(pd->strength[0], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_0); |
| 411 | |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame^] | 412 | mdss_dsi_phy_regulator_init(pd, phy_base); |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 413 | |
| 414 | off = MMSS_DSI_PHY_TIMING_CTRL_0; |
| 415 | for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) { |
| 416 | writel(pd->timing[i], phy_base + off); |
| 417 | dmb(); |
| 418 | } |
| 419 | |
| 420 | /* Currently the Phy settings for the DSI 0 is done in clk prepare*/ |
| 421 | if (phy_base == DSI1_PHY_BASE) { |
| 422 | writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1); |
| 423 | writel(0x05, phy_base + MMSS_DSI_PHY_CTRL_0); |
| 424 | dmb(); |
| 425 | |
| 426 | writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0); |
| 427 | dmb(); |
| 428 | |
| 429 | /* BITCLK_HS_SEL should be set to 0 for left */ |
| 430 | writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL); |
| 431 | |
| 432 | writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_2); |
| 433 | writel(0x02, phy_base + MMSS_DSI_PHY_CTRL_2); |
| 434 | writel(0x03, phy_base + MMSS_DSI_PHY_CTRL_2); |
| 435 | dmb(); |
| 436 | } |
| 437 | |
| 438 | writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1); |
| 439 | dmb(); |
| 440 | |
| 441 | for (ln = 0; ln < TOTAL_LANE_COUNT; ln++) { |
| 442 | off = (ln * 0x40); |
| 443 | for (i = 0; i < CONFIG_REG_FOR_EACH_LANE; i++, off += 4) { |
| 444 | offset = i + (ln * CONFIG_REG_FOR_EACH_LANE); |
| 445 | writel(pd->laneCfg[offset], phy_base + off); |
| 446 | dmb(); |
| 447 | } |
| 448 | } |
| 449 | |
| 450 | dmb(); |
| 451 | |
| 452 | off = MMSS_DSI_PHY_BIST_CTRL_0; |
| 453 | for (i = 0; i < TOTAL_BIST_CTRL_CONFIG; i++, off +=4) { |
| 454 | writel(pd->bistCtrl[i], phy_base + off); |
| 455 | } |
| 456 | dmb(); |
| 457 | |
| 458 | writel(0x41b, ctl_base + MMSS_DSI_CLKOUT_TIMING_CTRL); |
| 459 | dmb(); |
| 460 | } |
| 461 | |
| 462 | int mdss_dsi_phy_init (struct mipi_dsi_panel_config *pinfo, |
| 463 | uint32_t ctl_base, uint32_t phy_base) |
| 464 | { |
| 465 | int ret; |
| 466 | |
| 467 | if (pinfo->mdss_dsi_phy_config->is_pll_20nm) |
| 468 | ret = mdss_dsi_phy_20nm_init(pinfo, ctl_base, phy_base); |
| 469 | else |
| 470 | ret = mdss_dsi_phy_28nm_init(pinfo, ctl_base, phy_base); |
| 471 | |
| 472 | return ret; |
| 473 | } |