blob: 82aaf6df69ba8dbf05f1b8d4507923ac528a9b80 [file] [log] [blame]
mohamed sunfeer350e4282017-09-05 10:26:23 +05301/* Copyright (c) 2013-2015, 2017, The Linux Foundation. All rights reserved.
Deepa Dinamani0e5038f2013-05-16 15:02:16 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <debug.h>
30#include <platform/iomap.h>
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -070031#include <platform/irqs.h>
Deepa Dinamani0e5038f2013-05-16 15:02:16 -070032#include <platform/gpio.h>
33#include <reg.h>
34#include <target.h>
35#include <platform.h>
36#include <dload_util.h>
37#include <uart_dm.h>
38#include <mmc.h>
39#include <spmi.h>
40#include <board.h>
41#include <smem.h>
42#include <baseband.h>
43#include <dev/keys.h>
44#include <pm8x41.h>
45#include <crypto5_wrapper.h>
46#include <hsusb.h>
47#include <clock.h>
48#include <partition_parser.h>
49#include <scm.h>
50#include <platform/clock.h>
51#include <platform/gpio.h>
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -070052#include <platform/timer.h>
Deepa Dinamani0e5038f2013-05-16 15:02:16 -070053#include <stdlib.h>
Channagoud Kadabi415a7022013-09-11 10:48:40 -070054#include <ufs.h>
Sundarajan Srinivasan1215c6f2014-03-21 17:34:29 -070055#include <boot_device.h>
Deepa Dinamani0e5038f2013-05-16 15:02:16 -070056
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -070057#define PMIC_ARB_CHANNEL_NUM 0
58#define PMIC_ARB_OWNER_ID 0
59
Shashank Mittalc3621fe2014-08-28 15:38:19 -070060#define RECOVERY_MODE 0x77665502
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -070061#define FASTBOOT_MODE 0x77665500
62
Sundarajan Srinivasan4161b7e2013-09-10 13:55:31 -070063#define BOOT_DEVICE_MASK(val) ((val & 0x3E) >>1)
64
Sundarajan Srinivasan4431e162013-12-10 13:16:04 -080065#define SSD_CE_INSTANCE 1
66
Sundarajan Srinivasan86106c32013-12-19 11:36:07 -080067#define CE2_INSTANCE 2
68#define CE_EE 1
69#define CE_FIFO_SIZE 64
70#define CE_READ_PIPE 3
71#define CE_WRITE_PIPE 2
72#define CE_READ_PIPE_LOCK_GRP 0
73#define CE_WRITE_PIPE_LOCK_GRP 0
74#define CE_ARRAY_SIZE 20
75
Ameya Thakurcfca9212013-09-13 23:51:49 -070076enum cdp_subtype
77{
78 CDP_SUBTYPE_SMB349 = 0,
79 CDP_SUBTYPE_9x25_SMB349,
80 CDP_SUBTYPE_9x25_SMB1357,
81 CDP_SUBTYPE_9x35,
Sundarajan Srinivasan01e68f12013-11-01 12:21:52 -070082 CDP_SUBTYPE_SMB1357,
Sundarajan Srinivasan0e94a1c2013-12-17 10:55:51 -080083 CDP_SUBTYPE_SMB350,
84 CDP_SUBTYPE_9x35_M
Ameya Thakurcfca9212013-09-13 23:51:49 -070085};
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -070086
Ameya Thakurcfca9212013-09-13 23:51:49 -070087enum mtp_subtype
88{
89 MTP_SUBTYPE_SMB349 = 0,
90 MTP_SUBTYPE_9x25_SMB349,
91 MTP_SUBTYPE_9x25_SMB1357,
92 MTP_SUBTYPE_9x35,
Sundarajan Srinivasan0e94a1c2013-12-17 10:55:51 -080093 MTP_SUBTYPE_9x35_M
Ameya Thakurcfca9212013-09-13 23:51:49 -070094};
95
96enum rcm_subtype
97{
98 RCM_SUBTYPE_SMB349 = 0,
99 RCM_SUBTYPE_9x25_SMB349,
100 RCM_SUBTYPE_9x25_SMB1357,
101 RCM_SUBTYPE_9x35,
102 RCM_SUBTYPE_SMB1357,
Sundarajan Srinivasan0e94a1c2013-12-17 10:55:51 -0800103 RCM_SUBTYPE_SMB350,
104 RCM_SUBTYPE_9x35_M
Ameya Thakurcfca9212013-09-13 23:51:49 -0700105};
106
Sundarajan Srinivasan6ade93e2013-11-18 11:07:22 -0800107enum liquid_subtype
108{
109 LIQUID_SUBTYPE_STANDALONE = 0,
110 LIQUID_SUBTYPE_9x25,
111};
112
Ameya Thakurcfca9212013-09-13 23:51:49 -0700113static void set_sdc_power_ctrl(void);
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -0700114static uint32_t mmc_pwrctl_base[] =
115 { MSM_SDC1_BASE, MSM_SDC2_BASE };
116
117static uint32_t mmc_sdhci_base[] =
118 { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
119
120static uint32_t mmc_sdc_pwrctl_irq[] =
121 { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
122
123struct mmc_device *dev;
Channagoud Kadabi415a7022013-09-11 10:48:40 -0700124struct ufs_dev ufs_device;
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700125
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700126extern void ulpi_write(unsigned val, unsigned reg);
Pavel Nedeva6c0beb2013-11-15 17:20:27 +0200127extern int _emmc_recovery_init(void);
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700128
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700129void target_early_init(void)
130{
131#if WITH_DEBUG_UART
Sundarajan Srinivasand8b7c6f2013-09-13 16:50:22 -0700132 uart_dm_init(7, 0, BLSP2_UART1_BASE);
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700133#endif
134}
135
136/* Return 1 if vol_up pressed */
lijuang2d2b8a02015-06-05 21:34:15 +0800137int target_volume_up()
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700138{
lijuang2d2b8a02015-06-05 21:34:15 +0800139 static uint8_t first_time = 0;
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700140 uint8_t status = 0;
141 struct pm8x41_gpio gpio;
142
lijuang2d2b8a02015-06-05 21:34:15 +0800143 if (!first_time) {
144 /* Configure the GPIO */
145 gpio.direction = PM_GPIO_DIR_IN;
146 gpio.function = 0;
147 gpio.pull = PM_GPIO_PULL_UP_30;
148 gpio.vin_sel = 2;
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700149
lijuang2d2b8a02015-06-05 21:34:15 +0800150 pm8x41_gpio_config(2, &gpio);
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700151
lijuang2d2b8a02015-06-05 21:34:15 +0800152 /* Wait for the pmic gpio config to take effect */
153 udelay(10000);
154
155 first_time = 1;
156
157 }
Channagoud Kadabiefcb8ec2014-01-02 16:22:38 -0800158
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700159 /* Get status of P_GPIO_2 */
160 pm8x41_gpio_get(2, &status);
161
162 return !status; /* active low */
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700163}
164
165/* Return 1 if vol_down pressed */
166uint32_t target_volume_down()
167{
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700168 return pm8x41_resin_status();
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700169}
170
171static void target_keystatus()
172{
173 keys_init();
174
175 if(target_volume_down())
176 keys_post_event(KEY_VOLUMEDOWN, 1);
177
178 if(target_volume_up())
179 keys_post_event(KEY_VOLUMEUP, 1);
180}
181
David Ng4c2e86d2013-09-15 22:03:37 -0700182void target_uninit(void)
183{
Sundarajan Srinivasan1215c6f2014-03-21 17:34:29 -0700184 if(platform_boot_dev_isemmc())
Channagoud Kadabi154764f2014-01-24 17:45:19 -0800185 {
Sundarajan Srinivasan29cb66e2013-10-30 18:48:27 -0700186 mmc_put_card_to_sleep(dev);
Channagoud Kadabi154764f2014-01-24 17:45:19 -0800187 sdhci_mode_disable(&dev->host);
188 }
David Ng4c2e86d2013-09-15 22:03:37 -0700189}
190
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700191/* Do target specific usb initialization */
192void target_usb_init(void)
193{
194 uint32_t val;
195
196 /* Select and enable external configuration with USB PHY */
197 ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
198
199 /* Enable sess_vld */
200 val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
201 writel(val, USB_GENCONFIG_2);
202
203 /* Enable external vbus configuration in the LINK */
204 val = readl(USB_USBCMD);
205 val |= SESS_VLD_CTRL;
206 writel(val, USB_USBCMD);
207}
208
209void target_usb_stop(void)
210{
211 /* Disable VBUS mimicing in the controller. */
212 ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
213}
214
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700215static void set_sdc_power_ctrl()
216{
217 /* Drive strength configs for sdc pins */
218 struct tlmm_cfgs sdc1_hdrv_cfg[] =
219 {
220 { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
221 { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
222 { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
223 };
224
225 /* Pull configs for sdc pins */
226 struct tlmm_cfgs sdc1_pull_cfg[] =
227 {
228 { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
229 { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
230 { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
Channagoud Kadabic14b4042013-09-23 11:20:32 -0700231 { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK },
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700232 };
233
234 /* Set the drive strength & pull control values */
235 tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
236 tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
237}
238
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -0700239void target_sdc_init()
240{
241 struct mmc_config_data config;
242
243 /* Set drive strength & pull ctrl values */
244 set_sdc_power_ctrl();
245
246 config.bus_width = DATA_BUS_WIDTH_8BIT;
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -0700247
248 /* Try slot 1*/
249 config.slot = 1;
Channagoud Kadabide9b2d32013-11-08 13:24:47 -0800250 config.max_clk_rate = MMC_CLK_192MHZ;
251 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
252 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
253 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
Aparna Mallavarapu7b1393e2014-03-11 13:45:21 +0530254 config.hs400_support = 1;
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -0700255
256 if (!(dev = mmc_init(&config)))
257 {
258 /* Try slot 2 */
259 config.slot = 2;
Channagoud Kadabide9b2d32013-11-08 13:24:47 -0800260 config.max_clk_rate = MMC_CLK_200MHZ;
261 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
262 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
263 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -0700264
265 if (!(dev = mmc_init(&config)))
266 {
267 dprintf(CRITICAL, "mmc init failed!");
268 ASSERT(0);
269 }
270 }
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -0700271}
272
Channagoud Kadabi415a7022013-09-11 10:48:40 -0700273void *target_mmc_device()
274{
Sundarajan Srinivasan1215c6f2014-03-21 17:34:29 -0700275 if (platform_boot_dev_isemmc())
Channagoud Kadabi415a7022013-09-11 10:48:40 -0700276 return (void *) dev;
277 else
278 return (void *) &ufs_device;
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -0700279}
280
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700281void target_init(void)
282{
283 dprintf(INFO, "target_init()\n");
284
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700285 spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
286
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700287 target_keystatus();
288
Sundarajan Srinivasan86106c32013-12-19 11:36:07 -0800289 if (target_use_signed_kernel())
290 target_crypto_init_params();
291
Sundarajan Srinivasan1215c6f2014-03-21 17:34:29 -0700292 platform_read_boot_config();
Sundarajan Srinivasan4161b7e2013-09-10 13:55:31 -0700293
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800294#ifdef MMC_SDHCI_SUPPORT
Sundarajan Srinivasan1215c6f2014-03-21 17:34:29 -0700295 if (platform_boot_dev_isemmc())
Channagoud Kadabi415a7022013-09-11 10:48:40 -0700296 target_sdc_init();
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800297#endif
298#ifdef UFS_SUPPORT
299 if(!platform_boot_dev_isemmc())
Channagoud Kadabi415a7022013-09-11 10:48:40 -0700300 {
301 ufs_device.base = UFS_BASE;
302 ufs_init(&ufs_device);
303 }
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800304#endif
Channagoud Kadabi415a7022013-09-11 10:48:40 -0700305
306 /* Storage initialization is complete, read the partition table info */
307 if (partition_read_table())
308 {
309 dprintf(CRITICAL, "Error reading the partition table info\n");
310 ASSERT(0);
311 }
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700312}
313
Sundarajan Srinivasan4431e162013-12-10 13:16:04 -0800314void target_load_ssd_keystore(void)
315{
316 uint64_t ptn;
317 int index;
318 uint64_t size;
319 uint32_t *buffer = NULL;
320
321 if (!target_is_ssd_enabled())
322 return;
323
324 index = partition_get_index("ssd");
325
326 ptn = partition_get_offset(index);
327 if (ptn == 0){
328 dprintf(CRITICAL, "Error: ssd partition not found\n");
329 return;
330 }
331
332 size = partition_get_size(index);
mohamed sunfeer350e4282017-09-05 10:26:23 +0530333 if ((size == 0) || ((ULLONG_MAX - CACHE_LINE + 1) < size)) {
334 dprintf(CRITICAL, "Error: invalid ssd partition size %d\n",size);
Sundarajan Srinivasan4431e162013-12-10 13:16:04 -0800335 return;
336 }
337
338 buffer = memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE));
339 if (!buffer) {
340 dprintf(CRITICAL, "Error: allocating memory for ssd buffer\n");
341 return;
342 }
343
344 if (mmc_read(ptn, buffer, size)) {
345 dprintf(CRITICAL, "Error: cannot read data\n");
346 free(buffer);
347 return;
348 }
349
350 clock_ce_enable(SSD_CE_INSTANCE);
351 scm_protect_keystore(buffer, size);
352 clock_ce_disable(SSD_CE_INSTANCE);
353 free(buffer);
354}
355
356/* Do any target specific intialization needed before entering fastboot mode */
357void target_fastboot_init(void)
358{
Sundarajan Srinivasan23301ef2013-11-18 17:21:00 -0800359 /* We are entering fastboot mode, so read partition table */
360 mmc_read_partition_table(1);
361
Sundarajan Srinivasan4431e162013-12-10 13:16:04 -0800362 if (target_is_ssd_enabled()) {
363 clock_ce_enable(SSD_CE_INSTANCE);
364 target_load_ssd_keystore();
365 }
366
367}
368
Channagoud Kadabi7fe8df62014-02-04 17:08:10 -0800369/* Initialize target specific USB handlers */
370target_usb_iface_t* target_usb30_init()
371{
372 target_usb_iface_t *t_usb_iface;
373
374 t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
375 ASSERT(t_usb_iface);
376
377 t_usb_iface->mux_config = target_usb_phy_mux_configure;
378 t_usb_iface->phy_reset = target_usb_phy_reset;
379 t_usb_iface->clock_init = clock_usb30_init;
380 t_usb_iface->vbus_override = 1;
381
382 return t_usb_iface;
383}
384
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700385unsigned board_machtype(void)
386{
387 return LINUX_MACHTYPE_UNKNOWN;
388}
389
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700390/* Detect the target type */
391void target_detect(struct board_data *board)
392{
Channagoud Kadabieabb9ad2014-02-11 15:34:24 -0800393 /* This is alreay filled as part of board.c */
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700394}
395
Ameya Thakurcfca9212013-09-13 23:51:49 -0700396void set_cdp_baseband(struct board_data *board)
397{
398
399 uint32_t platform_subtype;
400 platform_subtype = board->platform_subtype;
401
402 switch(platform_subtype) {
403 case CDP_SUBTYPE_9x25_SMB349:
404 case CDP_SUBTYPE_9x25_SMB1357:
Ameya Thakurcfca9212013-09-13 23:51:49 -0700405 board->baseband = BASEBAND_MDM;
406 break;
Sundarajan Srinivasan839b5202013-11-12 17:21:07 -0800407 case CDP_SUBTYPE_9x35:
Sundarajan Srinivasan0e94a1c2013-12-17 10:55:51 -0800408 case CDP_SUBTYPE_9x35_M:
Sundarajan Srinivasan839b5202013-11-12 17:21:07 -0800409 board->baseband = BASEBAND_MDM2;
410 break;
Ameya Thakurcfca9212013-09-13 23:51:49 -0700411 case CDP_SUBTYPE_SMB349:
412 case CDP_SUBTYPE_SMB1357:
Sundarajan Srinivasan01e68f12013-11-01 12:21:52 -0700413 case CDP_SUBTYPE_SMB350:
Ameya Thakurcfca9212013-09-13 23:51:49 -0700414 board->baseband = BASEBAND_APQ;
415 break;
416 default:
417 dprintf(CRITICAL, "CDP platform subtype :%u is not supported\n",
418 platform_subtype);
419 ASSERT(0);
420 };
421
422}
423
424void set_mtp_baseband(struct board_data *board)
425{
426
427 uint32_t platform_subtype;
428 platform_subtype = board->platform_subtype;
429
430 switch(platform_subtype) {
431 case MTP_SUBTYPE_9x25_SMB349:
432 case MTP_SUBTYPE_9x25_SMB1357:
Ameya Thakurcfca9212013-09-13 23:51:49 -0700433 board->baseband = BASEBAND_MDM;
434 break;
Sundarajan Srinivasan839b5202013-11-12 17:21:07 -0800435 case MTP_SUBTYPE_9x35:
Sundarajan Srinivasan0e94a1c2013-12-17 10:55:51 -0800436 case MTP_SUBTYPE_9x35_M:
Sundarajan Srinivasan839b5202013-11-12 17:21:07 -0800437 board->baseband = BASEBAND_MDM2;
438 break;
Ameya Thakurcfca9212013-09-13 23:51:49 -0700439 case MTP_SUBTYPE_SMB349:
440 board->baseband = BASEBAND_APQ;
441 break;
442 default:
443 dprintf(CRITICAL, "MTP platform subtype :%u is not supported\n",
444 platform_subtype);
445 ASSERT(0);
446 };
447}
448
449void set_rcm_baseband(struct board_data *board)
450{
451 uint32_t platform_subtype;
452 platform_subtype = board->platform_subtype;
453
454 switch(platform_subtype) {
455 case RCM_SUBTYPE_9x25_SMB349:
456 case RCM_SUBTYPE_9x25_SMB1357:
Ameya Thakurcfca9212013-09-13 23:51:49 -0700457 board->baseband = BASEBAND_MDM;
458 break;
Sundarajan Srinivasan839b5202013-11-12 17:21:07 -0800459 case RCM_SUBTYPE_9x35:
Sundarajan Srinivasan0e94a1c2013-12-17 10:55:51 -0800460 case RCM_SUBTYPE_9x35_M:
Sundarajan Srinivasan839b5202013-11-12 17:21:07 -0800461 board->baseband = BASEBAND_MDM2;
462 break;
Ameya Thakurcfca9212013-09-13 23:51:49 -0700463 case RCM_SUBTYPE_SMB349:
464 case RCM_SUBTYPE_SMB1357:
Sundarajan Srinivasan01e68f12013-11-01 12:21:52 -0700465 case RCM_SUBTYPE_SMB350:
Ameya Thakurcfca9212013-09-13 23:51:49 -0700466 board->baseband = BASEBAND_APQ;
467 break;
468 default:
469 dprintf(CRITICAL, "RCM platform subtype :%u is not supported\n",
470 platform_subtype);
471 ASSERT(0);
472 };
473}
474
Sundarajan Srinivasan6ade93e2013-11-18 11:07:22 -0800475void set_liquid_baseband(struct board_data *board)
476{
477 uint32_t platform_subtype;
478
479 platform_subtype = board->platform_subtype;
480
481 switch(platform_subtype)
482 {
483 case LIQUID_SUBTYPE_STANDALONE:
484 board->baseband = BASEBAND_APQ;
485 break;
486 case LIQUID_SUBTYPE_9x25:
487 board->baseband = BASEBAND_MDM;
488 break;
489 default:
490 dprintf(CRITICAL, "Liquid platform subtype :%u is not supported\n",platform_subtype);
491 ASSERT(0);
492 }
493}
494
Justin Philipbe9de5c2014-09-17 12:26:49 +0530495static uint8_t splash_override;
Dhaval Patelf9986272013-10-18 19:06:05 -0700496/* Returns 1 if target supports continuous splash screen. */
497int target_cont_splash_screen()
498{
Justin Philipbe9de5c2014-09-17 12:26:49 +0530499 uint8_t splash_screen = 0;
500 if(!splash_override) {
501 switch(board_hardware_id())
502 {
503 case HW_PLATFORM_SURF:
504 case HW_PLATFORM_MTP:
505 case HW_PLATFORM_FLUID:
506 case HW_PLATFORM_LIQUID:
507 dprintf(SPEW, "Target_cont_splash=1\n");
508 splash_screen = 1;
509 break;
510 default:
511 dprintf(SPEW, "Target_cont_splash=0\n");
512 splash_screen = 0;
513 }
Dhaval Patelf9986272013-10-18 19:06:05 -0700514 }
Justin Philipbe9de5c2014-09-17 12:26:49 +0530515 return splash_screen;
516}
517
518void target_force_cont_splash_disable(uint8_t override)
519{
520 splash_override = override;
Dhaval Patelf9986272013-10-18 19:06:05 -0700521}
Ameya Thakurcfca9212013-09-13 23:51:49 -0700522
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700523/* Detect the modem type */
524void target_baseband_detect(struct board_data *board)
525{
Sundarajan Srinivasanf5932fb2013-08-06 17:26:04 -0700526 uint32_t platform;
527 uint32_t platform_subtype;
Ameya Thakurcfca9212013-09-13 23:51:49 -0700528 uint32_t platform_hardware;
Sundarajan Srinivasanf5932fb2013-08-06 17:26:04 -0700529
530 platform = board->platform;
Sundarajan Srinivasanf5932fb2013-08-06 17:26:04 -0700531
Ameya Thakurcfca9212013-09-13 23:51:49 -0700532 platform_hardware = board->platform_hw;
533
534 switch(platform_hardware) {
535 case HW_PLATFORM_SURF:
536 set_cdp_baseband(board);
Sundarajan Srinivasanf5932fb2013-08-06 17:26:04 -0700537 break;
Ameya Thakurcfca9212013-09-13 23:51:49 -0700538 case HW_PLATFORM_MTP:
539 set_mtp_baseband(board);
540 break;
541 case HW_PLATFORM_RCM:
542 set_rcm_baseband(board);
543 break;
544 case HW_PLATFORM_LIQUID:
Sundarajan Srinivasan6ade93e2013-11-18 11:07:22 -0800545 set_liquid_baseband(board);
Sundarajan Srinivasanf5932fb2013-08-06 17:26:04 -0700546 break;
Eugene Yasman2a462112013-12-09 09:26:37 +0200547 case HW_PLATFORM_SBC:
548 board->baseband = BASEBAND_APQ;
549 break;
Sundarajan Srinivasanf5932fb2013-08-06 17:26:04 -0700550 default:
Ameya Thakurcfca9212013-09-13 23:51:49 -0700551 dprintf(CRITICAL, "Platform :%u is not supported\n",
552 platform_hardware);
Sundarajan Srinivasanf5932fb2013-08-06 17:26:04 -0700553 ASSERT(0);
Ameya Thakurcfca9212013-09-13 23:51:49 -0700554 };
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700555}
556
557unsigned target_baseband()
558{
559 return board_baseband();
560}
561
562void target_serialno(unsigned char *buf)
563{
564 unsigned int serialno;
565 if (target_is_emmc_boot()) {
566 serialno = mmc_get_psn();
567 snprintf((char *)buf, 13, "%x", serialno);
568 }
569}
570
Pavel Nedeva6c0beb2013-11-15 17:20:27 +0200571int emmc_recovery_init(void)
572{
573 return _emmc_recovery_init();
574}
575
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700576unsigned check_reboot_mode(void)
577{
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700578 uint32_t restart_reason = 0;
579 uint32_t restart_reason_addr;
580
581 restart_reason_addr = RESTART_REASON_ADDR;
582
583 /* Read reboot reason and scrub it */
584 restart_reason = readl(restart_reason_addr);
585 writel(0x00, restart_reason_addr);
586
587 return restart_reason;
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700588}
589
590void reboot_device(unsigned reboot_reason)
591{
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700592 uint8_t reset_type = 0;
593
594 /* Write the reboot reason */
595 writel(reboot_reason, RESTART_REASON_ADDR);
596
Shashank Mittalc3621fe2014-08-28 15:38:19 -0700597 if(reboot_reason == FASTBOOT_MODE || reboot_reason == RECOVERY_MODE)
Sundarajan Srinivasand43b28b2013-06-25 16:59:13 -0700598 reset_type = PON_PSHOLD_WARM_RESET;
599 else
600 reset_type = PON_PSHOLD_HARD_RESET;
601
602 pm8x41_reset_configure(reset_type);
603
604 /* Drop PS_HOLD for MSM */
605 writel(0x00, MPM2_MPM_PS_HOLD);
606
607 mdelay(5000);
608
609 dprintf(CRITICAL, "Rebooting failed\n");
Deepa Dinamani0e5038f2013-05-16 15:02:16 -0700610}
Amol Jadi0a4c9b42013-10-11 14:22:11 -0700611
Sundarajan Srinivasan8a3ecf52014-05-06 11:32:41 -0700612void shutdown_device()
613{
614 dprintf(CRITICAL, "Going down for shutdown.\n");
615
616 /* Configure PMIC for shutdown. */
617 pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
618
619 /* Drop PS_HOLD for MSM */
620 writel(0x00, MPM2_MPM_PS_HOLD);
621
622 mdelay(5000);
623
624 dprintf(CRITICAL, "Shutdown failed\n");
625
626 ASSERT(0);
627}
628
Amol Jadi0a4c9b42013-10-11 14:22:11 -0700629/* identify the usb controller to be used for the target */
630const char * target_usb_controller()
631{
632 return "dwc";
633}
634
635/* mux hs phy to route to dwc controller */
636static void phy_mux_configure_with_jdr()
637{
638 uint32_t val;
639
640 val = readl(COPSS_USB_CONTROL_WITH_JDR);
641
642 /* Note: there are no details regarding this bit in hpg or swi. */
643 val |= BIT(8);
644
645 writel(val, COPSS_USB_CONTROL_WITH_JDR);
646}
647
648/* configure hs phy mux if using dwc controller */
649void target_usb_phy_mux_configure(void)
650{
651 if(!strcmp(target_usb_controller(), "dwc"))
652 {
653 phy_mux_configure_with_jdr();
654 }
655}
656
657void target_usb_phy_reset(void)
658{
659 uint32_t val;
660
661 /* SS PHY reset */
662 val = readl(GCC_USB3_PHY_BCR) | BIT(0);
663 writel(val, GCC_USB3_PHY_BCR);
664 udelay(10);
665 writel(val & ~BIT(0), GCC_USB3_PHY_BCR);
666
667 /* HS PHY reset */
668 /* Note: reg/bit details are not mentioned in hpg or swi. */
669 val = readl(COPSS_USB_CONTROL_WITH_JDR) | BIT(11);
670 writel(val, COPSS_USB_CONTROL_WITH_JDR);
671 udelay(10);
672 writel(val & ~BIT(11), COPSS_USB_CONTROL_WITH_JDR);
Channagoud Kadabi70500ea2013-10-29 17:33:44 -0700673
674 /* PHY_COMMON reset */
675 val = readl(GCC_USB30_PHY_COM_BCR) | BIT(0);
676 writel(val, GCC_USB30_PHY_COM_BCR);
677 udelay(10);
678 writel(val & ~BIT(0), GCC_USB30_PHY_COM_BCR);
Amol Jadi0a4c9b42013-10-11 14:22:11 -0700679}
Sundarajan Srinivasan86106c32013-12-19 11:36:07 -0800680
Hanumant Singh75311942014-01-29 13:43:53 -0800681bool target_warm_boot(void)
682{
683 uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
684 if (is_cold_boot)
685 return false;
686 else
687 return true;
688}
Sundarajan Srinivasan86106c32013-12-19 11:36:07 -0800689/* Set up params for h/w CE. */
690void target_crypto_init_params()
691{
692 struct crypto_init_params ce_params;
693
694 /* Set up base addresses and instance. */
695 ce_params.crypto_instance = CE2_INSTANCE;
696 ce_params.crypto_base = MSM_CE2_BASE;
697 ce_params.bam_base = MSM_CE2_BAM_BASE;
698
699 /* Set up BAM config. */
700 ce_params.bam_ee = CE_EE;
701 ce_params.pipes.read_pipe = CE_READ_PIPE;
702 ce_params.pipes.write_pipe = CE_WRITE_PIPE;
703 ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
704 ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
705
706 /* Assign buffer sizes. */
707 ce_params.num_ce = CE_ARRAY_SIZE;
708 ce_params.read_fifo_size = CE_FIFO_SIZE;
709 ce_params.write_fifo_size = CE_FIFO_SIZE;
710
711 /* BAM is initialized by TZ for this platform.
712 * Do not do it again as the initialization address space
713 * is locked.
714 */
715 ce_params.do_bam_init = 0;
716
717 crypto_init_params(&ce_params);
718}
719
720crypto_engine_type board_ce_type(void)
721{
722 return CRYPTO_ENGINE_TYPE_HW;
723}