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gerrit-public.fairphone.software / kernel / lk / 3de1c512347e9cdd6f3da1e7d4ef424b7e303d03 / . / platform / msm8996 / include / platform / iomap.h
blob: 2ae1d17be04cfd2725272fb675c836509050ade0 [file] [log] [blame]
Sridhar Parasurambe12c3d2015-01-16 13:42:26 -0800[diff] [blame]1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_THULIUM_IOMAP_H_
30#define _PLATFORM_THULIUM_IOMAP_H_
31
32#define MSM_SHARED_BASE 0x86000000
33
34#define MSM_IOMAP_HMSS_START 0x09800000
35
36#define MSM_IOMAP_BASE 0x00000000
37#define MSM_IOMAP_END 0x10000000
38
39#define MSM_SHARED_IMEM_BASE 0x066BF000
40#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]41#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + 0x6B0)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]42
43#define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000)
44#define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000)
45
46#define HMSS_APCS_F0_QTMR_V1_BASE (MSM_IOMAP_HMSS_START + 0x00050000)
47#define QTMR_BASE HMSS_APCS_F0_QTMR_V1_BASE
48
Sridhar Parasurambe12c3d2015-01-16 13:42:26 -0800[diff] [blame]49#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS 0x00068000
50#define RPM_SS_MSG_RAM_START_ADDRESS_BASE RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS
51#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE 0x00006000
52
Sridhar Parasuram103702f2015-01-26 18:07:55 -0800[diff] [blame]53#define APCS_HLOS_IPC_INTERRUPT_0 0x9820010
54
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]55#define PERIPH_SS_BASE 0x07400000
56
57#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00064000)
58#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
59#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
60#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
61
62#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0016F000)
63#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x00170000)
64#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x00171000)
65#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00172000)
66#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00173000)
67#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00174000)
68
69#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x001B0000)
70
71/* USB3.0 */
72#define MSM_USB30_BASE 0x6A00000
73#define MSM_USB30_QSCRATCH_BASE 0x6AF8800
74/* SS QMP (Qulacomm Multi Protocol) */
75#define QMP_PHY_BASE 0x7410000
76
77/* QUSB2 PHY */
78#define QUSB2_PHY_BASE 0x7411000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]79#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00012038)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]80
81/* Clocks */
82#define CLK_CTL_BASE 0x300000
83
84/* GPLL */
85#define GPLL0_MODE (CLK_CTL_BASE + 0x0000)
86#define GPLL4_MODE (CLK_CTL_BASE + 0x77000)
87#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x52000)
88#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
89
90/* UART Clocks */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]91#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x25004)
92#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29004)
Channagoud Kadabi35503c42014-11-14 16:22:43 -0800[diff] [blame]93#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2900C)
94#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x29010)
95#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0x29014)
96#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0x29018)
97#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0x2901C)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]98
99/* USB3 clocks */
100#define USB_30_BCR (CLK_CTL_BASE + 0xF000)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]101#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]102#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0xF008)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]103#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
104#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]105#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0xF014)
106#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0xF018)
107#define USB30_MASTER_M (CLK_CTL_BASE + 0xF01C)
108#define USB30_MASTER_N (CLK_CTL_BASE + 0xF020)
109#define USB30_MASTER_D (CLK_CTL_BASE + 0xF024)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]110#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF028)
111#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF02C)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]112#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0xF03C)
113
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]114#define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5000C)
115#define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x50010)
116#define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x50000)
117#define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x50004)
118#define USB30_PHY_BCR (CLK_CTL_BASE + 0x50020)
119#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x50024)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]120#define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x6A004)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]121#define GCC_AGGRE2_USB3_AXI_CBCR (CLK_CTL_BASE + 0x83018)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]122
123/* SDCC */
124#define SDCC1_BCR (CLK_CTL_BASE + 0x13000) /* block reset */
125#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x13004) /* branch control */
126#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x13008)
127#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x13010) /* cmd */
128#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x13014) /* cfg */
129#define SDCC1_M (CLK_CTL_BASE + 0x13018) /* m */
130#define SDCC1_N (CLK_CTL_BASE + 0x1301C) /* n */
131#define SDCC1_D (CLK_CTL_BASE + 0x13020) /* d */
132
133/* SDCC2 */
134#define SDCC2_BCR (CLK_CTL_BASE + 0x14000) /* block reset */
135#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x14004) /* branch control */
136#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x14008)
137#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x14010) /* cmd */
138#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x14014) /* cfg */
139#define SDCC2_M (CLK_CTL_BASE + 0x14018) /* m */
140#define SDCC2_N (CLK_CTL_BASE + 0x1401C) /* n */
141#define SDCC2_D (CLK_CTL_BASE + 0x14020) /* d */
142
143#define UFS_BASE 0x624000
144
145#define SPMI_BASE 0x4000000
146#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
147#define SPMI_PIC_BASE (SPMI_BASE + 0x1800000)
Channagoud Kadabi7b20dea2014-11-11 13:27:33 -0800[diff] [blame]148#define PMIC_ARB_CORE 0x400F000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]149
Channagoud Kadabi037c8b82015-02-05 12:09:32 -0800[diff] [blame]150#define MSM_CE_BAM_BASE 0x644000
151#define MSM_CE_BASE 0x67A000
152#define GCC_CE1_BCR (CLK_CTL_BASE + 0x00041000)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]153
154#define TLMM_BASE_ADDR 0x1010000
155#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
156#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x4 + (x)*0x1000)
157
158#define MPM2_MPM_CTRL_BASE 0x4A1000
159#define MPM2_MPM_PS_HOLD 0x4AB000
160#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000
161
Dinesh K Garg6bbbb702015-01-30 11:13:31 -0800[diff] [blame]162/* QSEECOM: Secure app region notification */
163#define APP_REGION_ADDR 0x86600000
Zhen Kong327fac52015-06-12 17:04:24 -0700[diff] [blame]164#define APP_REGION_SIZE 0x2200000
Dinesh K Garg6bbbb702015-01-30 11:13:31 -0800[diff] [blame]165
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]166/* DRV strength for sdcc */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]167#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0012C000)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]168
169/* SDHCI - power control registers */
170#define SDCC_MCI_HC_MODE (0x00000078)
171#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
172#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
173#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
174#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
175
176/* Boot config */
177#define SEC_CTRL_CORE_BASE 0x70000
178#define BOOT_CONFIG_OFFSET 0x00006044
179#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
180
Channagoud Kadabi652a6f62014-11-17 17:23:23 -0800[diff] [blame]181/* QMP rev registers */
182#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x788)
183#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x78C)
184#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x790)
185#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x794)
186
187/* Dummy macro needed for compilation only */
188#define PLATFORM_QMP_OFFSET 0x0
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]189
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800[diff] [blame]190/* RPMB send receive buffer needs to be mapped
191 * as device memory, define the start address
192 * and size in MB
193 */
Channagoud Kadabia71f0722015-08-11 16:21:40 -0700[diff] [blame]194#define RPMB_SND_RCV_BUF 0x91400000
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700[diff] [blame]195#define RPMB_SND_RCV_BUF_SZ 0x2
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800[diff] [blame]196
Channagoud Kadabi23edc0c2015-03-27 18:31:32 -0700[diff] [blame]197#define TCSR_BOOT_MISC_DETECT 0x007B3000
Dhaval Patel0f3cbeb2015-03-17 11:52:12 -0700[diff] [blame]198
199#define MSM_MMSS_CLK_CTL_BASE 0x8C0000
200#define MMSS_MISC_AHB_CBCR (MSM_MMSS_CLK_CTL_BASE + 0x5018)
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]201
202#define MIPI_DSI_BASE (0x994000)
203#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
204#define MIPI_DSI1_BASE (0x996000)
205#define DSI0_PHY_BASE (0x994400)
206#define DSI1_PHY_BASE (0x996400)
207#define DSI0_PLL_BASE (0x994800)
208#define DSI1_PLL_BASE (0x996800)
209#define DSI0_REGULATOR_BASE (0x994000)
210#define DSI1_REGULATOR_BASE (0x996000)
211
212#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0160
213#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0168
214
215#define MDP_BASE (0x900000)
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]216#define REG_MDP(off) (MDP_BASE + (off))
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]217
218#ifdef MDP_PP_0_BASE
219#undef MDP_PP_0_BASE
220#endif
221#define MDP_PP_0_BASE REG_MDP(0x71000)
222
223#ifdef MDP_PP_1_BASE
224#undef MDP_PP_1_BASE
225#endif
226#define MDP_PP_1_BASE REG_MDP(0x71800)
227
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]228#define MDP_DSC_0_BASE REG_MDP(0x81000)
229#define MDP_DSC_1_BASE REG_MDP(0x81400)
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]230
231#ifdef MDP_HW_REV
232#undef MDP_HW_REV
233#endif
234#define MDP_HW_REV REG_MDP(0x1000)
235
236#ifdef MDP_INTR_EN
237#undef MDP_INTR_EN
238#endif
239#define MDP_INTR_EN REG_MDP(0x1010)
240
241#ifdef MDP_INTR_CLEAR
242#undef MDP_INTR_CLEAR
243#endif
244#define MDP_INTR_CLEAR REG_MDP(0x1018)
245
246#ifdef MDP_HIST_INTR_EN
247#undef MDP_HIST_INTR_EN
248#endif
249#define MDP_HIST_INTR_EN REG_MDP(0x101C)
250
251#ifdef MDP_DISP_INTF_SEL
252#undef MDP_DISP_INTF_SEL
253#endif
254#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
255
256#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
257#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
258#endif
259#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
260
261#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
262#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
263#endif
264#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
265
266#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
267#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
268#endif
269#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
270
271#ifdef MDP_INTF_0_TIMING_ENGINE_EN
272#undef MDP_INTF_0_TIMING_ENGINE_EN
273#endif
274#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000)
275
276#ifdef MDP_INTF_1_TIMING_ENGINE_EN
277#undef MDP_INTF_1_TIMING_ENGINE_EN
278#endif
279#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
280
281#ifdef MDP_INTF_2_TIMING_ENGINE_EN
282#undef MDP_INTF_2_TIMING_ENGINE_EN
283#endif
284#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x6C000)
285
286#ifdef MDP_CTL_0_BASE
287#undef MDP_CTL_0_BASE
288#endif
289#define MDP_CTL_0_BASE REG_MDP(0x2000)
290
291#ifdef MDP_CTL_1_BASE
292#undef MDP_CTL_1_BASE
293#endif
294#define MDP_CTL_1_BASE REG_MDP(0x2200)
295
296#ifdef MDP_REG_SPLIT_DISPLAY_EN
297#undef MDP_REG_SPLIT_DISPLAY_EN
298#endif
299#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
300
301#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
302#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
303#endif
304#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
305
306#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
307#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
308#endif
309#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
310
311#ifdef MDP_INTF_0_BASE
312#undef MDP_INTF_0_BASE
313#endif
314#define MDP_INTF_0_BASE REG_MDP(0x6b000)
315
316#ifdef MDP_INTF_1_BASE
317#undef MDP_INTF_1_BASE
318#endif
319#define MDP_INTF_1_BASE REG_MDP(0x6b800)
320
321#ifdef MDP_INTF_2_BASE
322#undef MDP_INTF_2_BASE
323#endif
324#define MDP_INTF_2_BASE REG_MDP(0x6c000)
325
326#ifdef MDP_CLK_CTRL0
327#undef MDP_CLK_CTRL0
328#endif
329#define MDP_CLK_CTRL0 REG_MDP(0x12AC)
330
331#ifdef MDP_CLK_CTRL1
332#undef MDP_CLK_CTRL1
333#endif
334#define MDP_CLK_CTRL1 REG_MDP(0x12B4)
335
336#ifdef MDP_CLK_CTRL2
337#undef MDP_CLK_CTRL2
338#endif
339#define MDP_CLK_CTRL2 REG_MDP(0x12BC)
340
341#ifdef MDP_CLK_CTRL3
342#undef MDP_CLK_CTRL3
343#endif
344#define MDP_CLK_CTRL3 REG_MDP(0x13A8)
345
346#ifdef MDP_CLK_CTRL4
347#undef MDP_CLK_CTRL4
348#endif
349#define MDP_CLK_CTRL4 REG_MDP(0x13B0)
350
351#ifdef MDP_CLK_CTRL5
352#undef MDP_CLK_CTRL5
353#endif
354#define MDP_CLK_CTRL5 REG_MDP(0x13B8)
355
356#ifdef MDP_CLK_CTRL6
357#undef MDP_CLK_CTRL6
358#endif
359#define MDP_CLK_CTRL6 REG_MDP(0x12C4)
360
361#ifdef MDP_CLK_CTRL7
362#undef MDP_CLK_CTRL7
363#endif
364#define MDP_CLK_CTRL7 REG_MDP(0x13D0)
365
366#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
367#undef MMSS_MDP_SMP_ALLOC_W_BASE
368#endif
369#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
370
371#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
372#undef MMSS_MDP_SMP_ALLOC_R_BASE
373#endif
374#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
375
376#ifdef MDP_QOS_REMAPPER_CLASS_0
377#undef MDP_QOS_REMAPPER_CLASS_0
378#endif
379#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
380
381#ifdef MDP_QOS_REMAPPER_CLASS_1
382#undef MDP_QOS_REMAPPER_CLASS_1
383#endif
384#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x11E4)
385
386#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
387#undef VBIF_VBIF_DDR_FORCE_CLK_ON
388#endif
389#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xb0004)
390
391#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
392#undef VBIF_VBIF_DDR_OUT_MAX_BURST
393#endif
394#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xb00D8)
395
396#ifdef VBIF_VBIF_DDR_ARB_CTRL
397#undef VBIF_VBIF_DDR_ARB_CTRL
398#endif
399#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xb00F0)
400
401#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
402#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
403#endif
404#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xb0124)
405
406#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
407#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
408#endif
409#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xb0160)
410
411#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
412#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
413#endif
414#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xb0164)
415
416#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
417#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
418#endif
419#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xb0178)
420
421#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
422#undef VBIF_VBIF_DDR_OUT_AX_AOOO
423#endif
424#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xb017C)
425
426#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
427#undef VBIF_VBIF_IN_RD_LIM_CONF0
428#endif
429#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xb00B0)
430
431#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
432#undef VBIF_VBIF_IN_RD_LIM_CONF1
433#endif
434#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xb00B4)
435
436#ifdef VBIF_VBIF_IN_RD_LIM_CONF2
437#undef VBIF_VBIF_IN_RD_LIM_CONF2
438#endif
439#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xb00B8)
440
441#ifdef VBIF_VBIF_IN_RD_LIM_CONF3
442#undef VBIF_VBIF_IN_RD_LIM_CONF3
443#endif
444#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xb00BC)
445
446#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
447#undef VBIF_VBIF_IN_WR_LIM_CONF0
448#endif
449#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xb00C0)
450
451#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
452#undef VBIF_VBIF_IN_WR_LIM_CONF1
453#endif
454#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xb00C4)
455
456#ifdef VBIF_VBIF_IN_WR_LIM_CONF2
457#undef VBIF_VBIF_IN_WR_LIM_CONF2
458#endif
459#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xb00C8)
460
461#ifdef VBIF_VBIF_IN_WR_LIM_CONF3
462#undef VBIF_VBIF_IN_WR_LIM_CONF3
463#endif
464#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xb00CC)
465
466#ifdef VBIF_VBIF_ABIT_SHORT
467#undef VBIF_VBIF_ABIT_SHORT
468#endif
469#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xb0070)
470
471#ifdef VBIF_VBIF_ABIT_SHORT_CONF
472#undef VBIF_VBIF_ABIT_SHORT_CONF
473#endif
474#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xb0074)
475
476#ifdef VBIF_VBIF_GATE_OFF_WRREQ_EN
477#undef VBIF_VBIF_GATE_OFF_WRREQ_EN
478#endif
479#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xb00A8)
480
481#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
482#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
483#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
484#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
485#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
486#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
487#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
488#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
489
490#define DMA_CMD_OFFSET 0x048
491#define DMA_CMD_LENGTH 0x04C
492
493#define INT_CTRL 0x110
494#define CMD_MODE_DMA_SW_TRIGGER 0x090
495
496#define EOT_PACKET_CTRL 0x0CC
497#define MISR_CMD_CTRL 0x0A0
498#define MISR_VIDEO_CTRL 0x0A4
499#define VIDEO_MODE_CTRL 0x010
500#define HS_TIMER_CTRL 0x0BC
501
502#define SOFT_RESET 0x118
503#define CLK_CTRL 0x11C
504#define TRIG_CTRL 0x084
505#define CTRL 0x004
506#define COMMAND_MODE_DMA_CTRL 0x03C
507#define COMMAND_MODE_MDP_CTRL 0x040
508#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
509#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
510#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
511#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
512#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
513#define ERR_INT_MASK0 0x10C
514
515#define LANE_CTL 0x0AC
516#define LANE_SWAP_CTL 0x0B0
517#define TIMING_CTL 0x0C4
518
519#define VIDEO_MODE_ACTIVE_H 0x024
520#define VIDEO_MODE_ACTIVE_V 0x028
521#define VIDEO_MODE_TOTAL 0x02C
522#define VIDEO_MODE_HSYNC 0x030
523#define VIDEO_MODE_VSYNC 0x034
524#define VIDEO_MODE_VSYNC_VPOS 0x038
525
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]526#define VIDEO_COMPRESSION_MODE_CTRL 0x2A0
527#define VIDEO_COMPRESSION_MODE_CTRL_2 0x2A4
528#define CMD_COMPRESSION_MODE_CTRL 0x2A8
529#define CMD_COMPRESSION_MODE_CTRL_2 0x2Ac
530#define CMD_COMPRESSION_MODE_CTRL_3 0x2B0
531
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]532#define QPNP_LED_CTRL_BASE 0xD000
533#define QPNP_BLUE_LPG_CTRL_BASE 0xB100
534#define QPNP_GREEN_LPG_CTRL_BASE 0xB200
535#define QPNP_RED_LPG_CTRL_BASE 0xB300
536
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700[diff] [blame]537#define APSS_WDOG_BASE 0x9830000
538#define APPS_WDOG_BARK_VAL_REG (APSS_WDOG_BASE + 0x10)
539#define APPS_WDOG_BITE_VAL_REG (APSS_WDOG_BASE + 0x14)
540#define APPS_WDOG_RESET_REG (APSS_WDOG_BASE + 0x04)
541#define APPS_WDOG_CTL_REG (APSS_WDOG_BASE + 0x08)
542
543#define DDR_START platform_get_ddr_start()
544#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
545#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2200000
546#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x2000000
547#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]548#endif