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Sridhar Parasurambe12c3d2015-01-16 13:42:26 -08001/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
Channagoud Kadabied60a8b2014-06-27 15:35:09 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
Channagoud Kadabi0ffa7862015-03-19 11:58:28 -070016 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070027 */
28
29#include <debug.h>
30#include <reg.h>
31#include <platform/iomap.h>
32#include <qgic.h>
33#include <qtimer.h>
34#include <platform/clock.h>
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070035#include <arch/arm/mmu.h>
Channagoud Kadabi428a2132015-06-17 17:32:01 -070036#include <mmu.h>
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070037#include <smem.h>
38#include <board.h>
Channagoud Kadabid2f06a22015-06-23 18:25:42 -070039#include <target/display.h>
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070040
41#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
42#define MSM_SHARED_SIZE 2
43
Channagoud Kadabi45855f72015-07-07 15:06:28 -070044/* LK memory - cacheable, write back */
45#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070046 MMU_MEMORY_AP_READ_WRITE)
47
48/* Peripherals - non-shared device */
49#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
Channagoud Kadabi428a2132015-06-17 17:32:01 -070050 MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN | MMU_MEMORY_PXN)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070051
Channagoud Kadabi45855f72015-07-07 15:06:28 -070052/* SCRATCH memory - cacheable, write back */
53#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070054 MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
55
Channagoud Kadabi428a2132015-06-17 17:32:01 -070056/* COMMON memory - cacheable, write through */
57#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
58 MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
59
Channagoud Kadabia71f0722015-08-11 16:21:40 -070060/* downlaod mode memory - cacheable, write through */
61#define DLOAD_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
62 MMU_MEMORY_AP_READ_ONLY | MMU_MEMORY_XN)
63
Channagoud Kadabi2324bd52015-07-13 15:02:20 -070064static uint64_t ddr_start;
Channagoud Kadabi428a2132015-06-17 17:32:01 -070065
66static mmu_section_t default_mmu_section_table[] =
67{
Channagoud Kadabi2324bd52015-07-13 15:02:20 -070068/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
Channagoud Kadabid2f06a22015-06-23 18:25:42 -070069 { 0x00000000, 0x00000000, MMU_L2_NS_SECTION_MAPPING, 512, IOMAP_MEMORY},
Channagoud Kadabi428a2132015-06-17 17:32:01 -070070 { MEMBASE, MEMBASE, MMU_L2_NS_SECTION_MAPPING, (MEMSIZE / MB), LK_MEMORY},
71 { SCRATCH_ADDR, SCRATCH_ADDR, MMU_L2_NS_SECTION_MAPPING, SCRATCH_SIZE, SCRATCH_MEMORY},
72 { MSM_SHARED_BASE, MSM_SHARED_BASE, MMU_L2_NS_SECTION_MAPPING, MSM_SHARED_SIZE, COMMON_MEMORY},
73 { RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF, MMU_L2_NS_SECTION_MAPPING, RPMB_SND_RCV_BUF_SZ, IOMAP_MEMORY},
74};
75
Channagoud Kadabi2324bd52015-07-13 15:02:20 -070076static mmu_section_t default_mmu_section_table_3gb[] =
77{
78/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
79 { 0x40000000, 0x40000000, MMU_L1_NS_SECTION_MAPPING, 1024 , COMMON_MEMORY},
80 { 0x80000000, 0x80000000, MMU_L2_NS_SECTION_MAPPING, 88 , COMMON_MEMORY},
81};
82
83
Channagoud Kadabia71f0722015-08-11 16:21:40 -070084/* Map the ddr for download mode, this region belongs to non-hlos images and pil */
Channagoud Kadabi428a2132015-06-17 17:32:01 -070085static mmu_section_t dload_mmu_section_table[] =
86{
Channagoud Kadabia71f0722015-08-11 16:21:40 -070087/* Physical addr, Virtual addr, Mapping type , Size (in MB), Flags */
88 { 0x85800000, 0x85800000, MMU_L2_NS_SECTION_MAPPING, 8, DLOAD_MEMORY},
89 { 0x86200000, 0x86200000, MMU_L2_NS_SECTION_MAPPING, 174, DLOAD_MEMORY},
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070090};
91
92void platform_early_init(void)
93{
94 board_init();
95 platform_clock_init();
96 qgic_init();
97 qtimer_init();
98 scm_init();
99}
100
101void platform_init(void)
102{
103 dprintf(INFO, "platform_init()\n");
104}
105
106void platform_uninit(void)
107{
108#if DISPLAY_SPLASH_SCREEN
109 display_shutdown();
110#endif
111
112 qtimer_uninit();
113}
114
115int platform_use_identity_mmu_mappings(void)
116{
117 /* Use only the mappings specified in this file. */
118 return 0;
119}
120
121/* Setup memory for this platform */
122void platform_init_mmu_mappings(void)
123{
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700124 int i;
125 int table_sz = ARRAY_SIZE(default_mmu_section_table);
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700126 mmu_section_t kernel_mmu_section_table;
127 uint64_t ddr_size = smem_get_ddr_size();
Channagoud Kadabia71f0722015-08-11 16:21:40 -0700128 uint32_t kernel_size = 0;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700129
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700130 if (ddr_size == MEM_4GB)
131 {
132 ddr_start = 0x80000000;
Channagoud Kadabia71f0722015-08-11 16:21:40 -0700133 /* As per the memory map when DDR is 4GB first 88 MB is hlos memory
134 * use this for loading the kernel
135 */
136 kernel_size = 88;
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700137 }
138 else if (ddr_size == MEM_3GB)
139 {
140 ddr_start = 0x20000000;
Channagoud Kadabia71f0722015-08-11 16:21:40 -0700141 /* As per memory map wheh DDR is 3GB the first 512 MB is assigned to hlos
142 * use this region for loading kernel
143 */
144 kernel_size = 512;
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700145 }
146 else
147 {
148 dprintf(CRITICAL, "Unsupported memory map\n");
149 ASSERT(0);
150 }
151
152 kernel_mmu_section_table.paddress = ddr_start;
153 kernel_mmu_section_table.vaddress = ddr_start;
154 kernel_mmu_section_table.type = MMU_L2_NS_SECTION_MAPPING;
Channagoud Kadabia71f0722015-08-11 16:21:40 -0700155 kernel_mmu_section_table.size = kernel_size;
156 kernel_mmu_section_table.flags = SCRATCH_MEMORY;
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700157
158 /* Map kernel entry */
159 arm_mmu_map_entry(&kernel_mmu_section_table);
160
161 /* Map default memory needed for lk , scratch, rpmb & iomap */
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700162 for (i = 0 ; i < table_sz; i++)
163 arm_mmu_map_entry(&default_mmu_section_table[i]);
164
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700165 /* Map the rest of the DDR for 3GB needed for ramdump */
166 if (ddr_size == MEM_3GB)
167 {
168 for (i = 0 ; i < (int)ARRAY_SIZE(default_mmu_section_table_3gb); i++)
169 arm_mmu_map_entry(&default_mmu_section_table_3gb[i]);
170 }
171
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700172 if (scm_device_enter_dload())
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700173 {
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700174 /* TZ & Hyp memory can be mapped only while entering the download mode */
175 table_sz = ARRAY_SIZE(dload_mmu_section_table);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700176
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700177 for (i = 0 ; i < table_sz; i++)
178 arm_mmu_map_entry(&dload_mmu_section_table[i]);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700179 }
180}
181
182addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
183{
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700184 return virtual_to_physical_mapping(virt_addr);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700185}
186
187addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
188{
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700189 return physical_to_virtual_mapping(phys_addr);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700190}
191
192uint32_t platform_get_sclk_count(void)
193{
194 return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
195}
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800196
197addr_t get_bs_info_addr()
198{
199 return BS_INFO_ADDR;
200}
Channagoud Kadabi652a6f62014-11-17 17:23:23 -0800201
202uint32_t platform_get_qmp_rev()
203{
204 return readl(USB3_PHY_REVISION_ID3) << 24 | readl(USB3_PHY_REVISION_ID2) << 16 |
205 readl(USB3_PHY_REVISION_ID1) << 8 | readl(USB3_PHY_REVISION_ID0);
206}
Channagoud Kadabi1fc3c682015-03-29 19:49:11 -0700207
208uint32_t platform_get_max_periph()
209{
210 return 256;
211}
Channagoud Kadabi53a21262015-04-09 16:18:23 -0700212
213int platform_is_msm8996()
214{
215 if (board_platform_id() == MSM8996)
216 return 1;
217 else
218 return 0;
219}
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700220
221uint64_t platform_get_ddr_start()
222{
223 return ddr_start;
224}