Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
| 11 | * * Neither the name of Code Aurora nor |
| 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <stdint.h> |
| 30 | #include <debug.h> |
| 31 | #include <kernel/thread.h> |
| 32 | #include <platform/iomap.h> |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame^] | 33 | #include <platform/clock.h> |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 34 | #include <reg.h> |
| 35 | |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame^] | 36 | /* Read, modify, then write-back a register. */ |
| 37 | static void rmwreg(uint32_t val, uint32_t reg, uint32_t mask) |
| 38 | { |
| 39 | uint32_t regval = readl(reg); |
| 40 | regval &= ~mask; |
| 41 | regval |= val; |
| 42 | writel(regval, reg); |
| 43 | } |
| 44 | |
| 45 | |
| 46 | void config_mdp_axi_clk(uint8_t use_pxo){ |
| 47 | /* Program MM_PLL0 (PLL1) @ 1320 MHz and turn it on. */ |
| 48 | rmwreg(0, MM_PLL0_MODE_REG, (1<<0)); /* Disable output */ |
| 49 | writel(48, MM_PLL0_L_VAL_REG); |
| 50 | writel(8, MM_PLL0_M_VAL_REG); |
| 51 | writel(9, MM_PLL0_N_VAL_REG); |
| 52 | /* Set ref, enable. */ |
| 53 | if (use_pxo) |
| 54 | rmwreg((1<<1), MM_PLL0_MODE_REG, (1<<4)|(1<<1)); /* PXO */ |
| 55 | else |
| 56 | rmwreg((1<<4)|(1<<1), MM_PLL0_MODE_REG, (1<<4)|(1<<1)); /* MXO */ |
| 57 | udelay(10); |
| 58 | writel(0x14580, MM_PLL0_CONFIG_REG); /* Enable MN, set VCO, misc */ |
| 59 | rmwreg((1<<2), MM_PLL0_MODE_REG, (1<<2)); /* Deassert reset */ |
| 60 | rmwreg((1<<0), MM_PLL0_MODE_REG, (1<<0)); /* Enable output */ |
| 61 | |
| 62 | /* Set up MM AHB clock to PLL8/5. */ |
| 63 | //local_src_enable(PLL_8); |
| 64 | rmwreg(0x0102, AHB_NS_REG, 0x43C7); |
| 65 | udelay(200); /* Wait before using registers clocked by MM AHB_CLK. */ |
| 66 | |
| 67 | /* Set up MM Fabric (AXI). */ |
| 68 | writel(0x4248451, AXI_NS_REG); |
| 69 | } |
| 70 | |
| 71 | |
| 72 | /* Enable/disable for non-shared NT PLLs. */ |
| 73 | int nt_pll_enable(uint8_t src, uint8_t enable) |
| 74 | { |
| 75 | static const struct { |
| 76 | uint32_t const mode_reg; |
| 77 | uint32_t const status_reg; |
| 78 | } pll_reg[] = { |
| 79 | [PLL_1] = { MM_PLL0_MODE_REG, MM_PLL0_STATUS_REG }, |
| 80 | [PLL_2] = { MM_PLL1_MODE_REG, MM_PLL1_STATUS_REG }, |
| 81 | [PLL_3] = { MM_PLL2_MODE_REG, MM_PLL2_STATUS_REG }, |
| 82 | }; |
| 83 | uint32_t pll_mode; |
| 84 | |
| 85 | pll_mode = readl(pll_reg[src].mode_reg); |
| 86 | if (enable) { |
| 87 | /* Disable PLL bypass mode. */ |
| 88 | pll_mode |= (1<<1); |
| 89 | writel( pll_mode, pll_reg[src].mode_reg); |
| 90 | |
| 91 | /* H/W requires a 5us delay between disabling the bypass and |
| 92 | * de-asserting the reset. Delay 10us just to be safe. */ |
| 93 | udelay(10); |
| 94 | |
| 95 | /* De-assert active-low PLL reset. */ |
| 96 | pll_mode |= (1<<2); |
| 97 | writel( pll_mode, pll_reg[src].mode_reg); |
| 98 | |
| 99 | /* Enable PLL output. */ |
| 100 | pll_mode |= (1<<0); |
| 101 | writel( pll_mode, pll_reg[src].mode_reg); |
| 102 | |
| 103 | /* Wait until PLL is enabled. */ |
| 104 | while (!readl(pll_reg[src].status_reg)); |
| 105 | } else { |
| 106 | /* Disable the PLL output, disable test mode, enable |
| 107 | * the bypass mode, and assert the reset. */ |
| 108 | pll_mode &= 0xFFFFFFF0; |
| 109 | writel( pll_mode, pll_reg[src].mode_reg); |
| 110 | } |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | |
| 115 | |
| 116 | /* Write the M,N,D values and enable the MDP Core Clock */ |
| 117 | void config_mdp_clk( uint32_t ns, |
| 118 | uint32_t md, |
| 119 | uint32_t cc, |
| 120 | uint32_t ns_addr, |
| 121 | uint32_t md_addr, |
| 122 | uint32_t cc_addr) |
| 123 | { |
| 124 | int val = 0; |
| 125 | |
| 126 | /* MN counter reset */ |
| 127 | val = 1 << 31; |
| 128 | writel(val, ns_addr); |
| 129 | |
| 130 | /* Write the MD and CC register values */ |
| 131 | writel(md, md_addr); |
| 132 | writel(cc, cc_addr); |
| 133 | |
| 134 | /* Reset the clk control, and Write ns val */ |
| 135 | val = 1 << 31; |
| 136 | val |= ns; |
| 137 | writel(val, ns_addr); |
| 138 | |
| 139 | /* Clear MN counter reset */ |
| 140 | val = 1 << 31; |
| 141 | val = ~val; |
| 142 | val = val & readl(ns_addr); |
| 143 | writel(val, ns_addr); |
| 144 | |
| 145 | /* Enable MND counter */ |
| 146 | val = 1 << 8; |
| 147 | val = val | readl(cc_addr); |
| 148 | writel(val, cc_addr); |
| 149 | |
| 150 | /* Enable the root of the clock tree */ |
| 151 | val = 1 << 2; |
| 152 | val = val | readl(cc_addr); |
| 153 | writel(val, cc_addr); |
| 154 | |
| 155 | /* Enable the MDP Clock */ |
| 156 | val = 1 << 0; |
| 157 | val = val | readl(cc_addr); |
| 158 | writel(val, cc_addr); |
| 159 | } |
| 160 | |
| 161 | /* Write the M,N,D values and enable the Pixel Core Clock */ |
| 162 | void config_pixel_clk( uint32_t ns, |
| 163 | uint32_t md, |
| 164 | uint32_t cc, |
| 165 | uint32_t ns_addr, |
| 166 | uint32_t md_addr, |
| 167 | uint32_t cc_addr){ |
| 168 | unsigned int val = 0; |
| 169 | |
| 170 | /* Activate the reset for the M/N Counter */ |
| 171 | val = 1 << 7; |
| 172 | writel(val, ns_addr); |
| 173 | |
| 174 | /* Write the MD and CC register values */ |
| 175 | writel(md, md_addr); |
| 176 | writel(cc, cc_addr); |
| 177 | |
| 178 | /* Write the ns value, and active reset for M/N Counter, again */ |
| 179 | val = 1 << 7; |
| 180 | val |= ns; |
| 181 | writel(val, ns_addr); |
| 182 | |
| 183 | /* De-activate the reset for M/N Counter */ |
| 184 | val = 1 << 7; |
| 185 | val = ~val; |
| 186 | val = val & readl(ns_addr); |
| 187 | writel(val, ns_addr); |
| 188 | |
| 189 | /* Enable MND counter */ |
| 190 | val = 1 << 5; |
| 191 | val = val | readl(cc_addr); |
| 192 | writel(val, cc_addr); |
| 193 | |
| 194 | /* Enable the root of the clock tree */ |
| 195 | val = 1 << 2; |
| 196 | val = val | readl(cc_addr); |
| 197 | writel(val, cc_addr); |
| 198 | |
| 199 | /* Enable the MDP Clock */ |
| 200 | val = 1 << 0; |
| 201 | val = val | readl(cc_addr); |
| 202 | writel(val, cc_addr); |
| 203 | |
| 204 | /* Enable the LCDC Clock */ |
| 205 | val = 1 << 8; |
| 206 | val = val | readl(cc_addr); |
| 207 | writel(val, cc_addr); |
| 208 | } |
| 209 | |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 210 | /* Set rate and enable the clock */ |
| 211 | void clock_config(uint32_t ns, |
| 212 | uint32_t md, |
| 213 | uint32_t ns_addr, |
| 214 | uint32_t md_addr) |
| 215 | { |
| 216 | unsigned int val = 0; |
| 217 | |
| 218 | /* Activate the reset for the M/N Counter */ |
| 219 | val = 1 << 7; |
| 220 | writel(val, ns_addr); |
| 221 | |
| 222 | /* Write the MD value into the MD register */ |
| 223 | writel(md, md_addr); |
| 224 | |
| 225 | /* Write the ns value, and active reset for M/N Counter, again */ |
| 226 | val = 1 << 7; |
| 227 | val |= ns; |
| 228 | writel(val, ns_addr); |
| 229 | |
| 230 | /* De-activate the reset for M/N Counter */ |
| 231 | val = 1 << 7; |
| 232 | val = ~val; |
| 233 | val = val & readl(ns_addr); |
| 234 | writel(val, ns_addr); |
| 235 | |
| 236 | /* Enable the M/N Counter */ |
| 237 | val = 1 << 8; |
| 238 | val = val | readl(ns_addr); |
| 239 | writel(val, ns_addr); |
| 240 | |
| 241 | /* Enable the Clock Root */ |
| 242 | val = 1 << 11; |
| 243 | val = val | readl(ns_addr); |
| 244 | writel(val, ns_addr); |
| 245 | |
| 246 | /* Enable the Clock Branch */ |
| 247 | val = 1 << 9; |
| 248 | val = val | readl(ns_addr); |
| 249 | writel(val, ns_addr); |
| 250 | } |
| 251 | |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 252 | void acpu_clock_init (void) |
| 253 | { |
| 254 | } |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 255 | |
| 256 | void hsusb_clock_init(void) |
| 257 | { |
| 258 | int val; |
| 259 | /* Vote for PLL8 */ |
| 260 | val = readl(0x009034C0); |
| 261 | val |= (1<<8); |
| 262 | writel(val, 0x009034C0); |
| 263 | /* Wait until PLL is enabled. */ |
| 264 | while (!(readl(0x00903158) & (1<<16))); |
| 265 | |
| 266 | //Set 7th bit in NS Register |
| 267 | val = 1 << 7; |
| 268 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 269 | |
| 270 | //Set rate specific value in MD |
| 271 | writel(0x000500DF, USB_HS1_XVCR_FS_CLK_MD); |
| 272 | |
| 273 | //Set value in NS register |
| 274 | val = 1 << 7; |
| 275 | val |= 0x00E400C3; |
| 276 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 277 | |
| 278 | // Clear 7th bit |
| 279 | val = 1 << 7; |
| 280 | val = ~val; |
| 281 | val = val & readl(USB_HS1_XVCR_FS_CLK_NS); |
| 282 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 283 | |
| 284 | //set 11th bit |
| 285 | val = 1 << 11; |
| 286 | val |= readl(USB_HS1_XVCR_FS_CLK_NS); |
| 287 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 288 | |
| 289 | //set 9th bit |
| 290 | val = 1 << 9; |
| 291 | val |= readl(USB_HS1_XVCR_FS_CLK_NS); |
| 292 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 293 | |
| 294 | //set 8th bit |
| 295 | val = 1 << 8; |
| 296 | val |= readl(USB_HS1_XVCR_FS_CLK_NS); |
| 297 | writel(val, USB_HS1_XVCR_FS_CLK_NS); |
| 298 | } |
| 299 | |