Padmanabhan Komanduru | 40f0d3c | 2018-04-26 17:41:17 +0530 | [diff] [blame^] | 1 | /* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved. |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _PLATFORM_MSM_SHARED_MIPI_DSI_H_ |
| 31 | #define _PLATFORM_MSM_SHARED_MIPI_DSI_H_ |
| 32 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 33 | #include <msm_panel.h> |
| 34 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 35 | #define PASS 0 |
| 36 | #define FAIL 1 |
| 37 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 38 | /* |
| 39 | * DSI register offsets defined here are only used for non-MDSS targets. |
| 40 | * For MDSS targets, all offset definitions are picked up from corresponding |
| 41 | * target files. |
| 42 | */ |
| 43 | #if (DISPLAY_TYPE_MDSS == 0) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 44 | #define DSI_CLKOUT_TIMING_CTRL REG_DSI(0x0C0) |
| 45 | #define DSI_SOFT_RESET REG_DSI(0x114) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 46 | #define DSIPHY_SW_RESET REG_DSI(0x128) |
| 47 | #define DSIPHY_PLL_RDY REG_DSI(0x280) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 48 | #define DSI_CLK_CTRL REG_DSI(0x118) |
| 49 | #define DSI_TRIG_CTRL REG_DSI(0x080) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 50 | #define DSI_COMMAND_MODE_DMA_CTRL REG_DSI(0x038) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 51 | #define DSI_ERR_INT_MASK0 REG_DSI(0x108) |
| 52 | #define DSI_INT_CTRL REG_DSI(0x10C) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 53 | #define DSI_CMD_MODE_DMA_SW_TRIGGER REG_DSI(0x08C) |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 54 | #define DSI_DMA_CMD_OFFSET REG_DSI(0x044) |
| 55 | #define DSI_DMA_CMD_LENGTH REG_DSI(0x048) |
| 56 | #define DSI_CTRL REG_DSI(0x000) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 57 | #define DSI_CMD_MODE_MDP_SW_TRIGGER REG_DSI(0x090) |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 58 | #endif |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 59 | |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 60 | #define DSI_VIDEO_MODE_DONE_MASK BIT(17) |
| 61 | #define DSI_VIDEO_MODE_DONE_AK BIT(16) |
| 62 | #define DSI_VIDEO_MODE_DONE_STAT BIT(16) |
| 63 | |
Dhaval Patel | 33ff98f | 2014-04-15 14:44:31 -0700 | [diff] [blame] | 64 | /********************************************************** |
| 65 | DSI register configuration options |
| 66 | **********************************************************/ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 67 | #define MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */ |
| 68 | #define MIPI_DSI_REG_LEN 16 /* 4 x 4 bytes register */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 69 | |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 70 | #define TIMING_FLUSH 0x1E4 |
| 71 | #define TIMING_DB_MODE 0x1E8 |
| 72 | |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 73 | #define DSI_HW_REV_103 0x10030000 /* 8994 */ |
Padmanabhan Komanduru | 0a74989 | 2015-06-15 15:38:59 +0530 | [diff] [blame] | 74 | #define DSI_HW_REV_103_1 0x10030001 /* 8936/8939/8952 */ |
| 75 | #define DSI_HW_REV_104_2 0x10040002 /* 8956 */ |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 76 | #define DSI_HW_REV_104 0x10040000 /* thulium */ |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 77 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 78 | #define DTYPE_GEN_WRITE2 0x23 /* 4th Byte is 0x80 */ |
| 79 | #define DTYPE_GEN_LWRITE 0x29 /* 4th Byte is 0xc0 */ |
| 80 | #define DTYPE_DCS_WRITE1 0x15 /* 4th Byte is 0x80 */ |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 81 | |
Shivaraj Shetty | 5cbb746 | 2014-01-13 17:17:39 +0530 | [diff] [blame] | 82 | #define RDBK_DATA0 0x06C |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 83 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 84 | #define MIPI_VIDEO_MODE 1 |
| 85 | #define MIPI_CMD_MODE 2 |
| 86 | |
Dhaval Patel | 33ff98f | 2014-04-15 14:44:31 -0700 | [diff] [blame] | 87 | #define DSI_NON_BURST_SYNCH_PULSE 0 |
| 88 | #define DSI_NON_BURST_SYNCH_EVENT 1 |
| 89 | #define DSI_BURST_MODE 2 |
| 90 | |
| 91 | #define DSI_RGB_SWAP_RGB 0 |
| 92 | #define DSI_RGB_SWAP_RBG 1 |
| 93 | #define DSI_RGB_SWAP_BGR 2 |
| 94 | #define DSI_RGB_SWAP_BRG 3 |
| 95 | #define DSI_RGB_SWAP_GRB 4 |
| 96 | #define DSI_RGB_SWAP_GBR 5 |
| 97 | |
| 98 | #define DSI_VIDEO_DST_FORMAT_RGB565 0 |
| 99 | #define DSI_VIDEO_DST_FORMAT_RGB666 1 |
| 100 | #define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2 |
| 101 | #define DSI_VIDEO_DST_FORMAT_RGB888 3 |
| 102 | |
| 103 | #define DSI_CMD_DST_FORMAT_RGB111 0 |
| 104 | #define DSI_CMD_DST_FORMAT_RGB332 3 |
| 105 | #define DSI_CMD_DST_FORMAT_RGB444 4 |
| 106 | #define DSI_CMD_DST_FORMAT_RGB565 6 |
| 107 | #define DSI_CMD_DST_FORMAT_RGB666 7 |
| 108 | #define DSI_CMD_DST_FORMAT_RGB888 8 |
| 109 | |
| 110 | #define DSI_CMD_TRIGGER_NONE 0x0 /* mdp trigger */ |
| 111 | #define DSI_CMD_TRIGGER_TE 0x02 |
| 112 | #define DSI_CMD_TRIGGER_SW 0x04 |
| 113 | #define DSI_CMD_TRIGGER_SW_SEOF 0x05 /* cmd dma only */ |
| 114 | #define DSI_CMD_TRIGGER_SW_TE 0x06 |
| 115 | |
| 116 | #define DSI_DATALANE_SWAP_0123 0 |
| 117 | #define DSI_DATALANE_SWAP_3012 1 |
| 118 | #define DSI_DATALANE_SWAP_2301 2 |
| 119 | #define DSI_DATALANE_SWAP_1230 3 |
| 120 | #define DSI_DATALANE_SWAP_0321 4 |
| 121 | #define DSI_DATALANE_SWAP_1032 5 |
| 122 | #define DSI_DATALANE_SWAP_2103 6 |
| 123 | #define DSI_DATALANE_SWAP_3210 7 |
| 124 | |
| 125 | #define MAX_REGULATOR_CONFIG 7 |
| 126 | #define MAX_BIST_CONFIG 6 |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 127 | #define MAX_TIMING_CONFIG 40 |
Dhaval Patel | 33ff98f | 2014-04-15 14:44:31 -0700 | [diff] [blame] | 128 | #define MAX_LANE_CONFIG 45 |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 129 | #define MAX_STRENGTH_CONFIG 10 |
Dhaval Patel | 33ff98f | 2014-04-15 14:44:31 -0700 | [diff] [blame] | 130 | #define MAX_CTRL_CONFIG 4 |
| 131 | |
| 132 | /********************************************************** |
| 133 | DSI configuration structures |
| 134 | **********************************************************/ |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 135 | struct mipi_dsi_phy_ctrl { |
Dhaval Patel | 33ff98f | 2014-04-15 14:44:31 -0700 | [diff] [blame] | 136 | uint32_t regulator[5]; |
| 137 | uint32_t timing[12]; |
| 138 | uint32_t ctrl[4]; |
| 139 | uint32_t strength[4]; |
| 140 | uint32_t pll[21]; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 141 | }; |
| 142 | |
Mao Flynn | 5f137ed | 2014-04-18 14:59:47 +0800 | [diff] [blame] | 143 | enum dsi_reg_mode { |
| 144 | DSI_PHY_REGULATOR_DCDC_MODE, |
| 145 | DSI_PHY_REGULATOR_LDO_MODE, |
| 146 | }; |
| 147 | |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 148 | enum { |
| 149 | DSI_PLL_TYPE_28NM, |
| 150 | DSI_PLL_TYPE_20NM, |
| 151 | DSI_PLL_TYPE_THULIUM, |
Padmanabhan Komanduru | 40f0d3c | 2018-04-26 17:41:17 +0530 | [diff] [blame^] | 152 | DSI_PLL_TYPE_12NM, |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 153 | DSI_PLL_TYPE_MAX, |
| 154 | }; |
| 155 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 156 | struct mdss_dsi_phy_ctrl { |
Dhaval Patel | 33ff98f | 2014-04-15 14:44:31 -0700 | [diff] [blame] | 157 | uint32_t regulator[MAX_REGULATOR_CONFIG]; |
| 158 | uint32_t timing[MAX_TIMING_CONFIG]; |
| 159 | uint32_t ctrl[MAX_CTRL_CONFIG]; |
| 160 | uint32_t strength[MAX_STRENGTH_CONFIG]; |
| 161 | char bistCtrl[MAX_BIST_CONFIG]; |
| 162 | char laneCfg[MAX_LANE_CONFIG]; |
Mao Flynn | 5f137ed | 2014-04-18 14:59:47 +0800 | [diff] [blame] | 163 | enum dsi_reg_mode regulator_mode; |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 164 | int pll_type; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 165 | }; |
| 166 | |
Padmanabhan Komanduru | 1fc8bc4 | 2015-12-21 18:30:46 +0530 | [diff] [blame] | 167 | struct ssc_params { |
| 168 | uint32_t kdiv; |
| 169 | uint64_t triang_inc_7_0; |
| 170 | uint64_t triang_inc_9_8; |
| 171 | uint64_t triang_steps; |
| 172 | uint64_t dc_offset; |
| 173 | uint64_t freq_seed_7_0; |
| 174 | uint64_t freq_seed_15_8; |
| 175 | }; |
| 176 | |
| 177 | struct mdss_dsi_vco_calc { |
| 178 | uint64_t sdm_cfg0; |
| 179 | uint64_t sdm_cfg1; |
| 180 | uint64_t sdm_cfg2; |
| 181 | uint64_t sdm_cfg3; |
| 182 | uint64_t cal_cfg10; |
| 183 | uint64_t cal_cfg11; |
| 184 | uint64_t refclk_cfg; |
| 185 | uint64_t gen_vco_clk; |
| 186 | uint32_t lpfr_lut_res; |
| 187 | struct ssc_params ssc; |
| 188 | }; |
| 189 | |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 190 | struct mdss_dsi_pll_config { |
Arpita Banerjee | 2522bc6 | 2013-05-24 16:03:53 -0700 | [diff] [blame] | 191 | uint32_t pixel_clock; |
| 192 | uint32_t pixel_clock_mhz; |
| 193 | uint32_t byte_clock; |
| 194 | uint32_t bit_clock; |
| 195 | uint32_t halfbit_clock; |
| 196 | uint32_t vco_clock; |
Padmanabhan Komanduru | 0597502 | 2014-04-17 16:47:34 +0530 | [diff] [blame] | 197 | uint32_t vco_delay; |
Chandan Uddaraju | 34dda2a | 2015-02-04 14:33:16 -0800 | [diff] [blame] | 198 | uint32_t vco_min; |
| 199 | uint32_t vco_max; |
| 200 | uint32_t en_vco_zero_phase; |
Arpita Banerjee | 2522bc6 | 2013-05-24 16:03:53 -0700 | [diff] [blame] | 201 | uint8_t directpath; |
| 202 | uint8_t posdiv1; |
| 203 | uint8_t posdiv3; |
| 204 | uint8_t pclk_m; |
| 205 | uint8_t pclk_n; |
| 206 | uint8_t pclk_d; |
Dhaval Patel | d19fcf1 | 2014-08-12 13:16:05 -0700 | [diff] [blame] | 207 | |
Padmanabhan Komanduru | 1fc8bc4 | 2015-12-21 18:30:46 +0530 | [diff] [blame] | 208 | /* SSC related params */ |
| 209 | bool ssc_en; |
| 210 | bool is_center_spread; |
| 211 | uint32_t ssc_freq; |
| 212 | uint32_t ssc_ppm; |
| 213 | |
Dhaval Patel | d19fcf1 | 2014-08-12 13:16:05 -0700 | [diff] [blame] | 214 | /* pll 20nm */ |
| 215 | uint32_t dec_start; |
| 216 | uint32_t frac_start; |
| 217 | uint32_t lock_comp; |
| 218 | uint8_t hr_oclk2; |
| 219 | uint8_t hr_oclk3; |
| 220 | uint8_t lp_div_mux; |
| 221 | uint8_t ndiv; |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 222 | |
| 223 | /* pll thulium */ |
| 224 | uint32_t postdiv; |
| 225 | uint32_t n1div; |
| 226 | uint32_t n2div; |
Padmanabhan Komanduru | 40f0d3c | 2018-04-26 17:41:17 +0530 | [diff] [blame^] | 227 | |
| 228 | /* pll 12nm */ |
| 229 | uint32_t p_div_mux; |
| 230 | uint32_t gp_div_mux; |
| 231 | uint32_t divhf; |
Arpita Banerjee | 2522bc6 | 2013-05-24 16:03:53 -0700 | [diff] [blame] | 232 | }; |
| 233 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 234 | struct mipi_dsi_cmd { |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 235 | uint32_t size; |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 236 | char *payload; |
Sangani Suryanarayana Raju | 769f9ac | 2013-04-30 19:05:06 +0530 | [diff] [blame] | 237 | int wait; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 238 | }; |
| 239 | |
Vineet Bajaj | c227246 | 2015-05-07 17:35:03 +0530 | [diff] [blame] | 240 | struct mipi_dsi_i2c_cmd { |
| 241 | uint8_t i2c_addr; |
| 242 | uint8_t reg; |
| 243 | uint8_t val; |
| 244 | int sleep_in_ms; |
| 245 | }; |
| 246 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 247 | struct mipi_dsi_panel_config { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 248 | char mode; |
| 249 | char num_of_lanes; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 250 | char lane_swap; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 251 | char pack; |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 252 | uint8_t t_clk_pre; |
| 253 | uint8_t t_clk_post; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 254 | struct mipi_dsi_phy_ctrl *dsi_phy_config; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 255 | struct mdss_dsi_phy_ctrl *mdss_dsi_phy_config; |
Padmanabhan Komanduru | b3d3184 | 2014-11-04 15:47:53 +0530 | [diff] [blame] | 256 | struct mipi_dsi_cmd *panel_on_cmds; |
| 257 | int num_of_panel_on_cmds; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 258 | uint32_t signature; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 259 | char cmds_post_tg; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 260 | }; |
| 261 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 262 | enum { /* mipi dsi panel */ |
| 263 | DSI_VIDEO_MODE, |
| 264 | DSI_CMD_MODE, |
| 265 | }; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 266 | |
Dhaval Patel | 33ff98f | 2014-04-15 14:44:31 -0700 | [diff] [blame] | 267 | /********************************************************** |
| 268 | APIs |
| 269 | **********************************************************/ |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 270 | int mipi_config(struct msm_fb_panel_data *panel); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 271 | int mdss_dsi_config(struct msm_fb_panel_data *panel); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 272 | void mdss_dsi_phy_sw_reset(uint32_t ctl_base); |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 273 | int mdss_dsi_phy_init(struct mipi_panel_info *mipi); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 274 | void mdss_dsi_phy_contention_detection(struct mipi_panel_info *mipi, |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 275 | uint32_t phy_base); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 276 | int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 277 | |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 278 | int mdss_dsi_video_mode_config(struct msm_panel_info *pinfo, |
| 279 | uint16_t disp_width, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 280 | uint16_t disp_height, |
| 281 | uint16_t img_width, |
| 282 | uint16_t img_height, |
| 283 | uint16_t hsync_porch0_fp, |
| 284 | uint16_t hsync_porch0_bp, |
| 285 | uint16_t vsync_porch0_fp, |
| 286 | uint16_t vsync_porch0_bp, |
| 287 | uint16_t hsync_width, |
| 288 | uint16_t vsync_width, |
| 289 | uint16_t dst_format, |
| 290 | uint16_t traffic_mode, |
| 291 | uint8_t lane_en, |
Padmanabhan Komanduru | e320987 | 2015-01-12 16:33:16 +0530 | [diff] [blame] | 292 | uint8_t pulse_mode_hsa_he, |
| 293 | uint32_t low_pwr_stop_mode, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 294 | uint8_t eof_bllp_pwr, |
| 295 | uint8_t interleav, |
| 296 | uint32_t ctl_base); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 297 | int mdss_dsi_cmd_mode_config(struct msm_panel_info *pinfo, |
| 298 | uint16_t disp_width, |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 299 | uint16_t disp_height, |
| 300 | uint16_t img_width, |
| 301 | uint16_t img_height, |
| 302 | uint16_t dst_format, |
| 303 | uint8_t ystride, |
| 304 | uint8_t lane_en, |
| 305 | uint8_t interleav, |
| 306 | uint32_t ctl_base); |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 307 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 308 | int mipi_dsi_on(struct msm_panel_info *pinfo); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 309 | int mipi_cmd_trigger(); |
Siddhartha Agrawal | 24d81b5 | 2013-07-01 11:13:32 -0700 | [diff] [blame] | 310 | int mipi_dsi_off(struct msm_panel_info *pinfo); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 311 | int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi, |
| 312 | struct mipi_dsi_cmd *cmds, int count, char dual_dsi); |
| 313 | int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, uint32_t **rp, int rp_len, |
| 314 | int rdbk_len); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 315 | int32_t mdss_dsi_auto_pll_config(uint32_t pll_base, uint32_t ctl_base, |
| 316 | struct mdss_dsi_pll_config *pd); |
Aravind Venkateswaran | f270235 | 2015-07-23 18:14:13 -0700 | [diff] [blame] | 317 | void mdss_dsi_auto_pll_20nm_config(struct msm_panel_info *pinfo); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 318 | void mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base); |
| 319 | uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base); |
| 320 | void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t pll_base); |
| 321 | void mdss_dsi_uniphy_pll_sw_reset(uint32_t pll_base); |
| 322 | int mdss_dsi_post_on(struct msm_fb_panel_data *panel); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 323 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 324 | #endif |