Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <debug.h> |
| 30 | #include <platform/iomap.h> |
| 31 | #include <platform/irqs.h> |
| 32 | #include <platform/gpio.h> |
| 33 | #include <reg.h> |
| 34 | #include <target.h> |
| 35 | #include <platform.h> |
| 36 | #include <dload_util.h> |
| 37 | #include <uart_dm.h> |
| 38 | #include <mmc.h> |
| 39 | #include <spmi.h> |
| 40 | #include <board.h> |
| 41 | #include <smem.h> |
| 42 | #include <baseband.h> |
| 43 | #include <dev/keys.h> |
| 44 | #include <pm8x41.h> |
| 45 | #include <crypto5_wrapper.h> |
| 46 | #include <hsusb.h> |
| 47 | #include <clock.h> |
| 48 | #include <partition_parser.h> |
| 49 | #include <scm.h> |
| 50 | #include <platform/clock.h> |
| 51 | #include <platform/gpio.h> |
| 52 | #include <platform/timer.h> |
| 53 | #include <stdlib.h> |
| 54 | #include <ufs.h> |
Sundarajan Srinivasan | d598b12 | 2014-03-21 17:33:29 -0700 | [diff] [blame] | 55 | #include <boot_device.h> |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 56 | #include <qmp_phy.h> |
Joonwoo Park | 8b30997 | 2014-06-09 16:58:38 -0700 | [diff] [blame] | 57 | #include <qusb2_phy.h> |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 58 | |
Channagoud Kadabi | 4b93fd3 | 2014-06-04 17:28:03 -0700 | [diff] [blame] | 59 | #define CE_INSTANCE 3 |
| 60 | #define CE_EE 1 |
| 61 | #define CE_FIFO_SIZE 64 |
| 62 | #define CE_READ_PIPE 3 |
| 63 | #define CE_WRITE_PIPE 2 |
| 64 | #define CE_READ_PIPE_LOCK_GRP 0 |
| 65 | #define CE_WRITE_PIPE_LOCK_GRP 0 |
| 66 | #define CE_ARRAY_SIZE 20 |
| 67 | |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 68 | #define PMIC_ARB_CHANNEL_NUM 0 |
| 69 | #define PMIC_ARB_OWNER_ID 0 |
| 70 | |
| 71 | #define FASTBOOT_MODE 0x77665500 |
| 72 | |
| 73 | #define BOOT_DEVICE_MASK(val) ((val & 0x3E) >>1) |
| 74 | |
| 75 | static void set_sdc_power_ctrl(void); |
| 76 | static uint32_t mmc_pwrctl_base[] = |
| 77 | { MSM_SDC1_BASE, MSM_SDC2_BASE }; |
| 78 | |
| 79 | static uint32_t mmc_sdhci_base[] = |
| 80 | { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE }; |
| 81 | |
| 82 | static uint32_t mmc_sdc_pwrctl_irq[] = |
| 83 | { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ }; |
| 84 | |
| 85 | struct mmc_device *dev; |
| 86 | struct ufs_dev ufs_device; |
| 87 | |
| 88 | extern void ulpi_write(unsigned val, unsigned reg); |
| 89 | |
| 90 | void target_early_init(void) |
| 91 | { |
| 92 | #if WITH_DEBUG_UART |
| 93 | uart_dm_init(2, 0, BLSP1_UART1_BASE); |
| 94 | #endif |
| 95 | } |
| 96 | |
| 97 | /* Return 1 if vol_up pressed */ |
| 98 | static int target_volume_up() |
| 99 | { |
| 100 | uint8_t status = 0; |
| 101 | struct pm8x41_gpio gpio; |
| 102 | |
| 103 | /* Configure the GPIO */ |
| 104 | gpio.direction = PM_GPIO_DIR_IN; |
| 105 | gpio.function = 0; |
| 106 | gpio.pull = PM_GPIO_PULL_UP_30; |
| 107 | gpio.vin_sel = 2; |
| 108 | |
| 109 | pm8x41_gpio_config(3, &gpio); |
| 110 | |
| 111 | /* Wait for the pmic gpio config to take effect */ |
| 112 | thread_sleep(1); |
| 113 | |
| 114 | /* Get status of P_GPIO_5 */ |
| 115 | pm8x41_gpio_get(3, &status); |
| 116 | |
| 117 | return !status; /* active low */ |
| 118 | } |
| 119 | |
| 120 | /* Return 1 if vol_down pressed */ |
| 121 | uint32_t target_volume_down() |
| 122 | { |
| 123 | return pm8x41_resin_status(); |
| 124 | } |
| 125 | |
| 126 | static void target_keystatus() |
| 127 | { |
| 128 | keys_init(); |
| 129 | |
| 130 | if(target_volume_down()) |
| 131 | keys_post_event(KEY_VOLUMEDOWN, 1); |
| 132 | |
| 133 | if(target_volume_up()) |
| 134 | keys_post_event(KEY_VOLUMEUP, 1); |
| 135 | } |
| 136 | |
| 137 | void target_uninit(void) |
| 138 | { |
Sundarajan Srinivasan | d598b12 | 2014-03-21 17:33:29 -0700 | [diff] [blame] | 139 | if (platform_boot_dev_isemmc()) |
Channagoud Kadabi | d6a45ea | 2014-06-02 21:12:51 -0700 | [diff] [blame] | 140 | { |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 141 | mmc_put_card_to_sleep(dev); |
Channagoud Kadabi | d6a45ea | 2014-06-02 21:12:51 -0700 | [diff] [blame] | 142 | /* Disable HC mode before jumping to kernel */ |
| 143 | sdhci_mode_disable(&dev->host); |
| 144 | } |
Channagoud Kadabi | 4b93fd3 | 2014-06-04 17:28:03 -0700 | [diff] [blame] | 145 | |
| 146 | if (crypto_initialized()) |
| 147 | crypto_eng_cleanup(); |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | /* Do target specific usb initialization */ |
| 151 | void target_usb_init(void) |
| 152 | { |
| 153 | uint32_t val; |
| 154 | |
Sundarajan Srinivasan | 0ebf2fc | 2014-04-23 16:45:18 -0700 | [diff] [blame] | 155 | if(board_hardware_id() == HW_PLATFORM_DRAGON) |
| 156 | { |
| 157 | /* Select the QUSB2 PHY */ |
| 158 | writel(0x1, USB2_PHY_SEL); |
| 159 | |
Joonwoo Park | 8b30997 | 2014-06-09 16:58:38 -0700 | [diff] [blame] | 160 | qusb2_phy_reset(); |
Sundarajan Srinivasan | 0ebf2fc | 2014-04-23 16:45:18 -0700 | [diff] [blame] | 161 | } |
| 162 | |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 163 | /* Select and enable external configuration with USB PHY */ |
| 164 | ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET); |
| 165 | |
| 166 | /* Enable sess_vld */ |
| 167 | val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN; |
| 168 | writel(val, USB_GENCONFIG_2); |
| 169 | |
| 170 | /* Enable external vbus configuration in the LINK */ |
| 171 | val = readl(USB_USBCMD); |
| 172 | val |= SESS_VLD_CTRL; |
| 173 | writel(val, USB_USBCMD); |
| 174 | } |
| 175 | |
| 176 | void target_usb_stop(void) |
| 177 | { |
| 178 | /* Disable VBUS mimicing in the controller. */ |
| 179 | ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR); |
| 180 | } |
| 181 | |
| 182 | static void set_sdc_power_ctrl() |
| 183 | { |
| 184 | /* Drive strength configs for sdc pins */ |
| 185 | struct tlmm_cfgs sdc1_hdrv_cfg[] = |
| 186 | { |
Channagoud Kadabi | 9571715 | 2014-06-04 17:59:29 -0700 | [diff] [blame] | 187 | { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK }, |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 188 | { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK }, |
| 189 | { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK }, |
| 190 | }; |
| 191 | |
| 192 | /* Pull configs for sdc pins */ |
| 193 | struct tlmm_cfgs sdc1_pull_cfg[] = |
| 194 | { |
| 195 | { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK }, |
| 196 | { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK }, |
| 197 | { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK }, |
| 198 | }; |
| 199 | |
Channagoud Kadabi | 9571715 | 2014-06-04 17:59:29 -0700 | [diff] [blame] | 200 | struct tlmm_cfgs sdc1_rclk_cfg[] = |
| 201 | { |
| 202 | { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK }, |
| 203 | }; |
| 204 | |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 205 | /* Set the drive strength & pull control values */ |
| 206 | tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg)); |
| 207 | tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg)); |
Channagoud Kadabi | 9571715 | 2014-06-04 17:59:29 -0700 | [diff] [blame] | 208 | tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg)); |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | void target_sdc_init() |
| 212 | { |
Channagoud Kadabi | a66a6f2 | 2014-05-28 17:19:44 -0700 | [diff] [blame] | 213 | struct mmc_config_data config = {0}; |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 214 | |
| 215 | /* Set drive strength & pull ctrl values */ |
| 216 | set_sdc_power_ctrl(); |
| 217 | |
| 218 | config.bus_width = DATA_BUS_WIDTH_8BIT; |
| 219 | config.max_clk_rate = MMC_CLK_192MHZ; |
| 220 | |
| 221 | /* Try slot 1*/ |
| 222 | config.slot = 1; |
| 223 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 224 | config.pwrctl_base = mmc_pwrctl_base[config.slot - 1]; |
| 225 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 226 | |
| 227 | if (!(dev = mmc_init(&config))) |
| 228 | { |
| 229 | /* Try slot 2 */ |
| 230 | config.slot = 2; |
| 231 | config.max_clk_rate = MMC_CLK_200MHZ; |
| 232 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 233 | config.pwrctl_base = mmc_pwrctl_base[config.slot - 1]; |
| 234 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 235 | |
| 236 | if (!(dev = mmc_init(&config))) |
| 237 | { |
| 238 | dprintf(CRITICAL, "mmc init failed!"); |
| 239 | ASSERT(0); |
| 240 | } |
| 241 | } |
| 242 | } |
| 243 | |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 244 | void *target_mmc_device() |
| 245 | { |
Sundarajan Srinivasan | d598b12 | 2014-03-21 17:33:29 -0700 | [diff] [blame] | 246 | if (platform_boot_dev_isemmc()) |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 247 | return (void *) dev; |
| 248 | else |
| 249 | return (void *) &ufs_device; |
| 250 | } |
| 251 | |
| 252 | void target_init(void) |
| 253 | { |
| 254 | dprintf(INFO, "target_init()\n"); |
| 255 | |
| 256 | spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID); |
| 257 | |
| 258 | target_keystatus(); |
| 259 | |
Channagoud Kadabi | 4b93fd3 | 2014-06-04 17:28:03 -0700 | [diff] [blame] | 260 | |
| 261 | if (target_use_signed_kernel()) |
| 262 | target_crypto_init_params(); |
| 263 | |
Sundarajan Srinivasan | d598b12 | 2014-03-21 17:33:29 -0700 | [diff] [blame] | 264 | platform_read_boot_config(); |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 265 | |
Sundarajan Srinivasan | d598b12 | 2014-03-21 17:33:29 -0700 | [diff] [blame] | 266 | if (platform_boot_dev_isemmc()) |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 267 | { |
| 268 | target_sdc_init(); |
| 269 | } |
| 270 | else |
| 271 | { |
| 272 | ufs_device.base = UFS_BASE; |
| 273 | ufs_init(&ufs_device); |
| 274 | } |
| 275 | |
| 276 | /* Storage initialization is complete, read the partition table info */ |
| 277 | if (partition_read_table()) |
| 278 | { |
| 279 | dprintf(CRITICAL, "Error reading the partition table info\n"); |
| 280 | ASSERT(0); |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | unsigned board_machtype(void) |
| 285 | { |
| 286 | return LINUX_MACHTYPE_UNKNOWN; |
| 287 | } |
| 288 | |
| 289 | /* Detect the target type */ |
| 290 | void target_detect(struct board_data *board) |
| 291 | { |
| 292 | /* This is filled from board.c */ |
| 293 | } |
| 294 | |
| 295 | /* Detect the modem type */ |
| 296 | void target_baseband_detect(struct board_data *board) |
| 297 | { |
| 298 | uint32_t platform; |
| 299 | |
| 300 | platform = board->platform; |
| 301 | |
| 302 | switch(platform) { |
Channagoud Kadabi | 44ea30d | 2014-04-14 13:59:42 -0700 | [diff] [blame] | 303 | case MSM8994: |
Channagoud Kadabi | 0f3a4f7 | 2014-02-06 13:22:07 -0800 | [diff] [blame] | 304 | board->baseband = BASEBAND_MSM; |
| 305 | break; |
| 306 | default: |
| 307 | dprintf(CRITICAL, "Platform type: %u is not supported\n",platform); |
| 308 | ASSERT(0); |
| 309 | }; |
| 310 | } |
| 311 | unsigned target_baseband() |
| 312 | { |
| 313 | return board_baseband(); |
| 314 | } |
| 315 | |
| 316 | void target_serialno(unsigned char *buf) |
| 317 | { |
| 318 | unsigned int serialno; |
| 319 | if (target_is_emmc_boot()) { |
| 320 | serialno = mmc_get_psn(); |
| 321 | snprintf((char *)buf, 13, "%x", serialno); |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | unsigned check_reboot_mode(void) |
| 326 | { |
| 327 | uint32_t restart_reason = 0; |
| 328 | uint32_t restart_reason_addr; |
| 329 | |
| 330 | restart_reason_addr = RESTART_REASON_ADDR; |
| 331 | |
| 332 | /* Read reboot reason and scrub it */ |
| 333 | restart_reason = readl(restart_reason_addr); |
| 334 | writel(0x00, restart_reason_addr); |
| 335 | |
| 336 | return restart_reason; |
| 337 | } |
| 338 | |
| 339 | void reboot_device(unsigned reboot_reason) |
| 340 | { |
| 341 | uint8_t reset_type = 0; |
| 342 | |
| 343 | /* Write the reboot reason */ |
| 344 | writel(reboot_reason, RESTART_REASON_ADDR); |
| 345 | |
| 346 | if(reboot_reason == FASTBOOT_MODE) |
| 347 | reset_type = PON_PSHOLD_WARM_RESET; |
| 348 | else |
| 349 | reset_type = PON_PSHOLD_HARD_RESET; |
| 350 | |
| 351 | pm8x41_reset_configure(reset_type); |
| 352 | |
| 353 | /* Drop PS_HOLD for MSM */ |
| 354 | writel(0x00, MPM2_MPM_PS_HOLD); |
| 355 | |
| 356 | mdelay(5000); |
| 357 | |
| 358 | dprintf(CRITICAL, "Rebooting failed\n"); |
| 359 | } |
| 360 | |
| 361 | int emmc_recovery_init(void) |
| 362 | { |
| 363 | return _emmc_recovery_init(); |
| 364 | } |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 365 | |
| 366 | target_usb_iface_t* target_usb30_init() |
| 367 | { |
| 368 | target_usb_iface_t *t_usb_iface; |
| 369 | |
| 370 | t_usb_iface = calloc(1, sizeof(target_usb_iface_t)); |
| 371 | ASSERT(t_usb_iface); |
| 372 | |
| 373 | t_usb_iface->mux_config = target_usb_phy_mux_configure; |
| 374 | t_usb_iface->phy_init = usb30_qmp_phy_init; |
| 375 | t_usb_iface->phy_reset = usb30_qmp_phy_reset; |
| 376 | t_usb_iface->clock_init = clock_usb30_init; |
| 377 | t_usb_iface->vbus_override = 1; |
| 378 | |
| 379 | return t_usb_iface; |
| 380 | } |
| 381 | |
| 382 | /* identify the usb controller to be used for the target */ |
| 383 | const char * target_usb_controller() |
| 384 | { |
| 385 | return "dwc"; |
| 386 | } |
| 387 | |
| 388 | /* mux hs phy to route to dwc controller */ |
| 389 | static void phy_mux_configure_with_tcsr() |
| 390 | { |
| 391 | /* As per the hardware team, set the mux for snps controller */ |
| 392 | RMWREG32(TCSR_PHSS_USB2_PHY_SEL, 0x0, 0x1, 0x1); |
| 393 | } |
| 394 | |
| 395 | /* configure hs phy mux if using dwc controller */ |
| 396 | void target_usb_phy_mux_configure(void) |
| 397 | { |
| 398 | if(!strcmp(target_usb_controller(), "dwc")) |
| 399 | { |
| 400 | phy_mux_configure_with_tcsr(); |
| 401 | } |
| 402 | } |
Channagoud Kadabi | 3c2be1c | 2014-06-01 18:59:21 -0700 | [diff] [blame] | 403 | |
| 404 | uint32_t target_override_pll() |
| 405 | { |
| 406 | return 1; |
| 407 | } |
Channagoud Kadabi | 4b93fd3 | 2014-06-04 17:28:03 -0700 | [diff] [blame] | 408 | |
| 409 | /* Set up params for h/w CE. */ |
| 410 | void target_crypto_init_params() |
| 411 | { |
| 412 | struct crypto_init_params ce_params; |
| 413 | |
| 414 | /* Set up base addresses and instance. */ |
| 415 | ce_params.crypto_instance = CE_INSTANCE; |
| 416 | ce_params.crypto_base = MSM_CE3_BASE; |
| 417 | ce_params.bam_base = MSM_CE3_BAM_BASE; |
| 418 | |
| 419 | /* Set up BAM config. */ |
| 420 | ce_params.bam_ee = CE_EE; |
| 421 | ce_params.pipes.read_pipe = CE_READ_PIPE; |
| 422 | ce_params.pipes.write_pipe = CE_WRITE_PIPE; |
| 423 | ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP; |
| 424 | ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP; |
| 425 | |
| 426 | /* Assign buffer sizes. */ |
| 427 | ce_params.num_ce = CE_ARRAY_SIZE; |
| 428 | ce_params.read_fifo_size = CE_FIFO_SIZE; |
| 429 | ce_params.write_fifo_size = CE_FIFO_SIZE; |
| 430 | |
| 431 | /* BAM is initialized by TZ for this platform. |
| 432 | * Do not do it again as the initialization address space |
| 433 | * is locked. |
| 434 | */ |
| 435 | ce_params.do_bam_init = 0; |
| 436 | |
| 437 | crypto_init_params(&ce_params); |
| 438 | } |
| 439 | |
| 440 | crypto_engine_type board_ce_type(void) |
| 441 | { |
| 442 | return CRYPTO_ENGINE_TYPE_HW; |
| 443 | } |