Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008, Google Inc. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * * Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * * Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in |
| 12 | * the documentation and/or other materials provided with the |
| 13 | * distribution. |
| 14 | * * Neither the name of Google, Inc. nor the names of its contributors |
| 15 | * may be used to endorse or promote products derived from this |
| 16 | * software without specific prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 19 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 20 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 21 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 22 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 23 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 24 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 25 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 26 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 28 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 29 | * SUCH DAMAGE. |
| 30 | */ |
| 31 | |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 32 | #ifndef _PLATFORM_MSM7627A_IOMAP_H_ |
| 33 | #define _PLATFORM_MSM7627A_IOMAP_H_ |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 34 | |
| 35 | #define MSM_GPIO1_BASE 0xA9200000 |
| 36 | #define MSM_GPIO2_BASE 0xA9300000 |
| 37 | |
| 38 | #define MSM_UART1_BASE 0xA9A00000 |
| 39 | #define MSM_UART2_BASE 0xA9B00000 |
| 40 | #define MSM_UART3_BASE 0xA9C00000 |
| 41 | |
| 42 | #define MSM_VIC_BASE 0xC0000000 |
| 43 | #define MSM_GPT_BASE 0xC0100000 |
Amol Jadi | aeda4e6 | 2011-07-19 18:07:29 -0700 | [diff] [blame] | 44 | |
| 45 | #define GPT_REG(off) (MSM_GPT_BASE + (off)) |
| 46 | |
| 47 | #define GPT_MATCH_VAL GPT_REG(0x0000) |
| 48 | #define GPT_COUNT_VAL GPT_REG(0x0004) |
| 49 | #define GPT_ENABLE GPT_REG(0x0008) |
| 50 | #define GPT_CLEAR GPT_REG(0x000C) |
| 51 | #define DGT_MATCH_VAL GPT_REG(0x0010) |
| 52 | #define DGT_COUNT_VAL GPT_REG(0x0014) |
| 53 | #define DGT_ENABLE GPT_REG(0x0018) |
| 54 | #define DGT_CLEAR GPT_REG(0x001C) |
| 55 | #define SPSS_TIMER_STATUS GPT_REG(0x0034) |
| 56 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 57 | #define MSM_CSR_BASE 0xC0100000 |
| 58 | #define MSM_CLK_CTL_BASE 0xA8600000 |
| 59 | |
| 60 | #define MSM_SHARED_BASE 0x00100000 |
| 61 | |
| 62 | #define MSM_SDC1_BASE 0xA0400000 |
Aparna Mallavarapu | 5a83b2a | 2011-05-26 18:01:31 +0530 | [diff] [blame] | 63 | #define MSM_SDC3_BASE 0xA0600000 |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 64 | |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 65 | #define MIPI_DSI_BASE (0xA1100000) |
| 66 | #define DSI_PHY_SW_RESET (0xA1100128) |
| 67 | #define REG_DSI(off) (MIPI_DSI_BASE + (off)) |
| 68 | #define MDP_BASE (0xAA200000) |
| 69 | #define REG_MDP(off) (MDP_BASE + (off)) |
| 70 | #define DSIPHY_REGULATOR_BASE (0x2CC) |
| 71 | #define DSIPHY_TIMING_BASE (0x260) |
| 72 | #define DSIPHY_CTRL_BASE (0x290) |
| 73 | #define DSIPHY_PLL_BASE (0x200) |
| 74 | #define DSIPHY_STRENGTH_BASE (0x2A0) |
| 75 | |
| 76 | /* Range 0 - 4 */ |
| 77 | #define DSIPHY_REGULATOR_CTRL(x) REG_DSI(DSIPHY_REGULATOR_BASE + (x) * 4) |
| 78 | /* Range 0 - 11 */ |
| 79 | #define DSIPHY_TIMING_CTRL(x) REG_DSI(DSIPHY_TIMING_BASE + (x) * 4) |
| 80 | /* Range 0 - 3 */ |
| 81 | #define DSIPHY_CTRL(x) REG_DSI(DSIPHY_CTRL_BASE + (x) * 4) |
| 82 | /* Range 0 - 2 */ |
| 83 | #define DSIPHY_STRENGTH_CTRL(x) REG_DSI(DSIPHY_STRENGTH_BASE + (x) * 4) |
| 84 | /* Range 0 - 19 */ |
| 85 | #define DSIPHY_PLL_CTRL(x) REG_DSI(DSIPHY_PLL_BASE + (x) * 4) |
| 86 | |
| 87 | #define DSI_CMD_DMA_MEM_START_ADDR_PANEL (0x2E000000) |
| 88 | #define MDP_DMA_P_CONFIG (0xAA290000) |
| 89 | #define MDP_DMA_P_OUT_XY (0xAA290010) |
| 90 | #define MDP_DMA_P_SIZE (0xAA290004) |
| 91 | #define MDP_DMA_P_BUF_ADDR (0xAA290008) |
| 92 | #define MDP_DMA_P_BUF_Y_STRIDE (0xAA29000C) |
| 93 | |
| 94 | #define MDP_DSI_VIDEO_EN (0xAA2F0000) |
| 95 | #define MDP_DSI_VIDEO_HSYNC_CTL (0xAA2F0004) |
| 96 | #define MDP_DSI_VIDEO_VSYNC_PERIOD (0xAA2F0008) |
| 97 | #define MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH (0xAA2F000C) |
| 98 | #define MDP_DSI_VIDEO_DISPLAY_HCTL (0xAA2F0010) |
| 99 | #define MDP_DSI_VIDEO_DISPLAY_V_START (0xAA2F0014) |
| 100 | #define MDP_DSI_VIDEO_DISPLAY_V_END (0xAA2F0018) |
| 101 | #define MDP_DSI_VIDEO_BORDER_CLR (0xAA2F0028) |
| 102 | #define MDP_DSI_VIDEO_HSYNC_SKEW (0xAA2F0030) |
| 103 | #define MDP_DSI_VIDEO_CTL_POLARITY (0xAA2F0038) |
| 104 | #define MDP_DSI_VIDEO_TEST_CTL (0xAA2F0034) |
| 105 | |
| 106 | #define MDP_DMA_P_START REG_MDP(0x0000C) |
| 107 | #define MDP_DMA_S_START REG_MDP(0x00010) |
| 108 | #define MDP_DISP_INTF_SEL REG_MDP(0x00038) |
| 109 | #define MDP_MAX_RD_PENDING_CMD_CONFIG REG_MDP(0x0004C) |
| 110 | #define MDP_INTR_ENABLE REG_MDP(0x00020) |
| 111 | #define MDP_INTR_CLEAR REG_MDP(0x00028) |
| 112 | #define MDP_DSI_CMD_MODE_ID_MAP REG_MDP(0x000A0) |
| 113 | #define MDP_DSI_CMD_MODE_TRIGGER_EN REG_MDP(0x000A4) |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 114 | |
| 115 | #define MDP_TEST_MODE_CLK REG_MDP(0xF0000) |
| 116 | #define MDP_INTR_STATUS REG_MDP(0x00054) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 117 | #endif |