blob: 433421eb490c285753e42b48bfac408890d95e12 [file] [log] [blame]
Kuogee Hsiehdf961742013-12-18 14:13:45 -08001/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
Dhaval Patelf9986272013-10-18 19:06:05 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions
5 * are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in
10 * the documentation and/or other materials provided with the
11 * distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
19 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
20 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
23 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <debug.h>
31#include <smem.h>
32#include <err.h>
33#include <msm_panel.h>
34#include <mipi_dsi.h>
35#include <pm8x41.h>
36#include <pm8x41_wled.h>
37#include <board.h>
38#include <mdp5.h>
39#include <endian.h>
40#include <platform/gpio.h>
41#include <platform/clock.h>
42#include <platform/iomap.h>
43#include <target/display.h>
44#include "include/panel.h"
45#include "include/display_resource.h"
46
47#define HFPLL_LDO_ID 12
48
49#define GPIO_STATE_LOW 0
50#define GPIO_STATE_HIGH 2
51#define RESET_GPIO_SEQ_LEN 3
52
53static uint32_t dsi_pll_enable_seq(uint32_t ctl_base)
54{
55 uint32_t rc = 0;
56
57 mdss_dsi_uniphy_pll_sw_reset(ctl_base);
58
59 writel(0x01, ctl_base + 0x0220); /* GLB CFG */
60 mdelay(1);
61 writel(0x05, ctl_base + 0x0220); /* GLB CFG */
62 mdelay(1);
63 writel(0x07, ctl_base + 0x0220); /* GLB CFG */
64 mdelay(1);
65 writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
66 mdelay(1);
67
68 mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
69
70 while (!(readl(ctl_base + 0x02c0) & 0x01)) {
71 mdss_dsi_uniphy_pll_sw_reset(ctl_base);
72 writel(0x01, ctl_base + 0x0220); /* GLB CFG */
73 mdelay(1);
74 writel(0x05, ctl_base + 0x0220); /* GLB CFG */
75 mdelay(1);
76 writel(0x07, ctl_base + 0x0220); /* GLB CFG */
77 mdelay(1);
78 writel(0x05, ctl_base + 0x0220); /* GLB CFG */
79 mdelay(1);
80 writel(0x07, ctl_base + 0x0220); /* GLB CFG */
81 mdelay(1);
82 writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
83 mdelay(2);
84 mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
85 }
86 return rc;
87}
88
Kuogee Hsiehdf961742013-12-18 14:13:45 -080089int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
Dhaval Patelf9986272013-10-18 19:06:05 -070090{
91 struct pm8x41_gpio pwmgpio_param = {
92 .direction = PM_GPIO_DIR_OUT,
93 .function = PM_GPIO_FUNC_1,
94 .vin_sel = 2, /* VIN_2 */
95 .pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
96 .output_buffer = PM_GPIO_OUT_CMOS,
97 .out_strength = 0x03,
98 };
Kuogee Hsiehdf961742013-12-18 14:13:45 -080099
100 if (!bl) {
101 dprintf(CRITICAL, "backlight structure is not available\n");
102 return ERR_INVALID_ARGS;
103 }
104
105 if (bl->bl_interface_type != BL_PWM) {
106 dprintf(CRITICAL, "backlight type:%d not supported\n",
107 bl->bl_interface_type);
108 return ERR_NOT_SUPPORTED;
109 }
110
Dhaval Patelf9986272013-10-18 19:06:05 -0700111 if (enable) {
Dhaval Patel499b7d22014-01-07 21:57:30 -0800112 pm8x41_gpio_config(pwm_gpio.pin_id, &pwmgpio_param);
Dhaval Patelf9986272013-10-18 19:06:05 -0700113
114 /* lpg channel 2 */
Dhaval Patel499b7d22014-01-07 21:57:30 -0800115 pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
116 pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
117 pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
118 pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x44, 0xcc); /* LPG_VALUE_LSB */
119 pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x45, 0x00); /* LPG_VALUE_MSB */
120 pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
Dhaval Patelf9986272013-10-18 19:06:05 -0700121 } else {
Dhaval Patel499b7d22014-01-07 21:57:30 -0800122 pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0x0); /* LPG_ENABLE_CONTROL */
Dhaval Patelf9986272013-10-18 19:06:05 -0700123 }
124
125 return NO_ERROR;
126}
127
128int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
129{
130 struct mdss_dsi_pll_config *pll_data;
131 uint32_t dual_dsi = pinfo->mipi.dual_dsi;
132 dprintf(SPEW, "target_panel_clock\n");
133
134 pll_data = pinfo->mipi.dsi_pll_config;
135 if (enable) {
136 mdp_gdsc_ctrl(enable);
137 mmss_bus_clock_enable();
138 mdp_clock_enable();
139 mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
140 dsi_pll_enable_seq(MIPI_DSI0_BASE);
141 if (pinfo->mipi.dual_dsi &&
142 !(pinfo->mipi.broadcast)) {
143 mdss_dsi_auto_pll_config(MIPI_DSI1_BASE, pll_data);
144 dsi_pll_enable_seq(MIPI_DSI1_BASE);
145 }
146 mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
147 pll_data->pclk_m,
148 pll_data->pclk_n,
149 pll_data->pclk_d);
150 } else if(!target_cont_splash_screen()) {
151 /* Disable clocks if continuous splash off */
Dhaval Patelf14af122013-10-29 12:48:41 -0700152 mmss_dsi_clock_disable(dual_dsi);
Dhaval Patelf9986272013-10-18 19:06:05 -0700153 mdp_clock_disable();
154 mmss_bus_clock_disable();
155 mdp_gdsc_ctrl(enable);
156 }
157
158 return NO_ERROR;
159}
160
161/* Pull DISP_RST_N high to get panel out of reset */
162int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
163 struct msm_panel_info *pinfo)
164{
165 uint32_t i = 0;
166
167 if (enable) {
168 gpio_tlmm_config(reset_gpio.pin_id, 0,
169 reset_gpio.pin_direction, reset_gpio.pin_pull,
170 reset_gpio.pin_strength, reset_gpio.pin_state);
171
172 gpio_tlmm_config(enable_gpio.pin_id, 0,
173 enable_gpio.pin_direction, enable_gpio.pin_pull,
174 enable_gpio.pin_strength, enable_gpio.pin_state);
175
176 gpio_tlmm_config(bkl_gpio.pin_id, 0,
177 bkl_gpio.pin_direction, bkl_gpio.pin_pull,
178 bkl_gpio.pin_strength, bkl_gpio.pin_state);
179
180 gpio_set(enable_gpio.pin_id, 2);
181 gpio_set(bkl_gpio.pin_id, 2);
182 /* reset */
183 for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
184 if (resetseq->pin_state[i] == GPIO_STATE_LOW)
185 gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
186 else
187 gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
188 mdelay(resetseq->sleep[i]);
189 }
190 } else {
191 gpio_set(reset_gpio.pin_id, 0);
192 gpio_set(enable_gpio.pin_id, 0);
193 gpio_set(bkl_gpio.pin_id, 0);
194 }
195
196 return NO_ERROR;
197}
198
199int target_ldo_ctrl(uint8_t enable)
200{
201 uint32_t ldocounter = 0;
202 uint32_t pm8x41_ldo_base = 0x13F00;
203
204 while (ldocounter < TOTAL_LDO_DEFINED) {
205 struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
206 0x100 * ldo_entry_array[ldocounter].ldo_id),
207 ldo_entry_array[ldocounter].ldo_type);
208
209 dprintf(SPEW, "Setting %s\n",
210 ldo_entry_array[ldocounter].ldo_id);
211
212 /* Set voltage during power on */
213 if (enable) {
214 pm8x41_ldo_set_voltage(&ldo_entry,
215 ldo_entry_array[ldocounter].ldo_voltage);
216 pm8x41_ldo_control(&ldo_entry, enable);
217 } else if(ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) {
218 pm8x41_ldo_control(&ldo_entry, enable);
219 }
220 ldocounter++;
221 }
222
223 return NO_ERROR;
224}
225
Dhaval Patelab2de892013-10-25 10:40:58 -0700226int target_display_pre_on()
227{
228 writel(0x000000FA, MDP_QOS_REMAPPER_CLASS_0);
229 writel(0x00000055, MDP_QOS_REMAPPER_CLASS_1);
230 writel(0xC0000CCD, MDP_CLK_CTRL0);
231 writel(0xD0000CCC, MDP_CLK_CTRL1);
232 writel(0x00CCCCCC, MDP_CLK_CTRL2);
233 writel(0x000000CC, MDP_CLK_CTRL6);
234 writel(0x0CCCC0C0, MDP_CLK_CTRL3);
235 writel(0xCCCCC0C0, MDP_CLK_CTRL4);
236 writel(0xCCCCC0C0, MDP_CLK_CTRL5);
237 writel(0x00CCC000, MDP_CLK_CTRL7);
238
239 writel(0x00000001, VBIF_VBIF_DDR_FORCE_CLK_ON);
240 writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF0);
241 writel(0x08000808, VBIF_VBIF_IN_RD_LIM_CONF1);
242 writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF2);
243 writel(0x00000808, VBIF_VBIF_IN_RD_LIM_CONF3);
244 writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF0);
245 writel(0x00100000, VBIF_VBIF_IN_WR_LIM_CONF1);
246 writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF2);
247 writel(0x00000000, VBIF_VBIF_IN_WR_LIM_CONF3);
248 writel(0x00013fff, VBIF_VBIF_ABIT_SHORT);
249 writel(0x000000A4, VBIF_VBIF_ABIT_SHORT_CONF);
250 writel(0x00003FFF, VBIF_VBIF_GATE_OFF_WRREQ_EN);
251 writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
252
253 return NO_ERROR;
254}
255
Dhaval Patelf9986272013-10-18 19:06:05 -0700256void display_init(void)
257{
258 uint32_t ret = 0;
259 ret = gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR);
260 if (ret) {
261 msm_display_off();
262 }
263}
264
265void display_shutdown(void)
266{
267 gcdb_display_shutdown();
268}