Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 15 | * |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 27 | */ |
| 28 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 29 | #include <err.h> |
| 30 | #include <assert.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 31 | #include <debug.h> |
| 32 | #include <reg.h> |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 33 | #include <platform/timer.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 34 | #include <platform/iomap.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 35 | #include <mmc.h> |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 36 | #include <clock.h> |
| 37 | #include <platform/clock.h> |
Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 38 | #include <blsp_qup.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 39 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 40 | void hsusb_clock_init(void) |
| 41 | { |
| 42 | int ret; |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 43 | struct clk *iclk, *cclk; |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 44 | |
| 45 | ret = clk_get_set_enable("usb_iface_clk", 0, 1); |
| 46 | if(ret) |
| 47 | { |
| 48 | dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret); |
| 49 | ASSERT(0); |
| 50 | } |
| 51 | |
| 52 | ret = clk_get_set_enable("usb_core_clk", 75000000, 1); |
| 53 | if(ret) |
| 54 | { |
| 55 | dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret); |
| 56 | ASSERT(0); |
| 57 | } |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 58 | |
| 59 | mdelay(20); |
| 60 | |
| 61 | iclk = clk_get("usb_iface_clk"); |
| 62 | cclk = clk_get("usb_core_clk"); |
| 63 | |
| 64 | /* Disable USB all clock init */ |
| 65 | writel(0, USB_BOOT_CLOCK_CTL); |
| 66 | |
| 67 | clk_disable(iclk); |
| 68 | clk_disable(cclk); |
| 69 | |
| 70 | mdelay(20); |
| 71 | |
| 72 | /* Start the block reset for usb */ |
| 73 | writel(1, USB_HS_BCR); |
| 74 | |
| 75 | mdelay(20); |
| 76 | |
| 77 | /* Take usb block out of reset */ |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 78 | writel(0, USB_HS_BCR); |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 79 | |
| 80 | mdelay(20); |
| 81 | |
| 82 | ret = clk_enable(iclk); |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 83 | |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 84 | if(ret) |
| 85 | { |
| 86 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 87 | ASSERT(0); |
| 88 | } |
| 89 | |
| 90 | ret = clk_enable(cclk); |
| 91 | |
| 92 | if(ret) |
| 93 | { |
| 94 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 95 | ASSERT(0); |
| 96 | } |
| 97 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 98 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 99 | |
| 100 | void clock_init_mmc(uint32_t interface) |
| 101 | { |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 102 | char clk_name[64]; |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 103 | int ret; |
| 104 | |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 105 | snprintf(clk_name, 64, "sdc%u_iface_clk", interface); |
| 106 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 107 | /* enable interface clock */ |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 108 | ret = clk_get_set_enable(clk_name, 0, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 109 | if(ret) |
| 110 | { |
| 111 | dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret); |
| 112 | ASSERT(0); |
| 113 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 114 | } |
| 115 | |
| 116 | /* Configure MMC clock */ |
| 117 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 118 | { |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 119 | int ret; |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 120 | uint32_t reg; |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 121 | char clk_name[64]; |
| 122 | |
| 123 | snprintf(clk_name, 64, "sdc%u_core_clk", interface); |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 124 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 125 | if(freq == MMC_CLK_400KHZ) |
| 126 | { |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 127 | ret = clk_get_set_enable(clk_name, 400000, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 128 | } |
| 129 | else if(freq == MMC_CLK_50MHZ) |
| 130 | { |
Neeti Desai | ddc771b | 2012-08-28 18:17:04 -0700 | [diff] [blame] | 131 | ret = clk_get_set_enable(clk_name, 50000000, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 132 | } |
| 133 | else |
| 134 | { |
| 135 | dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq); |
| 136 | ASSERT(0); |
| 137 | } |
| 138 | |
| 139 | |
| 140 | if(ret) |
| 141 | { |
| 142 | dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret); |
| 143 | ASSERT(0); |
| 144 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 145 | |
| 146 | reg = 0; |
| 147 | reg |= MMC_BOOT_MCI_CLK_ENABLE; |
| 148 | reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 149 | reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK; |
| 150 | writel(reg, MMC_BOOT_MCI_CLK); |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 151 | |
| 152 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 153 | mmc_mclk_reg_wr_delay(); |
| 154 | |
| 155 | /* Wait 1 ms to provide the free running SD CLK to the card. */ |
| 156 | mdelay(1); |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 157 | } |
| 158 | |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 159 | /* Configure UART clock based on the UART block id*/ |
| 160 | void clock_config_uart_dm(uint8_t id) |
| 161 | { |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 162 | int ret; |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 163 | |
Neeti Desai | ac01127 | 2012-08-29 18:24:54 -0700 | [diff] [blame] | 164 | |
| 165 | ret = clk_get_set_enable("uart2_iface_clk", 0, 1); |
| 166 | if(ret) |
| 167 | { |
| 168 | dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret); |
| 169 | ASSERT(0); |
| 170 | } |
| 171 | |
| 172 | ret = clk_get_set_enable("uart2_core_clk", 7372800, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 173 | if(ret) |
| 174 | { |
| 175 | dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret); |
| 176 | ASSERT(0); |
| 177 | } |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 178 | } |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 179 | |
| 180 | /* Function to asynchronously reset CE. |
| 181 | * Function assumes that all the CE clocks are off. |
| 182 | */ |
| 183 | static void ce_async_reset(uint8_t instance) |
| 184 | { |
| 185 | if (instance == 1) |
| 186 | { |
| 187 | /* TODO: Add support for instance 1. */ |
| 188 | dprintf(CRITICAL, "CE instance not supported instance = %d", instance); |
| 189 | ASSERT(0); |
| 190 | } |
| 191 | else if (instance == 2) |
| 192 | { |
| 193 | /* Start the block reset for CE */ |
| 194 | writel(1, GCC_CE2_BCR); |
| 195 | |
| 196 | udelay(2); |
| 197 | |
| 198 | /* Take CE block out of reset */ |
| 199 | writel(0, GCC_CE2_BCR); |
| 200 | |
| 201 | udelay(2); |
| 202 | } |
| 203 | else |
| 204 | { |
| 205 | dprintf(CRITICAL, "CE instance not supported instance = %d", instance); |
| 206 | ASSERT(0); |
| 207 | } |
| 208 | } |
| 209 | |
| 210 | static void clock_ce_enable(uint8_t instance) |
| 211 | { |
| 212 | int ret; |
| 213 | char clk_name[64]; |
| 214 | |
| 215 | snprintf(clk_name, 64, "ce%u_src_clk", instance); |
| 216 | ret = clk_get_set_enable(clk_name, 100000000, 1); |
| 217 | if(ret) |
| 218 | { |
| 219 | dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret); |
| 220 | ASSERT(0); |
| 221 | } |
| 222 | |
| 223 | snprintf(clk_name, 64, "ce%u_core_clk", instance); |
| 224 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 225 | if(ret) |
| 226 | { |
| 227 | dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret); |
| 228 | ASSERT(0); |
| 229 | } |
| 230 | |
| 231 | snprintf(clk_name, 64, "ce%u_ahb_clk", instance); |
| 232 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 233 | if(ret) |
| 234 | { |
| 235 | dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret); |
| 236 | ASSERT(0); |
| 237 | } |
| 238 | |
| 239 | snprintf(clk_name, 64, "ce%u_axi_clk", instance); |
| 240 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 241 | if(ret) |
| 242 | { |
| 243 | dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret); |
| 244 | ASSERT(0); |
| 245 | } |
| 246 | |
| 247 | /* Wait for 48 * #pipes cycles. |
| 248 | * This is necessary as immediately after an access control reset (boot up) |
| 249 | * or a debug re-enable, the Crypto core sequentially clears its internal |
| 250 | * pipe key storage memory. If pipe key initialization writes are attempted |
| 251 | * during this time, they may be overwritten by the internal clearing logic. |
| 252 | */ |
| 253 | udelay(1); |
| 254 | } |
| 255 | |
| 256 | static void clock_ce_disable(uint8_t instance) |
| 257 | { |
| 258 | struct clk *ahb_clk; |
| 259 | struct clk *cclk; |
| 260 | struct clk *axi_clk; |
| 261 | struct clk *src_clk; |
| 262 | char clk_name[64]; |
| 263 | |
| 264 | snprintf(clk_name, 64, "ce%u_src_clk", instance); |
| 265 | src_clk = clk_get(clk_name); |
| 266 | |
| 267 | snprintf(clk_name, 64, "ce%u_ahb_clk", instance); |
| 268 | ahb_clk = clk_get(clk_name); |
| 269 | |
| 270 | snprintf(clk_name, 64, "ce%u_axi_clk", instance); |
| 271 | axi_clk = clk_get(clk_name); |
| 272 | |
| 273 | snprintf(clk_name, 64, "ce%u_core_clk", instance); |
| 274 | cclk = clk_get(clk_name); |
| 275 | |
| 276 | clk_disable(ahb_clk); |
| 277 | clk_disable(axi_clk); |
| 278 | clk_disable(cclk); |
| 279 | clk_disable(src_clk); |
| 280 | |
| 281 | /* Some delay for the clocks to stabalize. */ |
| 282 | udelay(1); |
| 283 | } |
| 284 | |
| 285 | void clock_config_ce(uint8_t instance) |
| 286 | { |
| 287 | /* Need to enable the clock before disabling since the clk_disable() |
| 288 | * has a check to default to nop when the clk_enable() is not called |
| 289 | * on that particular clock. |
| 290 | */ |
| 291 | clock_ce_enable(instance); |
| 292 | |
| 293 | clock_ce_disable(instance); |
| 294 | |
| 295 | ce_async_reset(instance); |
| 296 | |
| 297 | clock_ce_enable(instance); |
| 298 | } |
Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 299 | |
| 300 | void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id) |
| 301 | { |
| 302 | uint8_t ret = 0; |
| 303 | char clk_name[64]; |
| 304 | |
| 305 | struct clk *qup_clk; |
| 306 | |
| 307 | snprintf(clk_name, 64, "blsp%u_ahb_clk", blsp_id); |
| 308 | |
| 309 | ret = clk_get_set_enable(clk_name, 0 , 1); |
| 310 | |
| 311 | if (ret) { |
| 312 | dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name); |
| 313 | return; |
| 314 | } |
| 315 | |
| 316 | snprintf(clk_name, 64, "blsp%u_qup%u_i2c_apps_clk", blsp_id, |
| 317 | (qup_id + 1)); |
| 318 | |
| 319 | qup_clk = clk_get(clk_name); |
| 320 | |
| 321 | if (!qup_clk) { |
| 322 | dprintf(CRITICAL, "Failed to get %s\n", clk_name); |
| 323 | return; |
| 324 | } |
| 325 | |
| 326 | ret = clk_enable(qup_clk); |
| 327 | |
| 328 | if (ret) { |
| 329 | dprintf(CRITICAL, "Failed to enable %s\n", clk_name); |
| 330 | return; |
| 331 | } |
| 332 | } |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 333 | |
| 334 | void mdp_gdsc_ctrl(uint8_t enable) |
| 335 | { |
| 336 | uint32_t reg = 0; |
| 337 | reg = readl(MDP_GDSCR); |
| 338 | if (enable) { |
| 339 | if (reg & 0x1) |
| 340 | writel((reg & ~0x1), MDP_GDSCR); |
| 341 | |
| 342 | while(readl(MDP_GDSCR) & ((GDSC_POWER_ON_BIT) | (GDSC_POWER_ON_STATUS_BIT))); |
| 343 | } else |
| 344 | ASSERT(1); |
| 345 | } |
| 346 | |
| 347 | /* Configure MDP clock */ |
| 348 | void mdp_clock_init(void) |
| 349 | { |
| 350 | int ret; |
| 351 | |
| 352 | /* Set MDP clock to 200MHz */ |
| 353 | ret = clk_get_set_enable("mdp_ahb_clk", 0, 1); |
| 354 | if(ret) |
| 355 | { |
| 356 | dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret); |
| 357 | ASSERT(0); |
| 358 | } |
| 359 | |
| 360 | ret = clk_get_set_enable("mdss_mdp_clk_src", 75000000, 1); |
| 361 | if(ret) |
| 362 | { |
| 363 | dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret); |
| 364 | ASSERT(0); |
| 365 | } |
| 366 | |
| 367 | ret = clk_get_set_enable("mdss_mdp_clk", 0, 1); |
| 368 | if(ret) |
| 369 | { |
| 370 | dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret); |
| 371 | ASSERT(0); |
| 372 | } |
| 373 | |
| 374 | ret = clk_get_set_enable("mdss_mdp_lut_clk", 0, 1); |
| 375 | if(ret) |
| 376 | { |
| 377 | dprintf(CRITICAL, "failed to set lut_mdp clk ret = %d\n", ret); |
| 378 | ASSERT(0); |
| 379 | } |
| 380 | } |
| 381 | |
| 382 | /* Initialize all clocks needed by Display */ |
| 383 | void mmss_clock_init(void) |
| 384 | { |
| 385 | int ret; |
| 386 | |
| 387 | /* Configure Byte clock */ |
| 388 | writel(0x100, DSI_BYTE0_CFG_RCGR); |
| 389 | writel(0x1, DSI_BYTE0_CMD_RCGR); |
| 390 | writel(0x1, DSI_BYTE0_CBCR); |
| 391 | |
| 392 | /* Configure ESC clock */ |
| 393 | ret = clk_get_set_enable("mdss_esc0_clk", 0, 1); |
| 394 | if(ret) |
| 395 | { |
| 396 | dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret); |
| 397 | ASSERT(0); |
| 398 | } |
| 399 | |
| 400 | /* Configure MMSSNOC AXI clock */ |
| 401 | ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1); |
| 402 | if(ret) |
| 403 | { |
| 404 | dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret); |
| 405 | ASSERT(0); |
| 406 | } |
| 407 | |
| 408 | /* Configure MMSSNOC AXI clock */ |
| 409 | ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1); |
| 410 | if(ret) |
| 411 | { |
| 412 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 413 | ASSERT(0); |
| 414 | } |
| 415 | |
| 416 | /* Configure AXI clock */ |
| 417 | ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1); |
| 418 | if(ret) |
| 419 | { |
| 420 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 421 | ASSERT(0); |
| 422 | } |
| 423 | |
| 424 | /* Configure Pixel clock */ |
| 425 | writel(0x102, DSI_PIXEL0_CFG_RCGR); |
| 426 | writel(0x1, DSI_PIXEL0_CMD_RCGR); |
| 427 | writel(0x1, DSI_PIXEL0_CBCR); |
| 428 | } |