Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008, Google Inc. |
| 3 | * All rights reserved. |
Deepa Dinamani | 52aca8d | 2013-02-05 11:41:41 -0800 | [diff] [blame] | 4 | * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved. |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * * Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * * Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in |
| 12 | * the documentation and/or other materials provided with the |
| 13 | * distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 16 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 17 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 18 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 19 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 20 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 21 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 22 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 23 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 24 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 25 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 26 | * SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <qpic_nand.h> |
| 30 | #include <bam.h> |
| 31 | #include <dev/flash.h> |
| 32 | #include <lib/ptable.h> |
| 33 | #include <debug.h> |
| 34 | #include <string.h> |
| 35 | #include <malloc.h> |
| 36 | #include <sys/types.h> |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 37 | #include <platform.h> |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 38 | #include <platform/clock.h> |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 39 | |
| 40 | static uint32_t nand_base; |
| 41 | static struct ptable *flash_ptable; |
| 42 | static struct flash_info flash; |
| 43 | static unsigned char *flash_spare_bytes; |
| 44 | static uint32_t cfg0; |
| 45 | static uint32_t cfg1; |
| 46 | static uint32_t cfg0_raw; |
| 47 | static uint32_t cfg1_raw; |
| 48 | static uint32_t ecc_bch_cfg; |
| 49 | |
| 50 | struct cmd_element ce_array[100]; |
| 51 | |
| 52 | #define QPIC_BAM_DATA_FIFO_SIZE 64 |
| 53 | #define QPIC_BAM_CMD_FIFO_SIZE 64 |
| 54 | |
| 55 | static struct bam_desc cmd_desc_fifo[QPIC_BAM_CMD_FIFO_SIZE] __attribute__ ((aligned(BAM_DESC_SIZE))); |
| 56 | static struct bam_desc data_desc_fifo[QPIC_BAM_DATA_FIFO_SIZE] __attribute__ ((aligned(BAM_DESC_SIZE))); |
| 57 | |
| 58 | static struct bam_instance bam; |
| 59 | static uint8_t *bbtbl; |
| 60 | |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 61 | static uint8_t* rdwr_buf; |
| 62 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 63 | static struct flash_id supported_flash[] = { |
Deepa Dinamani | 649a94a | 2013-03-07 14:37:31 -0800 | [diff] [blame] | 64 | /* Flash ID ID Mask Density(MB) Wid Pgsz Blksz oobsz 8-bit ECCf */ |
| 65 | {0x1590AC2C, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 0}, |
| 66 | {0x2690AC2C, 0xFFFFFFFF, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1}, |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 67 | /* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 68 | }; |
| 69 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 70 | static void |
| 71 | qpic_nand_wait_for_cmd_exec(uint32_t num_desc) |
| 72 | { |
| 73 | /* Create a read/write event to notify the periperal of the added desc. */ |
| 74 | bam_sys_gen_event(&bam, CMD_PIPE_INDEX, num_desc); |
| 75 | |
| 76 | /* Wait for the descriptors to be processed */ |
| 77 | bam_wait_for_interrupt(&bam, CMD_PIPE_INDEX, P_PRCSD_DESC_EN_MASK); |
| 78 | |
| 79 | /* Read offset update for the circular FIFO */ |
| 80 | bam_read_offset_update(&bam, CMD_PIPE_INDEX); |
| 81 | } |
| 82 | |
| 83 | static void |
| 84 | qpic_nand_wait_for_data(uint32_t pipe_num) |
| 85 | { |
| 86 | /* Wait for the descriptors to be processed */ |
| 87 | bam_wait_for_interrupt(&bam, pipe_num, P_PRCSD_DESC_EN_MASK); |
| 88 | |
| 89 | /* Read offset update for the circular FIFO */ |
| 90 | bam_read_offset_update(&bam, pipe_num); |
| 91 | } |
| 92 | |
| 93 | static uint32_t |
| 94 | qpic_nand_read_reg(uint32_t reg_addr, |
| 95 | uint8_t flags, |
| 96 | struct cmd_element *cmd_list_ptr) |
| 97 | { |
| 98 | uint32_t val; |
| 99 | |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 100 | bam_add_cmd_element(cmd_list_ptr, reg_addr, (uint32_t)PA((addr_t)&val), CE_READ_TYPE); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 101 | |
| 102 | /* Enqueue the desc for the above command */ |
| 103 | bam_add_one_desc(&bam, |
| 104 | CMD_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 105 | (unsigned char*)PA((addr_t)cmd_list_ptr), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 106 | BAM_CE_SIZE, |
| 107 | BAM_DESC_CMD_FLAG| BAM_DESC_INT_FLAG | flags); |
| 108 | |
| 109 | qpic_nand_wait_for_cmd_exec(1); |
| 110 | |
| 111 | return val; |
| 112 | } |
| 113 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 114 | /* Assume the BAM is in a locked state. */ |
| 115 | void |
| 116 | qpic_nand_erased_status_reset(struct cmd_element *cmd_list_ptr) |
| 117 | { |
| 118 | uint32_t val = 0; |
| 119 | |
| 120 | /* Reset the Erased Codeword/Page detection controller. */ |
| 121 | val = NAND_ERASED_CW_DETECT_CFG_RESET_CTRL; |
| 122 | |
| 123 | bam_add_cmd_element(cmd_list_ptr, NAND_ERASED_CW_DETECT_CFG, val, CE_WRITE_TYPE); |
| 124 | |
| 125 | /* Enqueue the desc for the above command */ |
| 126 | bam_add_one_desc(&bam, |
| 127 | CMD_PIPE_INDEX, |
| 128 | (unsigned char*)cmd_list_ptr, |
| 129 | BAM_CE_SIZE, |
| 130 | BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG); |
| 131 | |
| 132 | qpic_nand_wait_for_cmd_exec(1); |
| 133 | |
| 134 | /* Enable the Erased Codeword/Page detection |
| 135 | * controller to check the data as it arrives. |
| 136 | * Also disable ECC reporting for an erased CW. |
| 137 | */ |
| 138 | val = NAND_ERASED_CW_DETECT_CFG_ACTIVATE_CTRL | NAND_ERASED_CW_DETECT_ERASED_CW_ECC_MASK; |
| 139 | |
| 140 | bam_add_cmd_element(cmd_list_ptr, NAND_ERASED_CW_DETECT_CFG, val, CE_WRITE_TYPE); |
| 141 | |
| 142 | /* Enqueue the desc for the above command */ |
| 143 | bam_add_one_desc(&bam, |
| 144 | CMD_PIPE_INDEX, |
| 145 | (unsigned char*)cmd_list_ptr, |
| 146 | BAM_CE_SIZE, |
| 147 | BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG); |
| 148 | |
| 149 | qpic_nand_wait_for_cmd_exec(1); |
| 150 | } |
| 151 | |
| 152 | static nand_result_t |
| 153 | qpic_nand_check_status(uint32_t status) |
| 154 | { |
| 155 | uint32_t erase_sts; |
| 156 | |
| 157 | /* Check for errors */ |
| 158 | if (status & NAND_FLASH_ERR) |
| 159 | { |
| 160 | /* Check if this is an ECC error on an erased page. */ |
| 161 | if (status & NAND_FLASH_OP_ERR) |
| 162 | { |
| 163 | erase_sts = qpic_nand_read_reg(NAND_ERASED_CW_DETECT_STATUS, 0, ce_array); |
| 164 | if ((erase_sts & (1 << NAND_ERASED_CW_DETECT_STATUS_PAGE_ALL_ERASED))) |
| 165 | { |
| 166 | /* Mask the OP ERROR. */ |
| 167 | status &= ~NAND_FLASH_OP_ERR; |
| 168 | qpic_nand_erased_status_reset(ce_array); |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | /* ECC error flagged on an erased page read. |
| 173 | * Ignore and return success. |
| 174 | */ |
| 175 | if (!(status & NAND_FLASH_ERR)) |
| 176 | return NANDC_RESULT_SUCCESS; |
| 177 | |
| 178 | dprintf(CRITICAL, "Nand Flash error. Status = %d\n", status); |
| 179 | |
| 180 | if (status & NAND_FLASH_TIMEOUT_ERR) |
| 181 | return NANDC_RESULT_TIMEOUT; |
| 182 | else |
| 183 | return NANDC_RESULT_FAILURE; |
| 184 | } |
| 185 | |
| 186 | return NANDC_RESULT_SUCCESS; |
| 187 | } |
| 188 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 189 | static uint32_t |
| 190 | qpic_nand_fetch_id(struct flash_info *flash) |
| 191 | { |
| 192 | struct cmd_element *cmd_list_ptr = ce_array; |
| 193 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 194 | int num_desc = 0; |
| 195 | uint32_t status; |
| 196 | uint32_t id; |
| 197 | uint32_t flash_cmd = NAND_CMD_FETCH_ID; |
| 198 | uint32_t exec_cmd = 1; |
| 199 | int nand_ret = NANDC_RESULT_SUCCESS; |
| 200 | |
| 201 | /* Issue the Fetch id command to the NANDc */ |
| 202 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)flash_cmd, CE_WRITE_TYPE); |
| 203 | cmd_list_ptr++; |
| 204 | |
| 205 | /* Execute the cmd */ |
| 206 | bam_add_cmd_element(cmd_list_ptr, NAND_EXEC_CMD, (uint32_t)exec_cmd, CE_WRITE_TYPE); |
| 207 | cmd_list_ptr++; |
| 208 | |
| 209 | /* Prepare the cmd desc for the above commands */ |
| 210 | bam_add_one_desc(&bam, |
| 211 | CMD_PIPE_INDEX, |
| 212 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 213 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 214 | BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG | |
| 215 | BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG); |
| 216 | |
| 217 | /* Keep track of the number of desc added. */ |
| 218 | num_desc++; |
| 219 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 220 | |
| 221 | cmd_list_ptr_start = ce_array; |
| 222 | cmd_list_ptr = ce_array; |
| 223 | |
| 224 | /* Read the status register */ |
| 225 | status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr); |
| 226 | |
| 227 | /* Check for errors */ |
| 228 | nand_ret = qpic_nand_check_status(status); |
| 229 | if (nand_ret) |
| 230 | { |
| 231 | dprintf( CRITICAL, "Read ID cmd status failed\n"); |
| 232 | goto qpic_nand_fetch_id_err; |
| 233 | } |
| 234 | |
| 235 | /* Read the id */ |
| 236 | id = qpic_nand_read_reg(NAND_READ_ID, BAM_DESC_UNLOCK_FLAG, cmd_list_ptr); |
| 237 | |
| 238 | flash->id = id; |
| 239 | flash->vendor = id & 0xff; |
| 240 | flash->device = (id >> 8) & 0xff; |
| 241 | flash->dev_cfg = (id >> 24) & 0xFF; |
| 242 | flash->widebus = 0; |
| 243 | flash->widebus &= (id >> 24) & 0xFF; |
| 244 | flash->widebus = flash->widebus? 1: 0; |
| 245 | |
| 246 | qpic_nand_fetch_id_err: |
| 247 | return nand_ret; |
| 248 | } |
| 249 | |
| 250 | static int |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 251 | qpic_bam_init(struct qpic_nand_init_config *config) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 252 | { |
| 253 | uint32_t bam_ret = NANDC_RESULT_SUCCESS; |
| 254 | |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 255 | bam.base = config->bam_base; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 256 | /* Set Read pipe params. */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 257 | bam.pipe[DATA_PRODUCER_PIPE_INDEX].pipe_num = config->pipes.read_pipe; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 258 | /* System consumer */ |
| 259 | bam.pipe[DATA_PRODUCER_PIPE_INDEX].trans_type = BAM2SYS; |
| 260 | bam.pipe[DATA_PRODUCER_PIPE_INDEX].fifo.size = QPIC_BAM_DATA_FIFO_SIZE; |
| 261 | bam.pipe[DATA_PRODUCER_PIPE_INDEX].fifo.head = data_desc_fifo; |
| 262 | |
| 263 | /* Set Write pipe params. */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 264 | bam.pipe[DATA_CONSUMER_PIPE_INDEX].pipe_num = config->pipes.write_pipe; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 265 | /* System producer */ |
| 266 | bam.pipe[DATA_CONSUMER_PIPE_INDEX].trans_type = SYS2BAM; |
| 267 | bam.pipe[DATA_CONSUMER_PIPE_INDEX].fifo.size = QPIC_BAM_DATA_FIFO_SIZE; |
| 268 | bam.pipe[DATA_CONSUMER_PIPE_INDEX].fifo.head = data_desc_fifo; |
| 269 | |
| 270 | /* Set Cmd pipe params. */ |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 271 | bam.pipe[CMD_PIPE_INDEX].pipe_num = config->pipes.cmd_pipe; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 272 | /* System consumer */ |
| 273 | bam.pipe[CMD_PIPE_INDEX].trans_type = BAM2SYS; |
| 274 | bam.pipe[CMD_PIPE_INDEX].fifo.size = QPIC_BAM_CMD_FIFO_SIZE; |
| 275 | bam.pipe[CMD_PIPE_INDEX].fifo.head = cmd_desc_fifo; |
| 276 | |
| 277 | /* Programs the threshold for BAM transfer |
| 278 | * When this threshold is reached, BAM signals the peripheral via the pipe_bytes_available |
| 279 | * interface. |
| 280 | * The peripheral is signalled with this notification in the following cases: |
| 281 | * a. It has accumulated all the descriptors. |
| 282 | * b. It has accumulated more than threshold bytes. |
| 283 | * c. It has reached EOT (End Of Transfer). |
| 284 | * Note: this value needs to be set by the h/w folks and is specific for each peripheral. |
| 285 | */ |
| 286 | bam.threshold = 32; |
| 287 | |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 288 | /* Set the EE. */ |
| 289 | bam.ee = config->ee; |
| 290 | |
| 291 | /* Set the max desc length for this BAM. */ |
| 292 | bam.max_desc_len = config->max_desc_len; |
| 293 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 294 | /* BAM Init. */ |
| 295 | bam_init(&bam); |
| 296 | |
| 297 | /* Initialize BAM QPIC read pipe */ |
| 298 | bam_sys_pipe_init(&bam, DATA_PRODUCER_PIPE_INDEX); |
| 299 | |
| 300 | /* Init read fifo */ |
| 301 | bam_ret = bam_pipe_fifo_init(&bam, bam.pipe[DATA_PRODUCER_PIPE_INDEX].pipe_num); |
| 302 | |
| 303 | if (bam_ret) |
| 304 | { |
| 305 | dprintf(CRITICAL, "QPIC:NANDc BAM Read FIFO init error\n"); |
| 306 | bam_ret = NANDC_RESULT_FAILURE; |
| 307 | goto qpic_nand_bam_init_error; |
| 308 | } |
| 309 | |
| 310 | /* Initialize BAM QPIC write pipe */ |
| 311 | bam_sys_pipe_init(&bam, DATA_CONSUMER_PIPE_INDEX); |
| 312 | |
| 313 | /* Init write fifo. Use the same fifo as read fifo. */ |
| 314 | bam_ret = bam_pipe_fifo_init(&bam, bam.pipe[DATA_CONSUMER_PIPE_INDEX].pipe_num); |
| 315 | |
| 316 | if (bam_ret) |
| 317 | { |
| 318 | dprintf(CRITICAL, "QPIC: NANDc: BAM Write FIFO init error\n"); |
| 319 | bam_ret = NANDC_RESULT_FAILURE; |
| 320 | goto qpic_nand_bam_init_error; |
| 321 | } |
| 322 | |
| 323 | /* Initialize BAM QPIC cmd pipe */ |
| 324 | bam_sys_pipe_init(&bam, CMD_PIPE_INDEX); |
| 325 | |
| 326 | /* Init cmd fifo */ |
| 327 | bam_ret = bam_pipe_fifo_init(&bam, bam.pipe[CMD_PIPE_INDEX].pipe_num); |
| 328 | |
| 329 | if (bam_ret) |
| 330 | { |
| 331 | dprintf(CRITICAL, "QPIC:NANDc BAM CMD FIFO init error\n"); |
| 332 | bam_ret = NANDC_RESULT_FAILURE; |
| 333 | goto qpic_nand_bam_init_error; |
| 334 | } |
| 335 | |
| 336 | qpic_nand_bam_init_error: |
| 337 | return bam_ret; |
| 338 | } |
| 339 | |
| 340 | /* Adds command elements for addr and cfg register writes. |
| 341 | * cfg: Defines the configuration for the flash cmd. |
| 342 | * start: Address where the command elements are added. |
| 343 | * |
| 344 | * Returns the address where the next cmd element can be added. |
| 345 | */ |
| 346 | static struct cmd_element* |
| 347 | qpic_nand_add_addr_n_cfg_ce(struct cfg_params *cfg, |
| 348 | struct cmd_element *start) |
| 349 | { |
| 350 | struct cmd_element *cmd_list_ptr = start; |
| 351 | |
| 352 | bam_add_cmd_element(cmd_list_ptr, NAND_ADDR0, (uint32_t)cfg->addr0, CE_WRITE_TYPE); |
| 353 | cmd_list_ptr++; |
| 354 | bam_add_cmd_element(cmd_list_ptr, NAND_ADDR1, (uint32_t)cfg->addr1, CE_WRITE_TYPE); |
| 355 | cmd_list_ptr++; |
| 356 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_CFG0, (uint32_t)cfg->cfg0, CE_WRITE_TYPE); |
| 357 | cmd_list_ptr++; |
| 358 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_CFG1, (uint32_t)cfg->cfg1, CE_WRITE_TYPE); |
| 359 | cmd_list_ptr++; |
| 360 | |
| 361 | return cmd_list_ptr; |
| 362 | } |
| 363 | |
| 364 | |
| 365 | static struct cmd_element* |
| 366 | qpic_nand_add_onfi_probe_ce(struct onfi_probe_params *params, |
| 367 | struct cmd_element *start) |
| 368 | { |
| 369 | struct cmd_element *cmd_list_ptr = start; |
| 370 | |
| 371 | cmd_list_ptr = qpic_nand_add_addr_n_cfg_ce(¶ms->cfg, cmd_list_ptr); |
| 372 | |
| 373 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV_CMD1, (uint32_t)params->dev_cmd1, CE_WRITE_TYPE); |
| 374 | cmd_list_ptr++; |
| 375 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV_CMD_VLD, (uint32_t)params->vld, CE_WRITE_TYPE); |
| 376 | cmd_list_ptr++; |
| 377 | bam_add_cmd_element(cmd_list_ptr, NAND_READ_LOCATION_n(0), (uint32_t)params->cfg.addr_loc_0, CE_WRITE_TYPE); |
| 378 | cmd_list_ptr++; |
| 379 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)params->cfg.cmd, CE_WRITE_TYPE); |
| 380 | cmd_list_ptr++; |
| 381 | bam_add_cmd_element(cmd_list_ptr, NAND_EXEC_CMD, (uint32_t)params->cfg.exec, CE_WRITE_TYPE); |
| 382 | cmd_list_ptr++; |
| 383 | |
| 384 | return cmd_list_ptr; |
| 385 | } |
| 386 | |
| 387 | static int |
| 388 | onfi_probe_cmd_exec(struct onfi_probe_params *params, |
| 389 | unsigned char* data_ptr, |
| 390 | int data_len) |
| 391 | { |
| 392 | struct cmd_element *cmd_list_ptr = ce_array; |
| 393 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 394 | int num_desc = 0; |
| 395 | uint32_t status = 0; |
| 396 | int nand_ret = NANDC_RESULT_SUCCESS; |
| 397 | uint8_t desc_flags = BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG |
| 398 | | BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG; |
| 399 | |
| 400 | params->cfg.addr_loc_0 = 0; |
| 401 | params->cfg.addr_loc_0 |= NAND_RD_LOC_LAST_BIT(1); |
| 402 | params->cfg.addr_loc_0 |= NAND_RD_LOC_OFFSET(0); |
| 403 | params->cfg.addr_loc_0 |= NAND_RD_LOC_SIZE(data_len); |
| 404 | |
| 405 | cmd_list_ptr = qpic_nand_add_onfi_probe_ce(params, cmd_list_ptr); |
| 406 | |
| 407 | /* Enqueue the desc for the above commands */ |
| 408 | bam_add_one_desc(&bam, |
| 409 | CMD_PIPE_INDEX, |
| 410 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 411 | PA((addr_t)(uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 412 | desc_flags); |
| 413 | |
| 414 | cmd_list_ptr_start = cmd_list_ptr; |
| 415 | num_desc++; |
| 416 | |
| 417 | /* Add Data desc */ |
| 418 | bam_add_desc(&bam, |
| 419 | DATA_PRODUCER_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 420 | (unsigned char *)PA((addr_t)data_ptr), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 421 | data_len, |
| 422 | BAM_DESC_INT_FLAG); |
| 423 | |
| 424 | /* Wait for the commands to be executed */ |
| 425 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 426 | |
| 427 | /* Read buffer status and check for errors. */ |
| 428 | status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr++); |
| 429 | |
| 430 | if (qpic_nand_check_status(status)) |
| 431 | { |
| 432 | nand_ret = NANDC_RESULT_FAILURE; |
| 433 | goto onfi_probe_exec_err; |
| 434 | } |
| 435 | |
| 436 | /* Wait for data to be available */ |
| 437 | qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX); |
| 438 | |
| 439 | /* Check for errors */ |
| 440 | nand_ret = qpic_nand_check_status(status); |
| 441 | |
| 442 | onfi_probe_exec_err: |
| 443 | return nand_ret; |
| 444 | } |
| 445 | |
| 446 | /* TODO: check why both vld and cmd need to be written. */ |
| 447 | void |
| 448 | qpic_nand_onfi_probe_cleanup(uint32_t vld, uint32_t dev_cmd1) |
| 449 | { |
| 450 | struct cmd_element *cmd_list_ptr = ce_array; |
| 451 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 452 | |
| 453 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV_CMD1, dev_cmd1, CE_WRITE_TYPE); |
| 454 | cmd_list_ptr++; |
| 455 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV_CMD_VLD, vld, CE_WRITE_TYPE); |
| 456 | cmd_list_ptr++; |
| 457 | |
| 458 | /* Enqueue the desc for the above commands */ |
| 459 | bam_add_one_desc(&bam, |
| 460 | CMD_PIPE_INDEX, |
| 461 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 462 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 463 | BAM_DESC_UNLOCK_FLAG | BAM_DESC_CMD_FLAG| BAM_DESC_INT_FLAG); |
| 464 | |
| 465 | qpic_nand_wait_for_cmd_exec(1); |
| 466 | } |
| 467 | |
| 468 | static int |
| 469 | qpic_nand_onfi_save_params(struct onfi_param_page *param_page, struct flash_info *flash) |
| 470 | { |
| 471 | int onfi_ret = NANDC_RESULT_SUCCESS; |
| 472 | uint32_t ecc_bits; |
| 473 | |
| 474 | onfi_ret = qpic_nand_fetch_id(flash); |
| 475 | |
| 476 | if (onfi_ret) |
| 477 | { |
| 478 | dprintf(CRITICAL, "Fetch ID cmd failed\n"); |
| 479 | goto onfi_save_params_err; |
| 480 | } |
| 481 | |
| 482 | flash->page_size = param_page->data_per_pg; |
| 483 | flash->block_size = param_page->pgs_per_blk * flash->page_size; |
| 484 | flash->num_blocks = param_page->blks_per_LUN; |
| 485 | flash->widebus = param_page->feature_supported & 0x1; |
| 486 | flash->density = param_page->blks_per_LUN * flash->blksize; |
| 487 | flash->spare_size = param_page->spare_per_pg; |
| 488 | ecc_bits = param_page->num_bits_ecc_correctability; |
| 489 | flash->num_pages_per_blk = param_page->pgs_per_blk; |
| 490 | flash->num_pages_per_blk_mask = param_page->pgs_per_blk - 1; |
| 491 | |
| 492 | if (ecc_bits >= 8) |
| 493 | flash->ecc_width = NAND_WITH_8_BIT_ECC; |
| 494 | else |
| 495 | flash->ecc_width = NAND_WITH_4_BIT_ECC; |
| 496 | |
| 497 | onfi_save_params_err: |
| 498 | return onfi_ret; |
| 499 | } |
| 500 | |
| 501 | static void |
| 502 | qpic_nand_save_config(struct flash_info *flash) |
| 503 | { |
| 504 | |
| 505 | /* Save Configurations */ |
| 506 | flash->cws_per_page = flash->page_size >> NAND_CW_DIV_RIGHT_SHIFT; |
| 507 | |
Deepa Dinamani | 16663a6 | 2013-02-07 16:25:59 -0800 | [diff] [blame] | 508 | /* Verify that we have enough buffer to handle all the cws in a page. */ |
| 509 | ASSERT(flash->cws_per_page <= QPIC_NAND_MAX_CWS_IN_PAGE); |
| 510 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 511 | /* Codeword Size = UD_SIZE_BYTES + ECC_PARITY_SIZE_BYTES |
| 512 | * + SPARE_SIZE_BYTES + Bad Block size |
| 513 | */ |
| 514 | if (flash->ecc_width & NAND_WITH_8_BIT_ECC) |
| 515 | { |
| 516 | flash->cw_size = NAND_CW_SIZE_8_BIT_ECC; |
| 517 | ecc_bch_cfg |= (1 << NAND_DEV0_ECC_MODE_SHIFT); /* Use 8-bit ecc */ |
| 518 | |
| 519 | if (flash->widebus) |
| 520 | { |
| 521 | cfg0 |= (0 << NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT); /* spare size bytes in each CW */ |
| 522 | ecc_bch_cfg |= (14 << NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT); /* parity bytes in each CW */ |
| 523 | } |
| 524 | else |
| 525 | { |
| 526 | cfg0 |= (2 << NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT); /* spare size bytes in each CW */ |
| 527 | ecc_bch_cfg |= (13 << NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT); /* parity bytes in each CW */ |
| 528 | } |
| 529 | } |
| 530 | else |
| 531 | { |
| 532 | flash->cw_size = NAND_CW_SIZE_4_BIT_ECC; |
| 533 | |
| 534 | if (flash->widebus) |
| 535 | { |
| 536 | cfg0 |= (2 << NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT); /* spare size bytes in each CW */ |
| 537 | ecc_bch_cfg |= (8 << NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT); /* parity bytes in each CW */ |
| 538 | } |
| 539 | else |
| 540 | { |
| 541 | cfg0 |= (4 << NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT); /* spare size bytes in each CW */ |
| 542 | ecc_bch_cfg |= (7 << NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT); /* parity bytes in each CW */ |
| 543 | } |
| 544 | } |
| 545 | |
| 546 | /* BAD_BLOCK_BYTE_NUM = Page Size - |
| 547 | * (CW_PER_PAGE * Codeword Size) + 1 |
| 548 | * Note: Set CW_PER_PAGE to 1 less than the actual number. |
| 549 | */ |
| 550 | flash->bad_blk_loc = flash->page_size - flash->cw_size * (flash->cws_per_page - 1) + 1; |
| 551 | |
| 552 | cfg0 |= ((flash->cws_per_page - 1) << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT) /* 4/8 cw/pg for 2/4k */ |
| 553 | |(DATA_BYTES_IN_IMG_PER_CW << NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT) /* 516 user data bytes */ |
| 554 | |(5 << NAND_DEV0_CFG0_ADDR_CYCLE_SHIFT) /* 5 address cycles */ |
| 555 | |(0 << NAND_DEV0_CFG0_DIS_STS_AFTER_WR_SHIFT);/* Send read status cmd after each write. */ |
| 556 | |
| 557 | cfg1 |= (7 << NAND_DEV0_CFG1_RECOVERY_CYCLES_SHIFT) /* 8 recovery cycles */ |
| 558 | |(0 << NAND_DEV0_CFG1_CS_ACTIVE_BSY_SHIFT) /* Allow CS deassertion */ |
| 559 | |(flash->bad_blk_loc << NAND_DEV0_CFG1_BAD_BLK_BYTE_NUM_SHIFT)/* Bad block marker location */ |
| 560 | |(0 << NAND_DEV0_CFG1_BAD_BLK_IN_SPARE_SHIFT) /* Bad block in user data area */ |
| 561 | |(2 << NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT) /* 8 cycle tWB/tRB */ |
| 562 | |(flash->widebus << NAND_DEV0_CFG1_WIDE_BUS_SHIFT); /* preserve wide flash flag */ |
| 563 | |
| 564 | cfg0_raw = ((flash->cws_per_page- 1) << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT) |
| 565 | |(5 << NAND_DEV0_CFG0_ADDR_CYCLE_SHIFT) |
| 566 | |(516 << NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT) //figure out the size of cw |
| 567 | | (1 << NAND_DEV0_CFG0_DIS_STS_AFTER_WR_SHIFT); |
| 568 | |
| 569 | cfg1_raw = (7 << NAND_DEV0_CFG1_RECOVERY_CYCLES_SHIFT) |
| 570 | | (0 << NAND_DEV0_CFG1_CS_ACTIVE_BSY_SHIFT) |
| 571 | | (17 << NAND_DEV0_CFG1_BAD_BLK_BYTE_NUM_SHIFT) |
| 572 | | (1 << NAND_DEV0_CFG1_BAD_BLK_IN_SPARE_SHIFT) |
| 573 | | (2 << NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT) |
| 574 | | (flash->widebus << NAND_DEV0_CFG1_WIDE_BUS_SHIFT) |
| 575 | |1 ; /* to disable reed solomon ecc..this feild is now read only. */ |
| 576 | |
| 577 | ecc_bch_cfg |= (0 << NAND_DEV0_ECC_DISABLE_SHIFT) /* Enable ECC */ |
| 578 | | (0 << NAND_DEV0_ECC_SW_RESET_SHIFT) /* Put ECC core in op mode */ |
| 579 | | (DATA_BYTES_IN_IMG_PER_CW << NAND_DEV0_ECC_NUM_DATA_BYTES) |
| 580 | | (1 << NAND_DEV0_ECC_FORCE_CLK_OPEN_SHIFT); /* Enable all clocks */ |
| 581 | } |
| 582 | |
| 583 | /* Onfi probe should issue the following commands to the flash device: |
| 584 | * 1. Read ID - with addr ONFI_READ_ID_ADDR. |
| 585 | * This returns the ONFI ASCII string indicating support for ONFI. |
| 586 | * 2. Read Prameter Page - with addr ONFI_READ_PARAM_PAGE_ADDR. |
| 587 | * This returns the params for the device. |
| 588 | * Each command inturn issues commands- ADDR0, ADDR1, chip_select, |
| 589 | * cfg0, cfg1, cmd_vld, dev_cmd1, read_loc0, flash, exec. |
| 590 | */ |
| 591 | static int |
| 592 | qpic_nand_onfi_probe(struct flash_info *flash) |
| 593 | { |
| 594 | struct onfi_probe_params params; |
| 595 | uint32_t vld; |
| 596 | uint32_t dev_cmd1; |
| 597 | unsigned char *buffer; |
| 598 | unsigned char onfi_str[4]; |
| 599 | uint32_t *id; |
| 600 | struct onfi_param_page *param_page; |
| 601 | int onfi_ret = NANDC_RESULT_SUCCESS; |
| 602 | |
| 603 | /* Allocate memory required to read the onfi param page */ |
| 604 | buffer = (unsigned char*) malloc(ONFI_READ_PARAM_PAGE_BUFFER_SIZE); |
| 605 | |
| 606 | /* Read the vld and dev_cmd1 registers before modifying */ |
| 607 | vld = qpic_nand_read_reg(NAND_DEV_CMD_VLD, 0, ce_array); |
| 608 | dev_cmd1 = qpic_nand_read_reg(NAND_DEV_CMD1, 0, ce_array); |
| 609 | |
| 610 | /* Initialize flash cmd */ |
| 611 | params.cfg.cmd = NAND_CMD_PAGE_READ; |
| 612 | params.cfg.exec = 1; |
| 613 | |
| 614 | /* Execute Read ID cmd */ |
| 615 | |
| 616 | /* Initialize the config */ |
| 617 | params.cfg.cfg0 = NAND_CFG0_RAW_ONFI_ID; |
| 618 | params.cfg.cfg1 = NAND_CFG1_RAW_ONFI_ID; |
| 619 | |
| 620 | /* Initialize the cmd and vld */ |
| 621 | params.dev_cmd1 = (dev_cmd1 & 0xFFFFFF00) | ONFI_READ_ID_CMD; |
| 622 | params.vld = vld & 0xFFFFFFFE; |
| 623 | |
| 624 | /* Initialize the address |
| 625 | * addr1 is not used bcos of the cfg. |
| 626 | */ |
| 627 | params.cfg.addr0 = ONFI_READ_ID_ADDR; |
| 628 | params.cfg.addr1 = 0; |
| 629 | |
| 630 | /* Lock the pipe and execute the cmd. */ |
| 631 | onfi_ret = onfi_probe_cmd_exec(¶ms, onfi_str, ONFI_READ_ID_BUFFER_SIZE); |
| 632 | if (onfi_ret) |
| 633 | { |
| 634 | dprintf(CRITICAL, "ONFI Read id cmd failed\n"); |
| 635 | goto qpic_nand_onfi_probe_err; |
| 636 | } |
| 637 | |
| 638 | /* Write back vld and cmd and unlock the pipe. */ |
| 639 | qpic_nand_onfi_probe_cleanup(vld, dev_cmd1); |
| 640 | |
| 641 | /* Check for onfi string */ |
| 642 | id = (uint32_t*)onfi_str; |
| 643 | if (*id != ONFI_SIGNATURE) |
| 644 | { |
| 645 | dprintf(CRITICAL, "Not an ONFI device\n"); |
| 646 | /* Not an onfi device. Return error. */ |
| 647 | onfi_ret = NANDC_RESULT_DEV_NOT_SUPPORTED; |
| 648 | goto qpic_nand_onfi_probe_err; |
| 649 | } |
| 650 | |
| 651 | dprintf(INFO, "ONFI device found\n"); |
| 652 | /* Now read the param page */ |
| 653 | /* Initialize the config */ |
| 654 | params.cfg.cfg0 = NAND_CFG0_RAW_ONFI_PARAM_PAGE; |
| 655 | params.cfg.cfg1 = NAND_CFG1_RAW_ONFI_PARAM_PAGE; |
| 656 | |
| 657 | /* Initialize the cmd and vld */ |
| 658 | params.dev_cmd1 = (dev_cmd1 & 0xFFFFFF00) | ONFI_READ_PARAM_PAGE_CMD; |
| 659 | params.vld = vld & 0xFFFFFFFE; |
| 660 | |
| 661 | /* Initialize the address |
| 662 | * addr1 is not used bcos of the cfg. |
| 663 | */ |
| 664 | params.cfg.addr0 = ONFI_READ_PARAM_PAGE_ADDR; |
| 665 | params.cfg.addr1 = 0; |
| 666 | |
| 667 | /* Lock the pipe and execute the cmd. */ |
| 668 | onfi_ret = onfi_probe_cmd_exec(¶ms, buffer, ONFI_READ_PARAM_PAGE_BUFFER_SIZE); |
| 669 | if (onfi_ret) |
| 670 | { |
| 671 | dprintf(CRITICAL, "ONFI Read param page failed\n"); |
| 672 | goto qpic_nand_onfi_probe_err; |
| 673 | } |
| 674 | |
| 675 | /* Write back vld and cmd and unlock the pipe. */ |
| 676 | qpic_nand_onfi_probe_cleanup(vld, dev_cmd1); |
| 677 | |
| 678 | /* Verify the integrity of the returned page */ |
| 679 | param_page = (struct onfi_param_page*)buffer; |
| 680 | |
| 681 | /* TODO: Add CRC check to validate the param page. */ |
| 682 | |
| 683 | /* Save the parameter values */ |
| 684 | onfi_ret = qpic_nand_onfi_save_params(param_page, flash); |
| 685 | |
| 686 | qpic_nand_onfi_probe_err: |
| 687 | if (onfi_ret) |
| 688 | dprintf(CRITICAL, "ONFI probe failed\n"); |
| 689 | |
| 690 | free(buffer); |
| 691 | |
| 692 | return onfi_ret; |
| 693 | } |
| 694 | |
| 695 | /* Enquues a desc for a flash cmd with NWD flag set: |
| 696 | * cfg: Defines the configuration for the flash cmd. |
| 697 | * start: Address where the command elements are added. |
| 698 | * |
| 699 | * Returns the address where the next cmd element can be added. |
| 700 | */ |
| 701 | struct cmd_element* |
| 702 | qpic_nand_add_cmd_ce(struct cfg_params *cfg, |
| 703 | struct cmd_element *start) |
| 704 | { |
| 705 | struct cmd_element *cmd_list_ptr; |
| 706 | |
| 707 | cmd_list_ptr = qpic_nand_add_addr_n_cfg_ce(cfg, start); |
| 708 | |
| 709 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)cfg->cmd, CE_WRITE_TYPE); |
| 710 | cmd_list_ptr++; |
| 711 | |
| 712 | bam_add_cmd_element(cmd_list_ptr, NAND_EXEC_CMD, (uint32_t)cfg->exec, CE_WRITE_TYPE); |
| 713 | cmd_list_ptr++; |
| 714 | |
| 715 | return cmd_list_ptr; |
| 716 | } |
| 717 | |
| 718 | /* Reads nand_flash_status and resets nand_flash_status and nand_read_status */ |
| 719 | struct cmd_element* |
| 720 | qpic_nand_add_read_n_reset_status_ce(struct cmd_element *start, |
| 721 | uint32_t *flash_status_read, |
| 722 | uint32_t read_status) |
| 723 | { |
| 724 | struct cmd_element *cmd_list_ptr = start; |
| 725 | uint32_t flash_status_reset; |
| 726 | uint32_t read_status_reset; |
| 727 | |
| 728 | /* Read and reset the status registers. */ |
| 729 | flash_status_reset = NAND_FLASH_STATUS_RESET; |
| 730 | read_status_reset = NAND_READ_STATUS_RESET; |
| 731 | |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 732 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)PA((addr_t)flash_status_read), CE_READ_TYPE); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 733 | cmd_list_ptr++; |
| 734 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)flash_status_reset, CE_WRITE_TYPE); |
| 735 | cmd_list_ptr++; |
| 736 | |
| 737 | if (read_status) |
| 738 | { |
| 739 | bam_add_cmd_element(cmd_list_ptr, NAND_READ_STATUS, (uint32_t)read_status_reset, CE_WRITE_TYPE); |
| 740 | cmd_list_ptr++; |
| 741 | } |
| 742 | |
| 743 | return cmd_list_ptr; |
| 744 | } |
| 745 | |
| 746 | struct cmd_element* |
| 747 | qpic_nand_add_isbad_cmd_ce(struct cfg_params *cfg, |
| 748 | struct cmd_element *start) |
| 749 | { |
| 750 | struct cmd_element *cmd_list_ptr = start; |
| 751 | |
| 752 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_ECC_CFG, (uint32_t)cfg->ecc_cfg, CE_WRITE_TYPE); |
| 753 | cmd_list_ptr++; |
| 754 | |
| 755 | bam_add_cmd_element(cmd_list_ptr, NAND_READ_LOCATION_n(0), (uint32_t)cfg->addr_loc_0, CE_WRITE_TYPE); |
| 756 | cmd_list_ptr++; |
| 757 | |
| 758 | cmd_list_ptr = qpic_nand_add_cmd_ce(cfg, cmd_list_ptr); |
| 759 | |
| 760 | return cmd_list_ptr; |
| 761 | } |
| 762 | |
| 763 | static int |
| 764 | qpic_nand_block_isbad_exec(struct cfg_params *params, |
| 765 | uint8_t *bad_block) |
| 766 | { |
| 767 | |
| 768 | struct cmd_element *cmd_list_ptr = ce_array; |
| 769 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 770 | uint8_t desc_flags = BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG |
| 771 | | BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG; |
| 772 | int num_desc = 0; |
| 773 | uint32_t status = 0; |
| 774 | int nand_ret = NANDC_RESULT_SUCCESS; |
| 775 | |
| 776 | cmd_list_ptr = qpic_nand_add_isbad_cmd_ce(params, cmd_list_ptr); |
| 777 | |
| 778 | /* Enqueue the desc for the above commands */ |
| 779 | bam_add_one_desc(&bam, |
| 780 | CMD_PIPE_INDEX, |
| 781 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 782 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 783 | desc_flags); |
| 784 | |
| 785 | num_desc++; |
| 786 | |
| 787 | /* Add Data desc */ |
| 788 | bam_add_desc(&bam, |
| 789 | DATA_PRODUCER_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 790 | (unsigned char *)PA((addr_t)bad_block), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 791 | 4, |
| 792 | BAM_DESC_INT_FLAG); |
| 793 | |
| 794 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 795 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 796 | status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr); |
| 797 | |
| 798 | nand_ret = qpic_nand_check_status(status); |
| 799 | |
| 800 | /* Dummy read to unlock pipe. */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 801 | status = qpic_nand_read_reg(NAND_FLASH_STATUS, BAM_DESC_UNLOCK_FLAG, cmd_list_ptr); |
| 802 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 803 | if (nand_ret) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 804 | return NANDC_RESULT_FAILURE; |
| 805 | |
| 806 | qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX); |
| 807 | |
| 808 | return nand_ret; |
| 809 | } |
| 810 | |
| 811 | static int |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 812 | qpic_nand_block_isbad(unsigned page) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 813 | { |
| 814 | unsigned cwperpage; |
| 815 | struct cfg_params params; |
| 816 | uint8_t bad_block[4]; |
| 817 | unsigned nand_ret = NANDC_RESULT_SUCCESS; |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 818 | uint32_t blk = page / flash.num_pages_per_blk; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 819 | |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 820 | if (bbtbl[blk] == NAND_BAD_BLK_VALUE_IS_GOOD) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 821 | return NANDC_RESULT_SUCCESS; |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 822 | else if (bbtbl[blk] == NAND_BAD_BLK_VALUE_IS_BAD) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 823 | return NANDC_RESULT_BAD_BLOCK; |
| 824 | else |
| 825 | { |
| 826 | /* Read the bad block value from the flash. |
| 827 | * Bad block value is stored in the first page of the block. |
| 828 | */ |
| 829 | /* Read the first page in the block. */ |
| 830 | cwperpage = flash.cws_per_page; |
| 831 | |
| 832 | /* Read page cmd */ |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 833 | params.cmd = NAND_CMD_PAGE_READ_ECC; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 834 | /* Clear the CW per page bits */ |
| 835 | params.cfg0 = cfg0_raw & ~(7U << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT); |
| 836 | params.cfg1 = cfg1_raw; |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 837 | /* addr0 - Write column addr + few bits in row addr upto 32 bits. */ |
| 838 | params.addr0 = (page << 16) | (USER_DATA_BYTES_PER_CW * cwperpage); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 839 | |
| 840 | /* addr1 - Write rest of row addr. |
| 841 | * This will be all 0s. |
| 842 | */ |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 843 | params.addr1 = (page >> 16) & 0xff; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 844 | params.addr_loc_0 = NAND_RD_LOC_OFFSET(0); |
| 845 | params.addr_loc_0 |= NAND_RD_LOC_LAST_BIT(1); |
| 846 | params.addr_loc_0 |= NAND_RD_LOC_SIZE(4); /* Read 4 bytes */ |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 847 | params.ecc_cfg = ecc_bch_cfg | 0x1; /* Disable ECC */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 848 | params.exec = 1; |
| 849 | |
| 850 | if (qpic_nand_block_isbad_exec(¶ms, bad_block)) |
| 851 | { |
| 852 | dprintf(CRITICAL, |
| 853 | "Could not read bad block value\n"); |
| 854 | return NANDC_RESULT_FAILURE; |
| 855 | } |
| 856 | |
| 857 | if (flash.widebus) |
| 858 | { |
| 859 | if (bad_block[0] != 0xFF && bad_block[1] != 0xFF) |
| 860 | { |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 861 | bbtbl[blk] = NAND_BAD_BLK_VALUE_IS_BAD; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 862 | nand_ret = NANDC_RESULT_BAD_BLOCK; |
| 863 | } |
| 864 | } |
| 865 | else if (bad_block[0] != 0xFF) |
| 866 | { |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 867 | bbtbl[blk] = NAND_BAD_BLK_VALUE_IS_BAD; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 868 | nand_ret = NANDC_RESULT_BAD_BLOCK; |
| 869 | } |
| 870 | else |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 871 | bbtbl[blk] = NAND_BAD_BLK_VALUE_IS_GOOD; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 872 | |
| 873 | return nand_ret; |
| 874 | } |
| 875 | } |
| 876 | |
| 877 | /* Function to erase a block on the nand. |
| 878 | * page: Starting page address for the block. |
| 879 | */ |
| 880 | static int |
| 881 | qpic_nand_blk_erase(uint32_t page) |
| 882 | { |
| 883 | struct cfg_params cfg; |
| 884 | struct cmd_element *cmd_list_ptr = ce_array; |
| 885 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 886 | uint32_t status; |
| 887 | int num_desc = 0; |
| 888 | uint32_t blk_addr = page / flash.num_pages_per_blk; |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 889 | int nand_ret; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 890 | |
| 891 | /* Erase only if the block is not bad */ |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 892 | if (qpic_nand_block_isbad(page)) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 893 | { |
| 894 | dprintf(CRITICAL, |
| 895 | "NAND Erase error: Block address belongs to bad block: %d\n", |
| 896 | blk_addr); |
| 897 | return NANDC_RESULT_FAILURE; |
| 898 | } |
| 899 | |
| 900 | /* Fill in params for the erase flash cmd */ |
| 901 | cfg.addr0 = page; |
| 902 | cfg.addr1 = 0; |
| 903 | /* Clear CW_PER_PAGE in cfg0 */ |
| 904 | cfg.cfg0 = cfg0 & ~(7U << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT); |
| 905 | cfg.cfg1 = cfg1; |
| 906 | cfg.cmd = NAND_CMD_BLOCK_ERASE; |
| 907 | cfg.exec = 1; |
| 908 | |
| 909 | cmd_list_ptr = qpic_nand_add_cmd_ce(&cfg, cmd_list_ptr); |
| 910 | |
| 911 | /* Enqueue the desc for the above commands */ |
| 912 | bam_add_one_desc(&bam, |
| 913 | CMD_PIPE_INDEX, |
| 914 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 915 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 916 | BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG | BAM_DESC_LOCK_FLAG); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 917 | |
| 918 | cmd_list_ptr_start = cmd_list_ptr; |
| 919 | num_desc++; |
| 920 | |
| 921 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 922 | |
| 923 | status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr); |
| 924 | |
| 925 | cmd_list_ptr++; |
| 926 | cmd_list_ptr_start = cmd_list_ptr; |
| 927 | |
| 928 | /* QPIC controller automatically sends |
| 929 | * GET_STATUS cmd to the nand card because |
| 930 | * of the configuration programmed. |
| 931 | * Read the result of GET_STATUS cmd. |
| 932 | */ |
| 933 | cmd_list_ptr = qpic_nand_add_read_n_reset_status_ce(cmd_list_ptr, &status, 1); |
| 934 | |
| 935 | /* Enqueue the desc for the above commands */ |
| 936 | bam_add_one_desc(&bam, |
| 937 | CMD_PIPE_INDEX, |
| 938 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 939 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 940 | BAM_DESC_INT_FLAG | BAM_DESC_CMD_FLAG) ; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 941 | |
| 942 | num_desc = 1; |
| 943 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 944 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 945 | status = qpic_nand_check_status(status); |
| 946 | |
| 947 | /* Dummy read to unlock pipe. */ |
| 948 | nand_ret = qpic_nand_read_reg(NAND_FLASH_STATUS, BAM_DESC_UNLOCK_FLAG, cmd_list_ptr); |
| 949 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 950 | /* Check for status errors*/ |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 951 | if (status) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 952 | { |
| 953 | dprintf(CRITICAL, |
| 954 | "NAND Erase error: Block address belongs to bad block: %d\n", |
| 955 | blk_addr); |
| 956 | return NANDC_RESULT_FAILURE; |
| 957 | } |
| 958 | |
| 959 | /* Check for PROG_ERASE_OP_RESULT bit for the result of erase operation. */ |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 960 | if (!(status & PROG_ERASE_OP_RESULT)) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 961 | return NANDC_RESULT_SUCCESS; |
| 962 | |
| 963 | return NANDC_RESULT_FAILURE; |
| 964 | } |
| 965 | |
| 966 | /* Return num of desc added. */ |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 967 | static void |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 968 | qpic_nand_add_wr_page_cws_cmd_desc(struct cfg_params *cfg, |
| 969 | uint32_t status[], |
| 970 | enum nand_cfg_value cfg_mode) |
| 971 | { |
| 972 | struct cmd_element *cmd_list_ptr = ce_array; |
| 973 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 974 | uint32_t ecc; |
| 975 | int num_desc = 0; |
| 976 | int int_flag = 0; |
| 977 | |
| 978 | if (cfg_mode == NAND_CFG) |
| 979 | ecc = ecc_bch_cfg; |
| 980 | else |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 981 | ecc = ecc_bch_cfg | 0x1; /* Disable ECC */ |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 982 | |
| 983 | /* Add ECC configuration */ |
| 984 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_ECC_CFG, |
| 985 | (uint32_t)ecc, CE_WRITE_TYPE); |
| 986 | cmd_list_ptr++; |
| 987 | cmd_list_ptr = qpic_nand_add_addr_n_cfg_ce(cfg, cmd_list_ptr); |
| 988 | |
| 989 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, |
| 990 | (uint32_t)cfg->cmd, CE_WRITE_TYPE); |
| 991 | cmd_list_ptr++; |
| 992 | |
| 993 | /* Enqueue the desc for the above commands */ |
| 994 | bam_add_one_desc(&bam, |
| 995 | CMD_PIPE_INDEX, |
| 996 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 997 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 998 | BAM_DESC_CMD_FLAG | BAM_DESC_LOCK_FLAG); |
| 999 | |
| 1000 | num_desc++; |
| 1001 | |
| 1002 | /* Add CE for all the CWs */ |
| 1003 | for (unsigned i = 0; i < flash.cws_per_page; i++) |
| 1004 | { |
| 1005 | cmd_list_ptr_start = cmd_list_ptr; |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1006 | int_flag = BAM_DESC_INT_FLAG; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1007 | |
| 1008 | bam_add_cmd_element(cmd_list_ptr, NAND_EXEC_CMD, (uint32_t)cfg->exec, CE_WRITE_TYPE); |
| 1009 | cmd_list_ptr++; |
| 1010 | |
| 1011 | /* Enqueue the desc for the above commands */ |
| 1012 | bam_add_one_desc(&bam, |
| 1013 | CMD_PIPE_INDEX, |
| 1014 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1015 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1016 | BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG); |
| 1017 | |
| 1018 | num_desc++; |
| 1019 | cmd_list_ptr_start = cmd_list_ptr; |
| 1020 | |
| 1021 | /* Set interrupt bit only for the last CW */ |
| 1022 | if (i == flash.cws_per_page - 1) |
| 1023 | { |
| 1024 | cmd_list_ptr = qpic_nand_add_read_n_reset_status_ce(cmd_list_ptr, |
| 1025 | &status[i], |
| 1026 | 1); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1027 | } |
| 1028 | else |
| 1029 | cmd_list_ptr = qpic_nand_add_read_n_reset_status_ce(cmd_list_ptr, |
| 1030 | &status[i], |
| 1031 | 0); |
| 1032 | |
| 1033 | /* Enqueue the desc for the above commands */ |
| 1034 | bam_add_one_desc(&bam, |
| 1035 | CMD_PIPE_INDEX, |
| 1036 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1037 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1038 | int_flag | BAM_DESC_CMD_FLAG); |
| 1039 | num_desc++; |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1040 | |
| 1041 | qpic_nand_wait_for_cmd_exec(num_desc); |
| 1042 | |
| 1043 | status[i] = qpic_nand_check_status(status[i]); |
| 1044 | |
| 1045 | num_desc = 0; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1046 | } |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1047 | return; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1048 | } |
| 1049 | |
| 1050 | void |
| 1051 | qpic_add_wr_page_cws_data_desc(const void *buffer, |
| 1052 | enum nand_cfg_value cfg_mode, |
| 1053 | const void *spareaddr) |
| 1054 | { |
| 1055 | int len; |
| 1056 | int flags; |
| 1057 | uint32_t start; |
| 1058 | unsigned num_desc = 0; |
| 1059 | |
| 1060 | for( unsigned i = 0; i < flash.cws_per_page; i++) |
| 1061 | { |
| 1062 | flags = 0; |
| 1063 | |
| 1064 | /* Set the interrupt flag on the last CW write for the page. */ |
| 1065 | if( i == flash.cws_per_page - 1) |
| 1066 | flags |= BAM_DESC_INT_FLAG; |
| 1067 | |
| 1068 | if (cfg_mode != NAND_CFG_RAW) |
| 1069 | { |
| 1070 | start = (uint32_t)buffer + i * DATA_BYTES_IN_IMG_PER_CW; |
| 1071 | |
| 1072 | if (i < (flash.cws_per_page - 1)) |
| 1073 | { |
| 1074 | len = DATA_BYTES_IN_IMG_PER_CW; |
| 1075 | flags |= BAM_DESC_EOT_FLAG; |
| 1076 | } |
| 1077 | else |
| 1078 | { |
| 1079 | /* Allow space for spare bytes in the last page */ |
| 1080 | len = USER_DATA_BYTES_PER_CW - ((flash.cws_per_page - 1) << 2); |
| 1081 | flags = 0; |
| 1082 | } |
| 1083 | } |
| 1084 | else |
| 1085 | { |
| 1086 | start = (uint32_t)buffer; |
| 1087 | len = flash.cw_size; |
| 1088 | flags |= BAM_DESC_EOT_FLAG; |
| 1089 | } |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1090 | bam_add_one_desc(&bam, DATA_CONSUMER_PIPE_INDEX, (unsigned char*)PA(start), len, flags); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1091 | num_desc++; |
| 1092 | |
| 1093 | if ((i == (flash.cws_per_page - 1)) && (cfg_mode == NAND_CFG)) |
| 1094 | { |
| 1095 | /* write extra data */ |
| 1096 | start = (uint32_t)spareaddr; |
| 1097 | len = (flash.cws_per_page << 2); |
| 1098 | flags = BAM_DESC_EOT_FLAG | BAM_DESC_INT_FLAG; |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1099 | bam_add_one_desc(&bam, DATA_CONSUMER_PIPE_INDEX, (unsigned char*)PA(start), len, flags); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1100 | num_desc++; |
| 1101 | } |
| 1102 | } |
| 1103 | |
| 1104 | bam_sys_gen_event(&bam, DATA_CONSUMER_PIPE_INDEX, num_desc); |
| 1105 | } |
| 1106 | |
| 1107 | static nand_result_t |
| 1108 | qpic_nand_write_page(uint32_t pg_addr, |
| 1109 | enum nand_cfg_value cfg_mode, |
| 1110 | const void* buffer, |
| 1111 | const void* spareaddr) |
| 1112 | { |
| 1113 | struct cfg_params cfg; |
Deepa Dinamani | 16663a6 | 2013-02-07 16:25:59 -0800 | [diff] [blame] | 1114 | uint32_t status[QPIC_NAND_MAX_CWS_IN_PAGE]; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1115 | int nand_ret = NANDC_RESULT_SUCCESS; |
| 1116 | |
| 1117 | if (cfg_mode == NAND_CFG_RAW) |
| 1118 | { |
| 1119 | cfg.cfg0 = cfg0_raw; |
| 1120 | cfg.cfg1 = cfg1_raw; |
| 1121 | } |
| 1122 | else |
| 1123 | { |
| 1124 | cfg.cfg0 = cfg0; |
| 1125 | cfg.cfg1 = cfg1; |
| 1126 | } |
| 1127 | |
| 1128 | cfg.cmd = NAND_CMD_PRG_PAGE; |
| 1129 | cfg.exec = 1; |
| 1130 | |
| 1131 | cfg.addr0 = pg_addr << 16; |
| 1132 | cfg.addr1 = (pg_addr >> 16) & 0xff; |
| 1133 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1134 | qpic_add_wr_page_cws_data_desc(buffer, cfg_mode, spareaddr); |
| 1135 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1136 | qpic_nand_add_wr_page_cws_cmd_desc(&cfg, status, cfg_mode); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1137 | |
| 1138 | /* Check for errors */ |
| 1139 | for(unsigned i = 0; i < flash.cws_per_page; i++) |
| 1140 | { |
| 1141 | nand_ret = qpic_nand_check_status(status[i]); |
| 1142 | if (nand_ret) |
| 1143 | { |
| 1144 | dprintf(CRITICAL, |
| 1145 | "Failed to write CW %d for page: %d\n", |
| 1146 | i, pg_addr); |
| 1147 | break; |
| 1148 | } |
| 1149 | } |
| 1150 | |
| 1151 | /* Wait for data to be available */ |
| 1152 | qpic_nand_wait_for_data(DATA_CONSUMER_PIPE_INDEX); |
| 1153 | |
| 1154 | return nand_ret; |
| 1155 | } |
| 1156 | |
| 1157 | static int |
| 1158 | qpic_nand_mark_badblock(uint32_t page) |
| 1159 | { |
| 1160 | char empty_buf[NAND_CW_SIZE_8_BIT_ECC]; |
| 1161 | |
| 1162 | memset(empty_buf, 0, NAND_CW_SIZE_8_BIT_ECC); |
| 1163 | |
| 1164 | /* Going to first page of the block */ |
| 1165 | if (page & flash.num_pages_per_blk_mask) |
| 1166 | page = page - (page & flash.num_pages_per_blk_mask); |
| 1167 | |
| 1168 | return qpic_nand_write_page(page, NAND_CFG_RAW, empty_buf, 0); |
| 1169 | } |
| 1170 | |
| 1171 | static void |
| 1172 | qpic_nand_non_onfi_probe(struct flash_info *flash) |
| 1173 | { |
| 1174 | int dev_found = 0; |
| 1175 | unsigned index; |
| 1176 | uint32_t ecc_bits; |
| 1177 | |
| 1178 | /* Read the nand id. */ |
| 1179 | qpic_nand_fetch_id(flash); |
| 1180 | |
| 1181 | /* Check if we support the device */ |
Deepa Dinamani | 649a94a | 2013-03-07 14:37:31 -0800 | [diff] [blame] | 1182 | for (index = 0; index < (ARRAY_SIZE(supported_flash)); index++) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1183 | { |
| 1184 | if ((flash->id & supported_flash[index].mask) == |
| 1185 | (supported_flash[index].flash_id & (supported_flash[index].mask))) |
| 1186 | { |
| 1187 | dev_found = 1; |
| 1188 | break; |
| 1189 | } |
| 1190 | } |
| 1191 | |
| 1192 | if (dev_found) |
| 1193 | { |
| 1194 | flash->page_size = supported_flash[index].pagesize; |
| 1195 | flash->block_size = supported_flash[index].blksize; |
| 1196 | flash->spare_size = supported_flash[index].oobsize; |
| 1197 | ecc_bits = supported_flash[index].ecc_8_bits; |
| 1198 | |
| 1199 | /* Make sure that the block size and page size are defined. */ |
| 1200 | ASSERT(flash->block_size); |
| 1201 | ASSERT(flash->page_size); |
| 1202 | |
| 1203 | flash->num_blocks = supported_flash[index].density; |
| 1204 | flash->num_blocks /= (flash->block_size); |
| 1205 | flash->num_pages_per_blk = flash->block_size / flash->page_size; |
| 1206 | flash->num_pages_per_blk_mask = flash->num_pages_per_blk - 1; |
| 1207 | |
| 1208 | /* Look for 8bit BCH ECC Nand, TODO: ECC Correctability >= 8 */ |
| 1209 | if (ecc_bits) |
| 1210 | flash->ecc_width = NAND_WITH_8_BIT_ECC; |
| 1211 | else |
| 1212 | flash->ecc_width = NAND_WITH_4_BIT_ECC; |
| 1213 | |
| 1214 | flash->density = supported_flash[index].density; |
| 1215 | flash->widebus = supported_flash[index].widebus; |
| 1216 | |
| 1217 | return; |
| 1218 | } |
| 1219 | |
| 1220 | /* Flash device is not supported, print flash device info and halt */ |
| 1221 | if (dev_found == 0) |
| 1222 | { |
| 1223 | dprintf(CRITICAL, "NAND device is not supported: nandid: 0x%x" |
| 1224 | "maker=0x%02x device=0x%02x\n", |
| 1225 | flash->id, |
| 1226 | flash->vendor, |
| 1227 | flash->device); |
| 1228 | ASSERT(0); |
| 1229 | } |
| 1230 | |
| 1231 | dprintf(INFO, "nandid: 0x%x maker=0x%02x device=0x%02x page_size=%d\n", |
| 1232 | flash->id, |
| 1233 | flash->vendor, |
| 1234 | flash->device, |
| 1235 | flash->page_size); |
| 1236 | |
| 1237 | dprintf(INFO, "spare_size=%d block_size=%d num_blocks=%d\n", |
| 1238 | flash->spare_size, |
| 1239 | flash->block_size, |
| 1240 | flash->num_blocks); |
| 1241 | } |
| 1242 | |
| 1243 | void |
| 1244 | qpic_nand_init(struct qpic_nand_init_config *config) |
| 1245 | { |
| 1246 | uint32_t i; |
| 1247 | int nand_ret; |
| 1248 | |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 1249 | qpic_nand_clock_init(); |
| 1250 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1251 | nand_base = config->nand_base; |
| 1252 | |
Deepa Dinamani | e9ded13 | 2012-11-27 15:03:38 -0800 | [diff] [blame] | 1253 | qpic_bam_init(config); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1254 | |
Deepa Dinamani | 649a94a | 2013-03-07 14:37:31 -0800 | [diff] [blame] | 1255 | qpic_nand_non_onfi_probe(&flash); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1256 | |
| 1257 | /* Save the RAW and read/write configs */ |
| 1258 | qpic_nand_save_config(&flash); |
| 1259 | |
| 1260 | flash_spare_bytes = (unsigned char *)malloc(flash.spare_size); |
| 1261 | |
| 1262 | if (flash_spare_bytes == NULL) |
| 1263 | { |
| 1264 | dprintf(CRITICAL, "Failed to allocate memory for spare bytes\n"); |
| 1265 | return; |
| 1266 | } |
| 1267 | |
| 1268 | /* Create a bad block table */ |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1269 | bbtbl = (uint8_t *) malloc(sizeof(uint8_t) * flash.num_blocks); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1270 | |
| 1271 | if (bbtbl == NULL) |
| 1272 | { |
| 1273 | dprintf(CRITICAL, "Failed to allocate memory for bad block table\n"); |
| 1274 | return; |
| 1275 | } |
| 1276 | |
| 1277 | for (i = 0; i < flash.num_blocks; i++) |
| 1278 | bbtbl[i] = NAND_BAD_BLK_VALUE_NOT_READ; |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1279 | |
| 1280 | /* Set aside contiguous memory for reads/writes. |
| 1281 | * This is needed as the BAM transfers only work with |
| 1282 | * physically contiguous buffers. |
| 1283 | * We will copy any data to be written/ to be read from |
| 1284 | * nand to this buffer and this buffer will be submitted to BAM. |
| 1285 | */ |
| 1286 | rdwr_buf = (uint8_t*) malloc(flash.page_size + flash.spare_size); |
| 1287 | |
| 1288 | if (rdwr_buf == NULL) |
| 1289 | { |
| 1290 | dprintf(CRITICAL, "Failed to allocate memory for page reads or writes\n"); |
| 1291 | return; |
| 1292 | } |
| 1293 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1294 | /* Reset and Configure erased CW/page detection controller. */ |
| 1295 | qpic_nand_erased_status_reset(ce_array); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1296 | } |
| 1297 | |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1298 | unsigned |
| 1299 | flash_page_size(void) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1300 | { |
| 1301 | return flash.page_size; |
| 1302 | } |
| 1303 | |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1304 | unsigned |
| 1305 | flash_block_size(void) |
| 1306 | { |
| 1307 | return flash.block_size; |
| 1308 | } |
| 1309 | |
Deepa Dinamani | 8e6b243 | 2012-10-17 17:12:44 -0700 | [diff] [blame] | 1310 | unsigned |
| 1311 | flash_num_blocks(void) |
| 1312 | { |
| 1313 | return flash.num_blocks; |
| 1314 | } |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1315 | |
| 1316 | struct ptable * |
| 1317 | flash_get_ptable(void) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1318 | { |
| 1319 | return flash_ptable; |
| 1320 | } |
| 1321 | |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1322 | void |
Deepa Dinamani | 87feab8 | 2012-10-04 14:28:05 -0700 | [diff] [blame] | 1323 | qpic_nand_uninit() |
| 1324 | { |
| 1325 | bam_pipe_reset(&bam, DATA_PRODUCER_PIPE_INDEX); |
| 1326 | bam_pipe_reset(&bam, DATA_CONSUMER_PIPE_INDEX); |
| 1327 | bam_pipe_reset(&bam, CMD_PIPE_INDEX); |
| 1328 | |
| 1329 | } |
| 1330 | void |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 1331 | flash_set_ptable(struct ptable *new_ptable) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1332 | { |
| 1333 | ASSERT(flash_ptable == NULL && new_ptable != NULL); |
| 1334 | flash_ptable = new_ptable; |
| 1335 | } |
| 1336 | |
| 1337 | /* Note: No support for raw reads. */ |
| 1338 | static int |
| 1339 | qpic_nand_read_page(uint32_t page, unsigned char* buffer, unsigned char* spareaddr) |
| 1340 | { |
| 1341 | struct cfg_params params; |
| 1342 | uint32_t ecc; |
Deepa Dinamani | 16663a6 | 2013-02-07 16:25:59 -0800 | [diff] [blame] | 1343 | uint32_t flash_sts[QPIC_NAND_MAX_CWS_IN_PAGE]; |
| 1344 | uint32_t buffer_sts[QPIC_NAND_MAX_CWS_IN_PAGE]; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1345 | uint32_t addr_loc_0; |
| 1346 | uint32_t addr_loc_1; |
| 1347 | struct cmd_element *cmd_list_ptr = ce_array; |
| 1348 | struct cmd_element *cmd_list_ptr_start = ce_array; |
| 1349 | uint32_t num_cmd_desc = 0; |
| 1350 | uint32_t num_data_desc = 0; |
| 1351 | uint32_t status; |
| 1352 | uint32_t i; |
| 1353 | int nand_ret = NANDC_RESULT_SUCCESS; |
| 1354 | /* UD bytes in last CW is 512 - cws_per_page *4. |
| 1355 | * Since each of the CW read earlier reads 4 spare bytes. |
| 1356 | */ |
| 1357 | uint16_t ud_bytes_in_last_cw = USER_DATA_BYTES_PER_CW - ((flash.cws_per_page - 1) << 2); |
| 1358 | uint16_t oob_bytes = DATA_BYTES_IN_IMG_PER_CW - ud_bytes_in_last_cw; |
| 1359 | |
| 1360 | params.addr0 = page << 16; |
| 1361 | params.addr1 = (page >> 16) & 0xff; |
| 1362 | params.cfg0 = cfg0; |
| 1363 | params.cfg1 = cfg1; |
| 1364 | params.cmd = NAND_CMD_PAGE_READ_ALL; |
| 1365 | params.exec = 1; |
| 1366 | ecc = ecc_bch_cfg; |
| 1367 | |
| 1368 | /* Read all the Data bytes in the first 3 CWs. */ |
| 1369 | addr_loc_0 = NAND_RD_LOC_OFFSET(0); |
| 1370 | addr_loc_0 |= NAND_RD_LOC_SIZE(DATA_BYTES_IN_IMG_PER_CW); |
| 1371 | addr_loc_0 |= NAND_RD_LOC_LAST_BIT(1); |
| 1372 | |
| 1373 | |
| 1374 | addr_loc_1 = NAND_RD_LOC_OFFSET(ud_bytes_in_last_cw); |
| 1375 | addr_loc_1 |= NAND_RD_LOC_SIZE(oob_bytes); |
| 1376 | addr_loc_1 |= NAND_RD_LOC_LAST_BIT(1); |
| 1377 | |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 1378 | status = qpic_nand_block_isbad(page); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1379 | |
| 1380 | if (status) |
| 1381 | return status; |
| 1382 | |
| 1383 | for (i = 0; i < flash.cws_per_page; i++) |
| 1384 | { |
| 1385 | num_cmd_desc = 0; |
| 1386 | num_data_desc = 0; |
| 1387 | |
| 1388 | if (i == 0) |
| 1389 | { |
| 1390 | cmd_list_ptr = qpic_nand_add_addr_n_cfg_ce(¶ms, cmd_list_ptr); |
| 1391 | |
| 1392 | bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_ECC_CFG,(uint32_t)ecc, CE_WRITE_TYPE); |
| 1393 | cmd_list_ptr++; |
| 1394 | } |
| 1395 | else |
| 1396 | cmd_list_ptr_start = cmd_list_ptr; |
| 1397 | |
| 1398 | bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)params.cmd, CE_WRITE_TYPE); |
| 1399 | cmd_list_ptr++; |
| 1400 | |
| 1401 | if (i == flash.cws_per_page - 1) |
| 1402 | { |
| 1403 | addr_loc_0 = NAND_RD_LOC_OFFSET(0); |
| 1404 | addr_loc_0 |= NAND_RD_LOC_SIZE(ud_bytes_in_last_cw); |
| 1405 | addr_loc_0 |= NAND_RD_LOC_LAST_BIT(0); |
| 1406 | |
| 1407 | /* Write addr loc 1 only for the last CW. */ |
| 1408 | bam_add_cmd_element(cmd_list_ptr, NAND_READ_LOCATION_n(1), (uint32_t)addr_loc_1, CE_WRITE_TYPE); |
| 1409 | cmd_list_ptr++; |
| 1410 | |
| 1411 | /* Add Data desc */ |
| 1412 | bam_add_one_desc(&bam, |
| 1413 | DATA_PRODUCER_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1414 | (unsigned char *)PA((addr_t)buffer), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1415 | ud_bytes_in_last_cw, |
| 1416 | 0); |
| 1417 | num_data_desc++; |
| 1418 | |
| 1419 | bam_add_one_desc(&bam, |
| 1420 | DATA_PRODUCER_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1421 | (unsigned char *)PA((addr_t)spareaddr), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1422 | oob_bytes, |
| 1423 | BAM_DESC_INT_FLAG); |
| 1424 | num_data_desc++; |
| 1425 | |
| 1426 | bam_sys_gen_event(&bam, DATA_PRODUCER_PIPE_INDEX, num_data_desc); |
| 1427 | } |
| 1428 | else |
| 1429 | { |
| 1430 | /* Add Data desc */ |
| 1431 | bam_add_one_desc(&bam, |
| 1432 | DATA_PRODUCER_PIPE_INDEX, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1433 | (unsigned char *)PA((addr_t)buffer), |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1434 | DATA_BYTES_IN_IMG_PER_CW, |
| 1435 | BAM_DESC_INT_FLAG); |
| 1436 | num_data_desc++; |
| 1437 | bam_sys_gen_event(&bam, DATA_PRODUCER_PIPE_INDEX, num_data_desc); |
| 1438 | } |
| 1439 | |
| 1440 | /* Write addr loc 0. */ |
| 1441 | bam_add_cmd_element(cmd_list_ptr, |
| 1442 | NAND_READ_LOCATION_n(0), |
| 1443 | (uint32_t)addr_loc_0, |
| 1444 | CE_WRITE_TYPE); |
| 1445 | |
| 1446 | cmd_list_ptr++; |
| 1447 | bam_add_cmd_element(cmd_list_ptr, |
| 1448 | NAND_EXEC_CMD, |
| 1449 | (uint32_t)params.exec, |
| 1450 | CE_WRITE_TYPE); |
| 1451 | cmd_list_ptr++; |
| 1452 | |
| 1453 | /* Enqueue the desc for the above commands */ |
| 1454 | bam_add_one_desc(&bam, |
| 1455 | CMD_PIPE_INDEX, |
| 1456 | (unsigned char*)cmd_list_ptr_start, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1457 | PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), |
Deepa Dinamani | 4b718ec | 2012-09-20 11:24:47 -0700 | [diff] [blame] | 1458 | BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG | BAM_DESC_LOCK_FLAG); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1459 | num_cmd_desc++; |
| 1460 | |
| 1461 | qpic_nand_wait_for_cmd_exec(num_cmd_desc); |
| 1462 | |
| 1463 | qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX); |
| 1464 | |
| 1465 | /* Save the status registers. */ |
| 1466 | flash_sts[i] = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr++); |
| 1467 | buffer_sts[i] = qpic_nand_read_reg(NAND_BUFFER_STATUS, 0, cmd_list_ptr++); |
| 1468 | |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1469 | flash_sts[i] = qpic_nand_check_status(flash_sts[i]); |
| 1470 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1471 | buffer += DATA_BYTES_IN_IMG_PER_CW; |
| 1472 | } |
| 1473 | |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 1474 | /* Read the buffer status again so that we can unlock the bam with this desc. */ |
| 1475 | buffer_sts[--i] = qpic_nand_read_reg(NAND_BUFFER_STATUS, BAM_DESC_UNLOCK_FLAG, cmd_list_ptr++); |
Deepa Dinamani | 4b718ec | 2012-09-20 11:24:47 -0700 | [diff] [blame] | 1476 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1477 | /* Check status */ |
| 1478 | for (i = 0; i < flash.cws_per_page ; i ++) |
Deepa Dinamani | 1953006 | 2012-10-03 14:43:05 -0700 | [diff] [blame] | 1479 | if (flash_sts[i]) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1480 | { |
| 1481 | nand_ret = NANDC_RESULT_BAD_PAGE; |
| 1482 | dprintf(CRITICAL, "NAND page read failed. page: %x\n", page); |
| 1483 | goto qpic_nand_read_page_error; |
| 1484 | } |
| 1485 | |
| 1486 | qpic_nand_read_page_error: |
| 1487 | return nand_ret; |
| 1488 | } |
| 1489 | |
| 1490 | /* Function to read a flash partition. |
| 1491 | * ptn : Partition to read. |
| 1492 | * extra_per_page : Spare data to be read. |
| 1493 | * offset : Num of bytes offset into the partition. |
| 1494 | * data : Buffer to read the data into. |
| 1495 | * bytes : Num of bytes to be read. |
| 1496 | */ |
| 1497 | /* TODO: call this func read_partition. */ |
| 1498 | int |
| 1499 | flash_read_ext(struct ptentry *ptn, |
| 1500 | unsigned extra_per_page, |
| 1501 | unsigned offset, |
| 1502 | void *data, |
| 1503 | unsigned bytes) |
| 1504 | { |
| 1505 | uint32_t page = |
| 1506 | (ptn->start * flash.num_pages_per_blk) + (offset / flash.page_size); |
| 1507 | uint32_t lastpage = (ptn->start + ptn->length) * flash.num_pages_per_blk; |
| 1508 | uint32_t count = |
| 1509 | (bytes + flash.page_size - 1 + extra_per_page) / (flash.page_size + |
| 1510 | extra_per_page); |
| 1511 | uint32_t *spare = (unsigned *)flash_spare_bytes; |
| 1512 | uint32_t errors = 0; |
| 1513 | unsigned char *image = data; |
| 1514 | int result = 0; |
| 1515 | uint32_t current_block = |
| 1516 | (page - (page & flash.num_pages_per_blk_mask)) / flash.num_pages_per_blk; |
| 1517 | uint32_t start_block = ptn->start; |
| 1518 | uint32_t start_block_count = 0; |
| 1519 | uint32_t isbad = 0; |
| 1520 | |
| 1521 | /* Verify first byte is at page boundary. */ |
| 1522 | if (offset & (flash.page_size - 1)) |
| 1523 | { |
| 1524 | dprintf(CRITICAL, "Read request start not at page boundary: %d\n", |
| 1525 | offset); |
| 1526 | return NANDC_RESULT_PARAM_INVALID; |
| 1527 | } |
| 1528 | |
| 1529 | /* Adjust page offset based on number of bad blocks from start to current page */ |
| 1530 | if (start_block < current_block) |
| 1531 | { |
| 1532 | start_block_count = (current_block - start_block); |
| 1533 | while (start_block_count |
| 1534 | && (start_block < (ptn->start + ptn->length))) |
| 1535 | { |
Deepa Dinamani | dc1381e | 2012-11-15 14:53:24 -0800 | [diff] [blame] | 1536 | isbad = qpic_nand_block_isbad(page); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1537 | if (isbad) |
| 1538 | page += flash.num_pages_per_blk; |
| 1539 | else |
| 1540 | start_block_count--; |
| 1541 | start_block++; |
| 1542 | } |
| 1543 | } |
| 1544 | |
| 1545 | while ((page < lastpage) && !start_block_count) |
| 1546 | { |
| 1547 | if (count == 0) |
| 1548 | { |
Deepa Dinamani | 52aca8d | 2013-02-05 11:41:41 -0800 | [diff] [blame] | 1549 | dprintf(SPEW, "flash_read_image: success (%d errors)\n", |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1550 | errors); |
| 1551 | return NANDC_RESULT_SUCCESS; |
| 1552 | } |
| 1553 | |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1554 | result = qpic_nand_read_page(page, rdwr_buf, (unsigned char *)spare); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1555 | |
| 1556 | if (result == NANDC_RESULT_BAD_PAGE) |
| 1557 | { |
| 1558 | /* bad page, go to next page. */ |
| 1559 | page++; |
| 1560 | errors++; |
| 1561 | continue; |
| 1562 | } |
| 1563 | else if (result == NANDC_RESULT_BAD_BLOCK) |
| 1564 | { |
| 1565 | /* bad block, go to next block same offset. */ |
| 1566 | page += flash.num_pages_per_blk; |
| 1567 | errors++; |
| 1568 | continue; |
| 1569 | } |
| 1570 | |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1571 | /* Copy the read page into correct location. */ |
| 1572 | memcpy(image, rdwr_buf, flash.page_size); |
| 1573 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1574 | page++; |
| 1575 | image += flash.page_size; |
| 1576 | /* Copy spare bytes to image */ |
| 1577 | memcpy(image, spare, extra_per_page); |
| 1578 | image += extra_per_page; |
| 1579 | count -= 1; |
| 1580 | } |
| 1581 | |
| 1582 | /* could not find enough valid pages before we hit the end */ |
| 1583 | dprintf(CRITICAL, "flash_read_image: failed (%d errors)\n", errors); |
| 1584 | return NANDC_RESULT_FAILURE; |
| 1585 | } |
| 1586 | |
| 1587 | int |
| 1588 | flash_erase(struct ptentry *ptn) |
| 1589 | { |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 1590 | int ret = 0; |
| 1591 | |
| 1592 | ret = qpic_nand_blk_erase(ptn->start * flash.num_pages_per_blk); |
| 1593 | |
| 1594 | if (ret) |
| 1595 | dprintf(CRITICAL, "Erase operation failed \n"); |
| 1596 | |
| 1597 | return ret; |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1598 | } |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 1599 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1600 | int |
| 1601 | flash_ecc_bch_enabled() |
| 1602 | { |
| 1603 | return (flash.ecc_width == NAND_WITH_4_BIT_ECC)? 0 : 1; |
| 1604 | } |
| 1605 | |
| 1606 | int |
| 1607 | flash_write(struct ptentry *ptn, |
| 1608 | unsigned extra_per_page, |
| 1609 | const void *data, |
| 1610 | unsigned bytes) |
| 1611 | { |
| 1612 | uint32_t page = ptn->start * flash.num_pages_per_blk; |
| 1613 | uint32_t lastpage = (ptn->start + ptn->length) * flash.num_pages_per_blk; |
| 1614 | uint32_t *spare = (unsigned *)flash_spare_bytes; |
| 1615 | const unsigned char *image = data; |
| 1616 | uint32_t wsize = flash.page_size + extra_per_page; |
| 1617 | int r; |
| 1618 | |
| 1619 | memset(spare, 0xff, (flash.spare_size / flash.cws_per_page)); |
| 1620 | |
| 1621 | while (bytes > 0) |
| 1622 | { |
| 1623 | if (bytes < wsize) |
| 1624 | { |
| 1625 | dprintf(CRITICAL, |
| 1626 | "flash_write_image: image undersized (%d < %d)\n", |
| 1627 | bytes, |
| 1628 | wsize); |
| 1629 | return -1; |
| 1630 | } |
| 1631 | |
| 1632 | if (page >= lastpage) |
| 1633 | { |
| 1634 | dprintf(CRITICAL, "flash_write_image: out of space\n"); |
| 1635 | return -1; |
| 1636 | } |
| 1637 | |
| 1638 | if ((page & flash.num_pages_per_blk_mask) == 0) |
| 1639 | { |
Deepa Dinamani | 2467bbb | 2012-10-02 13:59:58 -0700 | [diff] [blame] | 1640 | if (qpic_nand_blk_erase(page)) |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1641 | { |
| 1642 | dprintf(INFO, |
| 1643 | "flash_write_image: bad block @ %d\n", |
| 1644 | page / flash.num_pages_per_blk); |
| 1645 | |
| 1646 | page += flash.num_pages_per_blk; |
| 1647 | continue; |
| 1648 | } |
| 1649 | } |
| 1650 | |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1651 | memcpy(rdwr_buf, image, flash.page_size); |
| 1652 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1653 | if (extra_per_page) |
| 1654 | { |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1655 | memcpy(rdwr_buf + flash.page_size, image + flash.page_size, extra_per_page); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1656 | r = qpic_nand_write_page(page, |
| 1657 | NAND_CFG, |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1658 | rdwr_buf, |
| 1659 | rdwr_buf + flash.page_size); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1660 | } |
| 1661 | else |
| 1662 | { |
Deepa Dinamani | 0bf2f44 | 2012-10-19 11:41:06 -0700 | [diff] [blame] | 1663 | r = qpic_nand_write_page(page, NAND_CFG, rdwr_buf, spare); |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 1664 | } |
| 1665 | |
| 1666 | if (r) |
| 1667 | { |
| 1668 | dprintf(INFO, |
| 1669 | "flash_write_image: write failure @ page %d (src %d)\n", |
| 1670 | page, |
| 1671 | image - (const unsigned char *)data); |
| 1672 | |
| 1673 | image -= (page & flash.num_pages_per_blk_mask) * wsize; |
| 1674 | bytes += (page & flash.num_pages_per_blk_mask) * wsize; |
| 1675 | page &= ~flash.num_pages_per_blk_mask; |
| 1676 | if (qpic_nand_blk_erase(page)) |
| 1677 | { |
| 1678 | dprintf(INFO, |
| 1679 | "flash_write_image: erase failure @ page %d\n", |
| 1680 | page); |
| 1681 | } |
| 1682 | |
| 1683 | qpic_nand_mark_badblock(page); |
| 1684 | |
| 1685 | dprintf(INFO, |
| 1686 | "flash_write_image: restart write @ page %d (src %d)\n", |
| 1687 | page, image - (const unsigned char *)data); |
| 1688 | |
| 1689 | page += flash.num_pages_per_blk; |
| 1690 | continue; |
| 1691 | } |
| 1692 | page++; |
| 1693 | image += wsize; |
| 1694 | bytes -= wsize; |
| 1695 | } |
| 1696 | |
| 1697 | /* erase any remaining pages in the partition */ |
| 1698 | page = (page + flash.num_pages_per_blk_mask) & (~flash.num_pages_per_blk_mask); |
| 1699 | |
| 1700 | while (page < lastpage) |
| 1701 | { |
| 1702 | if (qpic_nand_blk_erase(page)) |
| 1703 | { |
| 1704 | dprintf(INFO, "flash_write_image: bad block @ %d\n", |
| 1705 | page / flash.num_pages_per_blk); |
| 1706 | } |
| 1707 | page += flash.num_pages_per_blk; |
| 1708 | } |
| 1709 | |
| 1710 | dprintf(INFO, "flash_write_image: success\n"); |
| 1711 | return 0; |
| 1712 | } |