Wenjun Zhang | 4e63ce4 | 2017-11-28 05:11:34 -0500 | [diff] [blame^] | 1 | /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _PLATFORM_MSM_SHARED_MSM_PANEL_H_ |
| 31 | #define _PLATFORM_MSM_SHARED_MSM_PANEL_H_ |
| 32 | |
Channagoud Kadabi | fb6ff7e | 2015-07-13 20:13:05 -0700 | [diff] [blame] | 33 | #include <sys/types.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 34 | #include <stdint.h> |
| 35 | #include <dev/fbcon.h> |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 36 | #include <sys/types.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 37 | |
Padmanabhan Komanduru | eb5bf6c | 2016-02-29 18:54:35 +0530 | [diff] [blame] | 38 | #define DFPS_MAX_FRAME_RATE 20 |
Huaibin Yang | b9f15e5 | 2015-01-22 10:34:47 -0800 | [diff] [blame] | 39 | #define DFPS_PLL_CODES_SIZE 0x1000 /* One page */ |
Huaibin Yang | 88540b3 | 2014-11-07 13:59:54 -0800 | [diff] [blame] | 40 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 41 | /* panel type list */ |
| 42 | #define NO_PANEL 0xffff /* No Panel */ |
| 43 | #define MDDI_PANEL 1 /* MDDI */ |
| 44 | #define EBI2_PANEL 2 /* EBI2 */ |
| 45 | #define LCDC_PANEL 3 /* internal LCDC type */ |
| 46 | #define EXT_MDDI_PANEL 4 /* Ext.MDDI */ |
| 47 | #define TV_PANEL 5 /* TV */ |
| 48 | #define HDMI_PANEL 6 /* HDMI TV */ |
| 49 | #define DTV_PANEL 7 /* DTV */ |
| 50 | #define MIPI_VIDEO_PANEL 8 /* MIPI */ |
| 51 | #define MIPI_CMD_PANEL 9 /* MIPI */ |
| 52 | #define WRITEBACK_PANEL 10 /* Wifi display */ |
| 53 | #define LVDS_PANEL 11 /* LVDS */ |
Asaf Penso | b8f524c | 2013-05-20 12:32:31 +0300 | [diff] [blame] | 54 | #define EDP_PANEL 12 /* EDP */ |
Zohaib Alam | b7b677f | 2014-10-24 15:54:42 -0400 | [diff] [blame] | 55 | #define QPIC_PANEL 13 /* QPIC */ |
Wenjun Zhang | 4e63ce4 | 2017-11-28 05:11:34 -0500 | [diff] [blame^] | 56 | #define SPI_PANEL 14 |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 57 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 58 | #define DISPLAY_UNKNOWN 0 |
| 59 | #define DISPLAY_1 1 |
| 60 | #define DISPLAY_2 2 |
| 61 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 62 | enum mdss_mdp_pipe_type { |
| 63 | MDSS_MDP_PIPE_TYPE_VIG, |
| 64 | MDSS_MDP_PIPE_TYPE_RGB, |
| 65 | MDSS_MDP_PIPE_TYPE_DMA, |
| 66 | }; |
| 67 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 68 | enum msm_mdp_hw_revision { |
| 69 | MDP_REV_20 = 1, |
| 70 | MDP_REV_22, |
| 71 | MDP_REV_30, |
| 72 | MDP_REV_303, |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 73 | MDP_REV_304, |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 74 | MDP_REV_305, |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 75 | MDP_REV_31, |
| 76 | MDP_REV_40, |
| 77 | MDP_REV_41, |
| 78 | MDP_REV_42, |
| 79 | MDP_REV_43, |
| 80 | MDP_REV_44, |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 81 | MDP_REV_50, |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 82 | }; |
| 83 | |
| 84 | /* panel info type */ |
| 85 | struct lcd_panel_info { |
| 86 | uint32_t vsync_enable; |
| 87 | uint32_t refx100; |
| 88 | uint32_t v_back_porch; |
| 89 | uint32_t v_front_porch; |
| 90 | uint32_t v_pulse_width; |
| 91 | uint32_t hw_vsync_mode; |
| 92 | uint32_t vsync_notifier_period; |
| 93 | uint32_t rev; |
| 94 | }; |
| 95 | |
Wenjun Zhang | 4e63ce4 | 2017-11-28 05:11:34 -0500 | [diff] [blame^] | 96 | struct mdss_spi_cmd { |
| 97 | int size; |
| 98 | char *payload; |
| 99 | int wait; |
| 100 | uint8_t cmds_post_tg; |
| 101 | }; |
| 102 | |
| 103 | struct spi_panel_info { |
| 104 | int num_of_panel_cmds; |
| 105 | struct mdss_spi_cmd *panel_cmds; |
| 106 | uint8_t *signature_addr; |
| 107 | uint8_t *signature; |
| 108 | uint8_t *signature_len; |
| 109 | }; |
| 110 | |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 111 | struct hdmi_panel_info { |
| 112 | uint32_t h_back_porch; |
| 113 | uint32_t h_front_porch; |
| 114 | uint32_t h_pulse_width; |
| 115 | uint32_t v_back_porch; |
| 116 | uint32_t v_front_porch; |
| 117 | uint32_t v_pulse_width; |
| 118 | }; |
| 119 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 120 | struct lcdc_panel_info { |
| 121 | uint32_t h_back_porch; |
| 122 | uint32_t h_front_porch; |
| 123 | uint32_t h_pulse_width; |
| 124 | uint32_t v_back_porch; |
| 125 | uint32_t v_front_porch; |
| 126 | uint32_t v_pulse_width; |
| 127 | uint32_t border_clr; |
| 128 | uint32_t underflow_clr; |
| 129 | uint32_t hsync_skew; |
| 130 | /* Pad width */ |
| 131 | uint32_t xres_pad; |
| 132 | /* Pad height */ |
| 133 | uint32_t yres_pad; |
Siddhartha Agrawal | 547ce4a | 2013-05-23 14:10:43 -0700 | [diff] [blame] | 134 | uint8_t dual_pipe; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 135 | uint8_t split_display; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 136 | uint8_t pipe_swap; |
Vineet Bajaj | 4effb13 | 2014-07-24 16:55:41 +0530 | [diff] [blame] | 137 | uint8_t dst_split; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 138 | }; |
| 139 | |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 140 | enum { |
| 141 | COMPRESSION_NONE, |
| 142 | COMPRESSION_DSC, |
| 143 | COMPRESSION_FBC |
| 144 | }; |
| 145 | |
| 146 | #define DCS_HDR_LEN 4 |
| 147 | #define DSC_PPS_LEN 128 |
| 148 | |
| 149 | struct msm_panel_info; |
| 150 | |
| 151 | struct dsc_desc { |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 152 | int initial_lines; |
| 153 | int slice_last_group_size; |
| 154 | int bpp; /* target bit per pixel */ |
| 155 | int bpc; /* bit per component */ |
| 156 | int line_buf_depth; |
| 157 | int config_by_manufacture_cmd; |
| 158 | int block_pred_enable; |
| 159 | int vbr_enable; |
| 160 | int enable_422; |
| 161 | int convert_rgb; |
| 162 | int input_10_bits; |
| 163 | int slice_per_pkt; |
| 164 | |
| 165 | int major; |
| 166 | int minor; |
Dhaval Patel | c4135d8 | 2016-03-30 17:40:53 -0700 | [diff] [blame] | 167 | int scr_rev; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 168 | int pps_id; |
| 169 | |
| 170 | int pic_height; |
| 171 | int pic_width; |
| 172 | int slice_height; |
| 173 | int slice_width; |
| 174 | int chunk_size; |
| 175 | |
| 176 | int pkt_per_line; |
| 177 | int bytes_in_slice; |
| 178 | int bytes_per_pkt; |
| 179 | int eol_byte_num; |
| 180 | int pclk_per_line; /* width */ |
| 181 | |
| 182 | int initial_dec_delay; |
| 183 | int initial_xmit_delay; |
| 184 | |
| 185 | int initial_scale_value; |
| 186 | int scale_decrement_interval; |
| 187 | int scale_increment_interval; |
| 188 | |
| 189 | int first_line_bpg_offset; |
| 190 | int nfl_bpg_offset; |
| 191 | int slice_bpg_offset; |
| 192 | |
| 193 | int initial_offset; |
| 194 | int final_offset; |
| 195 | |
| 196 | int rc_model_size; /* rate_buffer_size */ |
| 197 | |
| 198 | int det_thresh_flatness; |
| 199 | int max_qp_flatness; |
| 200 | int min_qp_flatness; |
| 201 | int edge_factor; |
| 202 | int quant_incr_limit0; |
| 203 | int quant_incr_limit1; |
| 204 | int tgt_offset_hi; |
| 205 | int tgt_offset_lo; |
| 206 | char *buf_thresh; |
| 207 | char *range_min_qp; |
| 208 | char *range_max_qp; |
| 209 | char *range_bpg_offset; |
| 210 | char pps_buf[DCS_HDR_LEN + DSC_PPS_LEN]; |
| 211 | |
| 212 | void (*parameter_calc) (struct msm_panel_info *pinfo); |
| 213 | int (*dsc2buf) (struct msm_panel_info *pinfo); |
| 214 | void (*dsi_dsc_config) (uint32_t base, int mode, struct dsc_desc *dsc); |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 215 | void (*mdp_dsc_config) (struct msm_panel_info *pinfo, |
| 216 | unsigned int pp_base, unsigned int dsc_base, |
| 217 | bool mux, bool split_mode); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 218 | }; |
| 219 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 220 | struct fbc_panel_info { |
| 221 | uint32_t enabled; |
| 222 | uint32_t comp_ratio; |
| 223 | uint32_t comp_mode; |
| 224 | uint32_t qerr_enable; |
| 225 | uint32_t cd_bias; |
| 226 | uint32_t pat_enable; |
| 227 | uint32_t vlc_enable; |
| 228 | uint32_t bflc_enable; |
| 229 | |
| 230 | uint32_t line_x_budget; |
| 231 | uint32_t block_x_budget; |
| 232 | uint32_t block_budget; |
| 233 | |
| 234 | uint32_t lossless_mode_thd; |
| 235 | uint32_t lossy_mode_thd; |
| 236 | uint32_t lossy_rgb_thd; |
| 237 | uint32_t lossy_mode_idx; |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 238 | |
| 239 | uint32_t slice_height; |
| 240 | uint32_t pred_mode; |
| 241 | uint32_t max_pred_err; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 242 | }; |
| 243 | |
Huaibin Yang | 88540b3 | 2014-11-07 13:59:54 -0800 | [diff] [blame] | 244 | |
| 245 | struct dfps_panel_info { |
| 246 | uint32_t enabled; |
| 247 | uint32_t frame_rate_cnt; |
| 248 | uint32_t frame_rate[DFPS_MAX_FRAME_RATE]; |
| 249 | }; |
| 250 | |
| 251 | struct dfps_pll_codes { |
| 252 | uint32_t codes[2]; |
| 253 | }; |
| 254 | |
| 255 | struct dfps_codes_info { |
| 256 | uint32_t is_valid; |
| 257 | uint32_t frame_rate; |
| 258 | uint32_t clk_rate; |
| 259 | struct dfps_pll_codes pll_codes; |
| 260 | }; |
| 261 | |
| 262 | struct dfps_info { |
| 263 | struct dfps_panel_info panel_dfps; |
| 264 | struct dfps_codes_info codes_dfps[DFPS_MAX_FRAME_RATE]; |
| 265 | void *dfps_fb_base; |
Ashish Garg | 342420a | 2017-04-24 18:00:12 +0530 | [diff] [blame] | 266 | uint32_t chip_serial; |
Huaibin Yang | 88540b3 | 2014-11-07 13:59:54 -0800 | [diff] [blame] | 267 | }; |
| 268 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 269 | /* intf timing settings */ |
| 270 | struct intf_timing_params { |
| 271 | uint32_t width; |
| 272 | uint32_t height; |
| 273 | uint32_t xres; |
| 274 | uint32_t yres; |
| 275 | |
| 276 | uint32_t h_back_porch; |
| 277 | uint32_t h_front_porch; |
| 278 | uint32_t v_back_porch; |
| 279 | uint32_t v_front_porch; |
| 280 | uint32_t hsync_pulse_width; |
| 281 | uint32_t vsync_pulse_width; |
| 282 | |
| 283 | uint32_t border_clr; |
| 284 | uint32_t underflow_clr; |
| 285 | uint32_t hsync_skew; |
| 286 | }; |
| 287 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 288 | struct mipi_panel_info { |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 289 | char cmds_post_tg; /* send on commands after tg on */ |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 290 | char mode; /* video/cmd */ |
| 291 | char interleave_mode; |
Arpita Banerjee | f1a8ac9 | 2013-05-21 10:09:35 -0700 | [diff] [blame] | 292 | int eof_bllp_power; |
Arpita Banerjee | 2522bc6 | 2013-05-24 16:03:53 -0700 | [diff] [blame] | 293 | uint32_t bitclock; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 294 | char crc_check; |
| 295 | char ecc_check; |
| 296 | char dst_format; /* shared by video and command */ |
| 297 | char num_of_lanes; |
| 298 | char data_lane0; |
| 299 | char data_lane1; |
| 300 | char data_lane2; |
| 301 | char data_lane3; |
| 302 | char dlane_swap; /* data lane swap */ |
| 303 | char rgb_swap; |
| 304 | char b_sel; |
| 305 | char g_sel; |
| 306 | char r_sel; |
| 307 | char rx_eot_ignore; |
| 308 | char tx_eot_append; |
| 309 | char t_clk_post; /* 0xc0, DSI_CLKOUT_TIMING_CTRL */ |
| 310 | char t_clk_pre; /* 0xc0, DSI_CLKOUT_TIMING_CTRL */ |
| 311 | char vc; /* virtual channel */ |
| 312 | struct mipi_dsi_phy_ctrl *dsi_phy_db; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 313 | struct mdss_dsi_phy_ctrl *mdss_dsi_phy_db; |
Arpita Banerjee | 2522bc6 | 2013-05-24 16:03:53 -0700 | [diff] [blame] | 314 | struct mdss_dsi_pll_config *dsi_pll_config; |
Padmanabhan Komanduru | b3d3184 | 2014-11-04 15:47:53 +0530 | [diff] [blame] | 315 | struct mipi_dsi_cmd *panel_on_cmds; |
| 316 | int num_of_panel_on_cmds; |
| 317 | struct mipi_dsi_cmd *panel_off_cmds; |
| 318 | int num_of_panel_off_cmds; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 319 | /* video mode */ |
| 320 | char pulse_mode_hsa_he; |
| 321 | char hfp_power_stop; |
| 322 | char hbp_power_stop; |
| 323 | char hsa_power_stop; |
| 324 | char eof_bllp_power_stop; |
| 325 | char bllp_power_stop; |
| 326 | char traffic_mode; |
| 327 | char frame_rate; |
| 328 | /* command mode */ |
| 329 | char interleave_max; |
| 330 | char insert_dcs_cmd; |
| 331 | char wr_mem_continue; |
| 332 | char wr_mem_start; |
| 333 | char te_sel; |
| 334 | char stream; /* 0 or 1 */ |
| 335 | char mdp_trigger; |
| 336 | char dma_trigger; |
| 337 | uint32_t dsi_pclk_rate; |
| 338 | /* The packet-size should not bet changed */ |
| 339 | char no_max_pkt_size; |
| 340 | /* Clock required during LP commands */ |
| 341 | char force_clk_lane_hs; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 342 | char lane_swap; |
Siddhartha Agrawal | 547ce4a | 2013-05-23 14:10:43 -0700 | [diff] [blame] | 343 | uint8_t dual_dsi; |
Padmanabhan Komanduru | c0766c8 | 2015-04-27 16:39:15 -0700 | [diff] [blame] | 344 | uint8_t use_dsi1_pll; |
Siddhartha Agrawal | 547ce4a | 2013-05-23 14:10:43 -0700 | [diff] [blame] | 345 | uint8_t broadcast; |
Dhaval Patel | 940e09c | 2013-08-08 20:47:05 -0700 | [diff] [blame] | 346 | uint8_t mode_gpio_state; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 347 | uint32_t signature; |
Aravind Venkateswaran | 27338a9 | 2013-11-04 17:27:05 -0800 | [diff] [blame] | 348 | uint32_t use_enable_gpio; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 349 | uint32_t ctl_base; |
| 350 | uint32_t phy_base; |
| 351 | uint32_t sctl_base; |
| 352 | uint32_t sphy_base; |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 353 | uint32_t reg_base; |
| 354 | uint32_t sreg_base; |
Padmanabhan Komanduru | c0766c8 | 2015-04-27 16:39:15 -0700 | [diff] [blame] | 355 | uint32_t pll_base; |
| 356 | uint32_t spll_base; |
Huaibin Yang | 88540b3 | 2014-11-07 13:59:54 -0800 | [diff] [blame] | 357 | |
| 358 | struct dfps_pll_codes pll_codes; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 359 | }; |
| 360 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 361 | struct edp_panel_info { |
| 362 | int max_lane_count; |
| 363 | unsigned long max_link_clk; |
| 364 | }; |
| 365 | |
Vineet Bajaj | c227246 | 2015-05-07 17:35:03 +0530 | [diff] [blame] | 366 | struct dsi2HDMI_panel_info { |
| 367 | struct mipi_dsi_i2c_cmd *dsi_tg_i2c_cmd; |
| 368 | struct mipi_dsi_i2c_cmd *dsi_setup_cfg_i2c_cmd; |
| 369 | int num_of_tg_i2c_cmds; |
| 370 | int num_of_cfg_i2c_cmds; |
Siddharth Zaveri | acaacc3 | 2015-12-12 15:10:33 -0500 | [diff] [blame] | 371 | uint8_t i2c_main_addr; |
| 372 | uint8_t i2c_cec_addr; |
| 373 | bool program_i2c_addr; |
Vineet Bajaj | c227246 | 2015-05-07 17:35:03 +0530 | [diff] [blame] | 374 | }; |
| 375 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 376 | enum lvds_mode { |
| 377 | LVDS_SINGLE_CHANNEL_MODE, |
| 378 | LVDS_DUAL_CHANNEL_MODE, |
| 379 | }; |
| 380 | |
| 381 | struct lvds_panel_info { |
| 382 | enum lvds_mode channel_mode; |
| 383 | /* Channel swap in dual mode */ |
| 384 | char channel_swap; |
| 385 | }; |
| 386 | |
Kuogee Hsieh | 9747d9e | 2014-12-05 15:42:11 -0800 | [diff] [blame] | 387 | struct labibb_desc { |
| 388 | char amoled_panel; /* lcd = 0, amoled = 1*/ |
| 389 | char force_config; /* 0 to use default value */ |
| 390 | uint32_t ibb_min_volt; |
| 391 | uint32_t ibb_max_volt; |
| 392 | uint32_t lab_min_volt; |
| 393 | uint32_t lab_max_volt; |
| 394 | char pwr_up_delay; /* ndx to => 1250, 2500, 5000 and 10000 us */ |
| 395 | char pwr_down_delay; /* ndx to => 1250, 2500, 5000 and 10000 us */ |
| 396 | char ibb_discharge_en; |
Vishnuvardhan Prodduturi | 4aa8dc4 | 2015-10-20 21:20:43 +0530 | [diff] [blame] | 397 | bool swire_control; |
Kuogee Hsieh | 9747d9e | 2014-12-05 15:42:11 -0800 | [diff] [blame] | 398 | }; |
| 399 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 400 | struct msm_panel_info { |
| 401 | uint32_t xres; |
| 402 | uint32_t yres; |
| 403 | uint32_t bpp; |
| 404 | uint32_t type; |
| 405 | uint32_t wait_cycle; |
| 406 | uint32_t clk_rate; |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 407 | uint32_t orientation; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 408 | uint32_t dest; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 409 | uint32_t compression_mode; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 410 | /* Select pipe type for handoff */ |
| 411 | uint32_t pipe_type; |
Arpita Banerjee | f1a8ac9 | 2013-05-21 10:09:35 -0700 | [diff] [blame] | 412 | char lowpowerstop; |
Kuogee Hsieh | 208736d | 2014-08-22 14:16:55 -0700 | [diff] [blame] | 413 | char lcd_reg_en; |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 414 | uint32_t border_top; |
| 415 | uint32_t border_bottom; |
| 416 | uint32_t border_left; |
| 417 | uint32_t border_right; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 418 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 419 | int lm_split[2]; |
| 420 | int num_dsc_enc; |
| 421 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 422 | struct lcd_panel_info lcd; |
| 423 | struct lcdc_panel_info lcdc; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 424 | struct fbc_panel_info fbc; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 425 | struct dsc_desc dsc; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 426 | struct mipi_panel_info mipi; |
| 427 | struct lvds_panel_info lvds; |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 428 | struct hdmi_panel_info hdmi; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 429 | struct edp_panel_info edp; |
Wenjun Zhang | 4e63ce4 | 2017-11-28 05:11:34 -0500 | [diff] [blame^] | 430 | struct spi_panel_info spi; |
Vineet Bajaj | c227246 | 2015-05-07 17:35:03 +0530 | [diff] [blame] | 431 | struct dsi2HDMI_panel_info adv7533; |
Siddharth Zaveri | acaacc3 | 2015-12-12 15:10:33 -0500 | [diff] [blame] | 432 | bool has_bridge_chip; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 433 | |
Huaibin Yang | 88540b3 | 2014-11-07 13:59:54 -0800 | [diff] [blame] | 434 | struct dfps_info dfps; |
| 435 | |
Kuogee Hsieh | 9747d9e | 2014-12-05 15:42:11 -0800 | [diff] [blame] | 436 | struct labibb_desc *labibb; |
| 437 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 438 | int (*on) (void); |
| 439 | int (*off) (void); |
Dhaval Patel | aa081d3 | 2013-10-25 13:47:46 -0700 | [diff] [blame] | 440 | int (*pre_on) (void); |
| 441 | int (*pre_off) (void); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 442 | int (*prepare) (void); |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 443 | int (*early_config) (void *pdata); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 444 | int (*config) (void *pdata); |
Channagoud Kadabi | 01c9182 | 2012-06-06 15:53:30 +0530 | [diff] [blame] | 445 | int (*rotate) (void); |
Sandeep Panda | 6c24af7 | 2015-12-23 15:36:07 +0530 | [diff] [blame] | 446 | |
| 447 | char autorefresh_enable; |
| 448 | uint32_t autorefresh_framenum; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 449 | }; |
| 450 | |
| 451 | struct msm_fb_panel_data { |
| 452 | struct msm_panel_info panel_info; |
| 453 | struct fbcon_config fb; |
| 454 | int mdp_rev; |
Channagoud Kadabi | 01c9182 | 2012-06-06 15:53:30 +0530 | [diff] [blame] | 455 | int rotate; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 456 | |
| 457 | /* function entry chain */ |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 458 | int (*power_func) (uint8_t enable, struct msm_panel_info *); |
| 459 | uint32_t (*clk_func) (uint8_t enable, struct msm_panel_info *pinfo); |
| 460 | int (*bl_func) (uint8_t enable); |
| 461 | uint32_t (*pll_clk_func) (uint8_t enable, struct msm_panel_info *); |
Huaibin Yang | 88540b3 | 2014-11-07 13:59:54 -0800 | [diff] [blame] | 462 | int (*dfps_func)(struct msm_panel_info *); |
Jayant Shekhar | e2e6b71 | 2013-11-20 16:54:20 +0530 | [diff] [blame] | 463 | int (*post_power_func)(int enable); |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 464 | int (*pre_init_func)(void); |
Casey Piper | 6c2f113 | 2015-03-24 11:37:19 -0700 | [diff] [blame] | 465 | int (*update_panel_info) (void); |
Vineet Bajaj | c227246 | 2015-05-07 17:35:03 +0530 | [diff] [blame] | 466 | int (*dsi2HDMI_config) (struct msm_panel_info *); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 467 | }; |
| 468 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 469 | #endif |