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Channagoud Kadabif8ad8e72015-01-06 15:10:13 -08001/* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
Channagoud Kadabied60a8b2014-06-27 15:35:09 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <debug.h>
30#include <platform/iomap.h>
31#include <platform/irqs.h>
32#include <platform/gpio.h>
33#include <reg.h>
34#include <target.h>
35#include <platform.h>
36#include <dload_util.h>
37#include <uart_dm.h>
38#include <mmc.h>
39#include <spmi.h>
40#include <board.h>
41#include <smem.h>
42#include <baseband.h>
Sridhar Parasuramd75ade52015-03-09 15:45:16 -070043#include <regulator.h>
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070044#include <dev/keys.h>
45#include <pm8x41.h>
46#include <crypto5_wrapper.h>
47#include <clock.h>
48#include <partition_parser.h>
49#include <scm.h>
50#include <platform/clock.h>
51#include <platform/gpio.h>
52#include <platform/timer.h>
53#include <stdlib.h>
54#include <ufs.h>
55#include <boot_device.h>
56#include <qmp_phy.h>
Channagoud Kadabi7d308202014-12-22 12:07:04 -080057#include <sdhci_msm.h>
58#include <qusb2_phy.h>
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -080059#include <rpmb.h>
Sridhar Parasuram9f28f672015-03-17 15:40:47 -070060#include <rpm-glink.h>
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070061
Channagoud Kadabi4a870cf2015-01-21 10:39:01 -080062#define CE_INSTANCE 1
63#define CE_EE 1
64#define CE_FIFO_SIZE 64
65#define CE_READ_PIPE 3
66#define CE_WRITE_PIPE 2
67#define CE_READ_PIPE_LOCK_GRP 0
68#define CE_WRITE_PIPE_LOCK_GRP 0
69#define CE_ARRAY_SIZE 20
70
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070071#define PMIC_ARB_CHANNEL_NUM 0
72#define PMIC_ARB_OWNER_ID 0
73
74static void set_sdc_power_ctrl(void);
75static uint32_t mmc_pwrctl_base[] =
76 { MSM_SDC1_BASE, MSM_SDC2_BASE };
77
78static uint32_t mmc_sdhci_base[] =
79 { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
80
81static uint32_t mmc_sdc_pwrctl_irq[] =
82 { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
83
84struct mmc_device *dev;
85struct ufs_dev ufs_device;
86
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070087void target_early_init(void)
88{
89#if WITH_DEBUG_UART
Channagoud Kadabi35503c42014-11-14 16:22:43 -080090 uart_dm_init(8, 0, BLSP2_UART1_BASE);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070091#endif
92}
93
94/* Return 1 if vol_up pressed */
Amit Blay6a3e88b2015-06-23 22:25:06 +030095int target_volume_up()
Channagoud Kadabied60a8b2014-06-27 15:35:09 -070096{
97 uint8_t status = 0;
98 struct pm8x41_gpio gpio;
99
100 /* Configure the GPIO */
101 gpio.direction = PM_GPIO_DIR_IN;
102 gpio.function = 0;
103 gpio.pull = PM_GPIO_PULL_UP_30;
104 gpio.vin_sel = 2;
105
106 pm8x41_gpio_config(2, &gpio);
107
108 /* Wait for the pmic gpio config to take effect */
109 thread_sleep(1);
110
111 /* Get status of P_GPIO_5 */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800112 pm8x41_gpio_get(2, &status);
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700113
114 return !status; /* active low */
115}
116
117/* Return 1 if vol_down pressed */
118uint32_t target_volume_down()
119{
120 return pm8x41_resin_status();
121}
122
123static void target_keystatus()
124{
125 keys_init();
126
127 if(target_volume_down())
128 keys_post_event(KEY_VOLUMEDOWN, 1);
129
130 if(target_volume_up())
131 keys_post_event(KEY_VOLUMEUP, 1);
132}
133
134void target_uninit(void)
135{
136 if (platform_boot_dev_isemmc())
137 {
138 mmc_put_card_to_sleep(dev);
139 /* Disable HC mode before jumping to kernel */
140 sdhci_mode_disable(&dev->host);
141 }
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800142
143 if (is_sec_app_loaded())
144 {
145 if (unload_sec_app() < 0)
146 {
147 dprintf(CRITICAL, "Failed to unload App for rpmb\n");
148 ASSERT(0);
149 }
150 }
151
Sridhar Parasuram9f28f672015-03-17 15:40:47 -0700152 /* Tear down glink channels */
153 rpm_glink_uninit();
154
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800155 if (rpmb_uninit() < 0)
156 {
157 dprintf(CRITICAL, "RPMB uninit failed\n");
158 ASSERT(0);
159 }
160
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700161}
162
163static void set_sdc_power_ctrl()
164{
165 /* Drive strength configs for sdc pins */
166 struct tlmm_cfgs sdc1_hdrv_cfg[] =
167 {
168 { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
169 { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
170 { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
171 };
172
173 /* Pull configs for sdc pins */
174 struct tlmm_cfgs sdc1_pull_cfg[] =
175 {
176 { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
177 { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
178 { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
179 };
180
181 struct tlmm_cfgs sdc1_rclk_cfg[] =
182 {
183 { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
184 };
185
186 /* Set the drive strength & pull control values */
187 tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
188 tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
189 tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
190}
191
192void target_sdc_init()
193{
194 struct mmc_config_data config = {0};
195
196 /* Set drive strength & pull ctrl values */
197 set_sdc_power_ctrl();
198
199 config.bus_width = DATA_BUS_WIDTH_8BIT;
200 config.max_clk_rate = MMC_CLK_192MHZ;
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800201 config.hs400_support = 1;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700202
203 /* Try slot 1*/
204 config.slot = 1;
205 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
206 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
207 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
208
209 if (!(dev = mmc_init(&config)))
210 {
211 /* Try slot 2 */
212 config.slot = 2;
213 config.max_clk_rate = MMC_CLK_200MHZ;
214 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
215 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
216 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
217
218 if (!(dev = mmc_init(&config)))
219 {
220 dprintf(CRITICAL, "mmc init failed!");
221 ASSERT(0);
222 }
223 }
224}
225
226void *target_mmc_device()
227{
228 if (platform_boot_dev_isemmc())
229 return (void *) dev;
230 else
231 return (void *) &ufs_device;
232}
233
234void target_init(void)
235{
236 dprintf(INFO, "target_init()\n");
237
238 spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
239
240 target_keystatus();
241
242 if (target_use_signed_kernel())
243 target_crypto_init_params();
244
245 platform_read_boot_config();
246
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800247#ifdef MMC_SDHCI_SUPPORT
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700248 if (platform_boot_dev_isemmc())
249 {
250 target_sdc_init();
251 }
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800252#endif
253#ifdef UFS_SUPPORT
254 if (!platform_boot_dev_isemmc())
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700255 {
256 ufs_device.base = UFS_BASE;
257 ufs_init(&ufs_device);
258 }
Sridhar Parasuram50b9d962015-02-12 11:28:09 -0800259#endif
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700260
261 /* Storage initialization is complete, read the partition table info */
Channagoud Kadabi58a273b2015-02-10 12:56:22 -0800262 mmc_read_partition_table(0);
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800263
264 if (rpmb_init() < 0)
265 {
266 dprintf(CRITICAL, "RPMB init failed\n");
267 ASSERT(0);
268 }
Sridhar Parasuram9f28f672015-03-17 15:40:47 -0700269 /* Initialize Glink */
270 rpm_glink_init();
271
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700272}
273
274unsigned board_machtype(void)
275{
276 return LINUX_MACHTYPE_UNKNOWN;
277}
278
279/* Detect the target type */
280void target_detect(struct board_data *board)
281{
282 /* This is filled from board.c */
283}
284
Dhaval Patelb95039c2015-03-16 11:14:06 -0700285static uint8_t splash_override;
286/* Returns 1 if target supports continuous splash screen. */
287int target_cont_splash_screen()
288{
289 uint8_t splash_screen = 0;
290 if(!splash_override) {
291 switch(board_hardware_id())
292 {
293 case HW_PLATFORM_SURF:
294 case HW_PLATFORM_MTP:
295 case HW_PLATFORM_FLUID:
296 dprintf(SPEW, "Target_cont_splash=1\n");
297 splash_screen = 1;
298 break;
299 default:
300 dprintf(SPEW, "Target_cont_splash=0\n");
301 splash_screen = 0;
302 }
303 }
304 return splash_screen;
305}
306
307void target_force_cont_splash_disable(uint8_t override)
308{
309 splash_override = override;
310}
311
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700312/* Detect the modem type */
313void target_baseband_detect(struct board_data *board)
314{
315 uint32_t platform;
316
317 platform = board->platform;
318
319 switch(platform) {
Channagoud Kadabi439df822015-05-26 11:14:16 -0700320 case APQ8096:
321 board->baseband = BASEBAND_APQ;
322 break;
Channagoud Kadabi4a4c05e2015-03-30 15:18:58 -0700323 case MSM8996:
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800324 if (board->platform_version == 0x10000)
325 board->baseband = BASEBAND_APQ;
326 else
327 board->baseband = BASEBAND_MSM;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700328 break;
329 default:
330 dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
331 ASSERT(0);
332 };
333}
334unsigned target_baseband()
335{
336 return board_baseband();
337}
338
339void target_serialno(unsigned char *buf)
340{
341 unsigned int serialno;
342 if (target_is_emmc_boot()) {
343 serialno = mmc_get_psn();
344 snprintf((char *)buf, 13, "%x", serialno);
345 }
346}
347
348unsigned check_reboot_mode(void)
349{
350 uint32_t restart_reason = 0;
351 uint32_t restart_reason_addr;
352
353 restart_reason_addr = RESTART_REASON_ADDR;
354
355 /* Read reboot reason and scrub it */
356 restart_reason = readl(restart_reason_addr);
357 writel(0x00, restart_reason_addr);
358
359 return restart_reason;
360}
361
362void reboot_device(unsigned reboot_reason)
363{
364 uint8_t reset_type = 0;
365
366 /* Write the reboot reason */
367 writel(reboot_reason, RESTART_REASON_ADDR);
368
369 if(reboot_reason)
370 reset_type = PON_PSHOLD_WARM_RESET;
371 else
372 reset_type = PON_PSHOLD_HARD_RESET;
373
374 pm8x41_reset_configure(reset_type);
375
376 /* Drop PS_HOLD for MSM */
377 writel(0x00, MPM2_MPM_PS_HOLD);
378
379 mdelay(5000);
380
381 dprintf(CRITICAL, "Rebooting failed\n");
382}
383
384int emmc_recovery_init(void)
385{
386 return _emmc_recovery_init();
387}
388
389void target_usb_phy_reset()
390{
391 usb30_qmp_phy_reset();
392 qusb2_phy_reset();
393}
394
395target_usb_iface_t* target_usb30_init()
396{
397 target_usb_iface_t *t_usb_iface;
398
399 t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
400 ASSERT(t_usb_iface);
401
402 t_usb_iface->phy_init = usb30_qmp_phy_init;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700403 t_usb_iface->phy_reset = target_usb_phy_reset;
404 t_usb_iface->clock_init = clock_usb30_init;
405 t_usb_iface->vbus_override = 1;
406
407 return t_usb_iface;
408}
409
410/* identify the usb controller to be used for the target */
411const char * target_usb_controller()
412{
413 return "dwc";
414}
415
416uint32_t target_override_pll()
417{
Channagoud Kadabi1e5144b2015-04-28 17:15:05 -0700418 if (board_soc_version() >= 0x20000)
419 return 0;
420 else
421 return 1;
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700422}
423
Channagoud Kadabi4a870cf2015-01-21 10:39:01 -0800424crypto_engine_type board_ce_type(void)
425{
426 return CRYPTO_ENGINE_TYPE_SW;
427}
428
429/* Set up params for h/w CE. */
430void target_crypto_init_params()
431{
432 struct crypto_init_params ce_params;
433
434 /* Set up base addresses and instance. */
435 ce_params.crypto_instance = CE_INSTANCE;
436 ce_params.crypto_base = MSM_CE_BASE;
437 ce_params.bam_base = MSM_CE_BAM_BASE;
438
439 /* Set up BAM config. */
440 ce_params.bam_ee = CE_EE;
441 ce_params.pipes.read_pipe = CE_READ_PIPE;
442 ce_params.pipes.write_pipe = CE_WRITE_PIPE;
443 ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
444 ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
445
446 /* Assign buffer sizes. */
447 ce_params.num_ce = CE_ARRAY_SIZE;
448 ce_params.read_fifo_size = CE_FIFO_SIZE;
449 ce_params.write_fifo_size = CE_FIFO_SIZE;
450
451 /* BAM is initialized by TZ for this platform.
452 * Do not do it again as the initialization address space
453 * is locked.
454 */
455 ce_params.do_bam_init = 0;
456
457 crypto_init_params(&ce_params);
458}
Channagoud Kadabi083290f2015-03-13 14:18:38 -0700459
460unsigned target_pause_for_battery_charge(void)
461{
462 uint8_t pon_reason = pm8x41_get_pon_reason();
463 uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
464 dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
465 pon_reason, is_cold_boot);
466 /* In case of fastboot reboot,adb reboot or if we see the power key
467 * pressed we do not want go into charger mode.
468 * fastboot reboot is warm boot with PON hard reset bit not set
469 * adb reboot is a cold boot with PON hard reset bit set
470 */
471 if (is_cold_boot &&
472 (!(pon_reason & HARD_RST)) &&
473 (!(pon_reason & KPDPWR_N)) &&
474 ((pon_reason & PON1)))
475 return 1;
476 else
477 return 0;
478}
Channagoud Kadabi23edc0c2015-03-27 18:31:32 -0700479
480int set_download_mode(enum dload_mode mode)
481{
482 int ret = 0;
483 ret = scm_dload_mode(mode);
484
485 return ret;
486}