Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <string.h> |
| 32 | #include <smem.h> |
| 33 | #include <err.h> |
| 34 | #include <msm_panel.h> |
| 35 | #include <mipi_dsi.h> |
| 36 | #include <pm8x41.h> |
| 37 | #include <pm8x41_wled.h> |
| 38 | #include <qpnp_wled.h> |
| 39 | #include <board.h> |
| 40 | #include <mdp5.h> |
| 41 | #include <scm.h> |
| 42 | #include <regulator.h> |
| 43 | #include <platform/clock.h> |
| 44 | #include <platform/gpio.h> |
| 45 | #include <platform/iomap.h> |
| 46 | #include <target/display.h> |
| 47 | #include <qtimer.h> |
| 48 | |
| 49 | #include "include/panel.h" |
| 50 | #include "include/display_resource.h" |
| 51 | #include "gcdb_display.h" |
| 52 | |
| 53 | /*---------------------------------------------------------------------------*/ |
| 54 | /* GPIO configuration */ |
| 55 | /*---------------------------------------------------------------------------*/ |
| 56 | static struct gpio_pin reset_gpio = { |
| 57 | "msmgpio", 0, 3, 1, 0, 1 |
| 58 | }; |
| 59 | |
| 60 | static struct gpio_pin enable_gpio = { |
| 61 | "msmgpio", 90, 3, 1, 0, 1 |
| 62 | }; |
| 63 | |
| 64 | static struct gpio_pin bkl_gpio = { |
| 65 | "msmgpio", 91, 3, 1, 0, 1 |
| 66 | }; |
| 67 | |
| 68 | #define VCO_DELAY_USEC 1000 |
| 69 | #define GPIO_STATE_LOW 0 |
| 70 | #define GPIO_STATE_HIGH 2 |
| 71 | #define RESET_GPIO_SEQ_LEN 3 |
| 72 | #define PMIC_WLED_SLAVE_ID 3 |
| 73 | |
| 74 | static void mdss_dsi_uniphy_pll_sw_reset_8952(uint32_t pll_base) |
| 75 | { |
| 76 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 77 | mdelay(1); |
| 78 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
| 79 | mdelay(1); |
| 80 | } |
| 81 | |
| 82 | static void dsi_pll_toggle_lock_detect_8952(uint32_t pll_base) |
| 83 | { |
| 84 | writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 85 | udelay(1); |
| 86 | writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 87 | udelay(512); |
| 88 | } |
| 89 | |
| 90 | static void dsi_pll_sw_reset_8952(uint32_t pll_base) |
| 91 | { |
| 92 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 93 | udelay(1); |
| 94 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
Padmanabhan Komanduru | 6cf6352 | 2015-06-08 14:48:00 +0530 | [diff] [blame^] | 95 | udelay(1); |
| 96 | } |
| 97 | |
| 98 | static uint32_t dsi_pll_lock_status_8956(uint32_t pll_base) |
| 99 | { |
| 100 | uint32_t counter, status; |
| 101 | |
| 102 | status = readl(pll_base + 0x00c0) & 0x01; |
| 103 | for (counter = 0; counter < 5 && !status; counter++) { |
| 104 | udelay(100); |
| 105 | status = readl(pll_base + 0x00c0) & 0x01; |
| 106 | } |
| 107 | |
| 108 | return status; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | static uint32_t gf_1_dsi_pll_enable_sequence_8952(uint32_t pll_base) |
| 112 | { |
| 113 | uint32_t rc; |
| 114 | |
| 115 | dsi_pll_sw_reset_8952(pll_base); |
| 116 | |
| 117 | /* |
| 118 | * Add hardware recommended delays between register writes for |
| 119 | * the updates to take effect. These delays are necessary for the |
| 120 | * PLL to successfully lock |
| 121 | */ |
| 122 | writel(0x14, pll_base + 0x0070); /* CAL CFG1*/ |
| 123 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 124 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 125 | udelay(3); |
| 126 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 127 | udelay(500); |
| 128 | |
| 129 | dsi_pll_toggle_lock_detect_8952(pll_base); |
| 130 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 131 | |
| 132 | return rc; |
| 133 | } |
| 134 | |
| 135 | static uint32_t gf_2_dsi_pll_enable_sequence_8952(uint32_t pll_base) |
| 136 | { |
| 137 | uint32_t rc; |
| 138 | |
| 139 | dsi_pll_sw_reset_8952(pll_base); |
| 140 | |
| 141 | /* |
| 142 | * Add hardware recommended delays between register writes for |
| 143 | * the updates to take effect. These delays are necessary for the |
| 144 | * PLL to successfully lock |
| 145 | */ |
| 146 | writel(0x04, pll_base + 0x0070); /* CAL CFG1*/ |
| 147 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 148 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 149 | udelay(3); |
| 150 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 151 | udelay(500); |
| 152 | |
| 153 | dsi_pll_toggle_lock_detect_8952(pll_base); |
| 154 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 155 | |
| 156 | return rc; |
| 157 | } |
| 158 | |
| 159 | static uint32_t tsmc_dsi_pll_enable_sequence_8952(uint32_t pll_base) |
| 160 | { |
| 161 | uint32_t rc; |
| 162 | |
| 163 | dsi_pll_sw_reset_8952(pll_base); |
| 164 | /* |
| 165 | * Add hardware recommended delays between register writes for |
| 166 | * the updates to take effect. These delays are necessary for the |
| 167 | * PLL to successfully lock |
| 168 | */ |
| 169 | |
| 170 | writel(0x34, pll_base + 0x0070); /* CAL CFG1*/ |
| 171 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 172 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 173 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 174 | udelay(500); |
| 175 | |
| 176 | dsi_pll_toggle_lock_detect_8952(pll_base); |
| 177 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 178 | |
| 179 | return rc; |
| 180 | } |
| 181 | |
| 182 | |
| 183 | static uint32_t dsi_pll_enable_seq_8952(uint32_t pll_base) |
| 184 | { |
| 185 | uint32_t pll_locked = 0; |
| 186 | uint32_t counter = 0; |
| 187 | |
| 188 | do { |
| 189 | pll_locked = tsmc_dsi_pll_enable_sequence_8952(pll_base); |
| 190 | |
| 191 | dprintf(SPEW, "TSMC pll locked status is %d\n", pll_locked); |
| 192 | ++counter; |
| 193 | } while (!pll_locked && (counter < 3)); |
| 194 | |
| 195 | if(!pll_locked) { |
| 196 | counter = 0; |
| 197 | do { |
| 198 | pll_locked = gf_1_dsi_pll_enable_sequence_8952(pll_base); |
| 199 | |
| 200 | dprintf(SPEW, "GF P1 pll locked status is %d\n", pll_locked); |
| 201 | ++counter; |
| 202 | } while (!pll_locked && (counter < 3)); |
| 203 | } |
| 204 | |
| 205 | if(!pll_locked) { |
| 206 | counter = 0; |
| 207 | do { |
| 208 | pll_locked = gf_2_dsi_pll_enable_sequence_8952(pll_base); |
| 209 | |
| 210 | dprintf(SPEW, "GF P2 pll locked status is %d\n", pll_locked); |
| 211 | ++counter; |
| 212 | } while (!pll_locked && (counter < 3)); |
| 213 | } |
| 214 | |
| 215 | return pll_locked; |
| 216 | } |
| 217 | |
Padmanabhan Komanduru | 6cf6352 | 2015-06-08 14:48:00 +0530 | [diff] [blame^] | 218 | static uint32_t dsi_pll_enable_seq_8956(uint32_t pll_base) |
| 219 | { |
| 220 | /* |
| 221 | * PLL power up sequence |
| 222 | * Add necessary delays recommended by h/w team |
| 223 | */ |
| 224 | |
| 225 | /* Lock Detect setting */ |
| 226 | writel(0x0d, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 227 | writel(0x34, pll_base + 0x0070); /* PLL CAL_CFG1 */ |
| 228 | writel(0x10, pll_base + 0x005c); /* LKDetect CFG0 */ |
| 229 | writel(0x1a, pll_base + 0x0060); /* LKDetect CFG1 */ |
| 230 | |
| 231 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 232 | udelay(300); |
| 233 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 234 | udelay(300); |
| 235 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 236 | udelay(300); |
| 237 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
| 238 | udelay(300); |
| 239 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 240 | udelay(1000); |
| 241 | |
| 242 | return dsi_pll_lock_status_8956(pll_base); |
| 243 | } |
| 244 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 245 | static int msm8952_wled_backlight_ctrl(uint8_t enable) |
| 246 | { |
| 247 | uint8_t slave_id = PMIC_WLED_SLAVE_ID; /* pmi */ |
| 248 | |
| 249 | pm8x41_wled_config_slave_id(slave_id); |
| 250 | qpnp_wled_enable_backlight(enable); |
| 251 | qpnp_ibb_enable(enable); |
| 252 | return NO_ERROR; |
| 253 | } |
| 254 | |
| 255 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
| 256 | { |
| 257 | uint32_t ret = NO_ERROR; |
| 258 | |
| 259 | if (bl->bl_interface_type == BL_DCS) |
| 260 | return ret; |
| 261 | |
| 262 | ret = msm8952_wled_backlight_ctrl(enable); |
| 263 | |
| 264 | return ret; |
| 265 | } |
| 266 | |
| 267 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 268 | { |
| 269 | int32_t ret = 0; |
| 270 | struct mdss_dsi_pll_config *pll_data; |
| 271 | dprintf(SPEW, "target_panel_clock\n"); |
| 272 | |
| 273 | pll_data = pinfo->mipi.dsi_pll_config; |
| 274 | pll_data->vco_delay = VCO_DELAY_USEC; |
| 275 | |
| 276 | if (enable) { |
| 277 | mdp_gdsc_ctrl(enable); |
| 278 | mdss_bus_clocks_enable(); |
| 279 | mdp_clock_enable(); |
| 280 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 281 | if (ret) { |
| 282 | dprintf(CRITICAL, |
| 283 | "%s: Failed to restore MDP security configs", |
| 284 | __func__); |
| 285 | mdp_clock_disable(); |
| 286 | mdss_bus_clocks_disable(); |
| 287 | mdp_gdsc_ctrl(0); |
| 288 | return ret; |
| 289 | } |
Padmanabhan Komanduru | 6cf6352 | 2015-06-08 14:48:00 +0530 | [diff] [blame^] | 290 | if (!platform_is_msm8956()) |
| 291 | mdss_dsi_uniphy_pll_sw_reset_8952(pinfo->mipi.pll_base); |
| 292 | else |
| 293 | dsi_pll_sw_reset_8952(pinfo->mipi.pll_base); |
Padmanabhan Komanduru | c0766c8 | 2015-04-27 16:39:15 -0700 | [diff] [blame] | 294 | mdss_dsi_auto_pll_config(pinfo->mipi.pll_base, |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 295 | pinfo->mipi.ctl_base, pll_data); |
Padmanabhan Komanduru | 6cf6352 | 2015-06-08 14:48:00 +0530 | [diff] [blame^] | 296 | if (platform_is_msm8956()) |
| 297 | ret = dsi_pll_enable_seq_8956(pinfo->mipi.pll_base); |
| 298 | else |
| 299 | ret = dsi_pll_enable_seq_8952(pinfo->mipi.pll_base); |
| 300 | if (!ret) |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 301 | dprintf(CRITICAL, "Not able to enable the pll\n"); |
| 302 | gcc_dsi_clocks_enable(pll_data->pclk_m, pll_data->pclk_n, |
| 303 | pll_data->pclk_d); |
| 304 | } else if(!target_cont_splash_screen()) { |
| 305 | gcc_dsi_clocks_disable(); |
| 306 | mdp_clock_disable(); |
| 307 | mdss_bus_clocks_disable(); |
| 308 | mdp_gdsc_ctrl(enable); |
| 309 | } |
| 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 315 | struct msm_panel_info *pinfo) |
| 316 | { |
| 317 | int ret = NO_ERROR; |
| 318 | |
| 319 | if (enable) { |
| 320 | if (pinfo->mipi.use_enable_gpio) { |
| 321 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 322 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 323 | enable_gpio.pin_strength, |
| 324 | enable_gpio.pin_state); |
| 325 | |
| 326 | gpio_set_dir(enable_gpio.pin_id, 2); |
| 327 | } |
| 328 | |
| 329 | gpio_tlmm_config(bkl_gpio.pin_id, 0, |
| 330 | bkl_gpio.pin_direction, bkl_gpio.pin_pull, |
| 331 | bkl_gpio.pin_strength, bkl_gpio.pin_state); |
| 332 | |
| 333 | gpio_set_dir(bkl_gpio.pin_id, 2); |
| 334 | |
| 335 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 336 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 337 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 338 | |
| 339 | gpio_set_dir(reset_gpio.pin_id, 2); |
| 340 | |
| 341 | /* reset */ |
| 342 | for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 343 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
| 344 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_LOW); |
| 345 | else |
| 346 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 347 | mdelay(resetseq->sleep[i]); |
| 348 | } |
| 349 | } else if(!target_cont_splash_screen()) { |
| 350 | gpio_set_dir(reset_gpio.pin_id, 0); |
| 351 | if (pinfo->mipi.use_enable_gpio) |
| 352 | gpio_set_dir(enable_gpio.pin_id, 0); |
| 353 | } |
| 354 | |
| 355 | return ret; |
| 356 | } |
| 357 | |
| 358 | static void wled_init(struct msm_panel_info *pinfo) |
| 359 | { |
| 360 | struct qpnp_wled_config_data config = {0}; |
| 361 | struct labibb_desc *labibb; |
| 362 | int display_type = 0; |
| 363 | |
| 364 | labibb = pinfo->labibb; |
| 365 | |
| 366 | if (labibb) |
| 367 | display_type = labibb->amoled_panel; |
| 368 | |
| 369 | config.display_type = display_type; |
| 370 | config.lab_init_volt = 4600000; /* fixed, see pmi register */ |
| 371 | config.ibb_init_volt = 1400000; /* fixed, see pmi register */ |
| 372 | |
| 373 | if (labibb && labibb->force_config) { |
| 374 | config.lab_min_volt = labibb->lab_min_volt; |
| 375 | config.lab_max_volt = labibb->lab_max_volt; |
| 376 | config.ibb_min_volt = labibb->ibb_min_volt; |
| 377 | config.ibb_max_volt = labibb->ibb_max_volt; |
| 378 | config.pwr_up_delay = labibb->pwr_up_delay; |
| 379 | config.pwr_down_delay = labibb->pwr_down_delay; |
| 380 | config.ibb_discharge_en = labibb->ibb_discharge_en; |
| 381 | } else { |
| 382 | /* default */ |
| 383 | config.pwr_up_delay = 3; |
| 384 | config.pwr_down_delay = 3; |
| 385 | config.ibb_discharge_en = 1; |
| 386 | if (display_type) { /* amoled */ |
| 387 | config.lab_min_volt = 4600000; |
| 388 | config.lab_max_volt = 4600000; |
| 389 | config.ibb_min_volt = 4000000; |
| 390 | config.ibb_max_volt = 4000000; |
| 391 | } else { /* lcd */ |
| 392 | config.lab_min_volt = 5500000; |
| 393 | config.lab_max_volt = 5500000; |
| 394 | config.ibb_min_volt = 5500000; |
| 395 | config.ibb_max_volt = 5500000; |
| 396 | } |
| 397 | } |
| 398 | |
| 399 | dprintf(SPEW, "%s: %d %d %d %d %d %d %d %d %d %d\n", __func__, |
| 400 | config.display_type, |
| 401 | config.lab_min_volt, config.lab_max_volt, |
| 402 | config.ibb_min_volt, config.ibb_max_volt, |
| 403 | config.lab_init_volt, config.ibb_init_volt, |
| 404 | config.pwr_up_delay, config.pwr_down_delay, |
| 405 | config.ibb_discharge_en); |
| 406 | |
| 407 | /* QPNP WLED init for display backlight */ |
| 408 | pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID); |
| 409 | |
| 410 | qpnp_wled_init(&config); |
| 411 | } |
| 412 | |
Dhaval Patel | 7709c41 | 2015-05-12 10:09:41 -0700 | [diff] [blame] | 413 | int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db) |
| 414 | { |
| 415 | memcpy(phy_db->regulator, panel_regulator_settings, REGULATOR_SIZE); |
| 416 | memcpy(phy_db->ctrl, panel_physical_ctrl, PHYSICAL_SIZE); |
| 417 | memcpy(phy_db->strength, panel_strength_ctrl, STRENGTH_SIZE); |
| 418 | memcpy(phy_db->bistCtrl, panel_bist_ctrl, BIST_SIZE); |
| 419 | memcpy(phy_db->laneCfg, panel_lane_config, LANE_SIZE); |
| 420 | return NO_ERROR; |
| 421 | } |
| 422 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 423 | int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo) |
| 424 | { |
| 425 | |
| 426 | if (enable) { |
| 427 | regulator_enable(REG_LDO2 | REG_LDO6 | REG_LDO17); |
| 428 | mdelay(10); |
| 429 | wled_init(pinfo); |
| 430 | qpnp_ibb_enable(true); /*5V boost*/ |
| 431 | mdelay(50); |
| 432 | } else { |
| 433 | regulator_disable(REG_LDO2 | REG_LDO6 | REG_LDO17); |
| 434 | } |
| 435 | |
| 436 | return NO_ERROR; |
| 437 | } |
| 438 | |
| 439 | bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size) |
| 440 | { |
| 441 | return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size); |
| 442 | } |
| 443 | |
| 444 | void target_display_init(const char *panel_name) |
| 445 | { |
| 446 | char cont_splash = '\0'; |
| 447 | |
| 448 | set_panel_cmd_string(panel_name, &cont_splash); |
| 449 | panel_name += strspn(panel_name, " "); |
| 450 | |
| 451 | if (!strcmp(panel_name, NO_PANEL_CONFIG) |
| 452 | || !strcmp(panel_name, SIM_VIDEO_PANEL) |
| 453 | || !strcmp(panel_name, SIM_CMD_PANEL)) { |
| 454 | dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n", |
| 455 | panel_name); |
| 456 | return; |
| 457 | } |
| 458 | |
| 459 | if (gcdb_display_init(panel_name, MDP_REV_50, (void *)MIPI_FB_ADDR)) { |
| 460 | target_force_cont_splash_disable(true); |
| 461 | msm_display_off(); |
| 462 | } |
| 463 | |
| 464 | if (cont_splash == '0') { |
| 465 | dprintf(INFO, "Forcing continuous splash disable\n"); |
| 466 | target_force_cont_splash_disable(true); |
| 467 | } |
| 468 | } |
| 469 | |
| 470 | void target_display_shutdown(void) |
| 471 | { |
| 472 | gcdb_display_shutdown(); |
| 473 | } |