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Dhaval Patelb95039c2015-03-16 11:14:06 -07001/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions
5 * are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in
10 * the documentation and/or other materials provided with the
11 * distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
19 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
20 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
23 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <debug.h>
31#include <string.h>
32#include <smem.h>
33#include <err.h>
34#include <msm_panel.h>
35#include <mipi_dsi.h>
36#include <pm8x41.h>
37#include <pm8x41_wled.h>
38#include <qpnp_wled.h>
39#include <board.h>
40#include <mdp5.h>
41#include <endian.h>
42#include <regulator.h>
43#include <qtimer.h>
44#include <arch/defines.h>
45#include <platform/gpio.h>
46#include <platform/clock.h>
47#include <platform/iomap.h>
48#include <target/display.h>
49#include <mipi_dsi_autopll_thulium.h>
50
51#include "include/panel.h"
52#include "include/display_resource.h"
53#include "gcdb_display.h"
54
55#define GPIO_STATE_LOW 0
56#define GPIO_STATE_HIGH 2
57#define RESET_GPIO_SEQ_LEN 3
58
59#define PWM_DUTY_US 13
60#define PWM_PERIOD_US 27
61#define PMIC_WLED_SLAVE_ID 3
62#define PMIC_MPP_SLAVE_ID 2
63
64#define MAX_POLL_READS 15
65#define POLL_TIMEOUT_US 1000
66
67#define STRENGTH_SIZE_IN_BYTES_8996 10
68#define REGULATOR_SIZE_IN_BYTES_8996 5
69#define LANE_SIZE_IN_BYTES_8996 20
70
71/*---------------------------------------------------------------------------*/
72/* GPIO configuration */
73/*---------------------------------------------------------------------------*/
74static struct gpio_pin reset_gpio = {
75 "msmgpio", 8, 3, 1, 0, 1
76};
77
78static struct gpio_pin lcd_reg_en = { /* boost regulator */
79 "pmi8994_gpios", 8, 3, 1, 0, 1
80};
81
82static struct gpio_pin bklt_gpio = { /* lcd_bklt_reg_en */
83 "pm8994_gpios", 14, 3, 1, 0, 1
84};
85
86static uint32_t thulium_dsi_pll_lock_status(uint32_t pll_base, uint32_t off,
87 uint32_t bit)
88{
89 uint32_t cnt, status;
90
91 /* check pll lock first */
92 for (cnt = 0; cnt < MAX_POLL_READS; cnt++) {
93 status = readl(pll_base + off);
94 dprintf(SPEW, "%s: pll_base=%x cnt=%d status=%x\n",
95 __func__, pll_base, cnt, status);
96 status &= BIT(bit); /* bit 5 */
97 if (status)
98 break;
99 udelay(POLL_TIMEOUT_US);
100 }
101
102 return status;
103}
104
105static uint32_t thulium_dsi_pll_enable_seq(uint32_t phy_base, uint32_t pll_base)
106{
107 uint32_t pll_locked;
108
109 writel(0x01, phy_base + 0x48);
110 dmb();
111
112 pll_locked = thulium_dsi_pll_lock_status(pll_base, 0xcc, 5);
113 if (pll_locked)
114 pll_locked = thulium_dsi_pll_lock_status(pll_base, 0xcc, 0);
115
116 if (!pll_locked)
117 dprintf(ERROR, "%s: DSI PLL lock failed\n", __func__);
118 else
119 dprintf(SPEW, "%s: DSI PLL lock Success\n", __func__);
120
121 return pll_locked;
122}
123
124static int thulium_wled_backlight_ctrl(uint8_t enable)
125{
126 qpnp_wled_enable_backlight(enable);
Dhaval Patelb95039c2015-03-16 11:14:06 -0700127 return NO_ERROR;
128}
129
130static int thulium_pwm_backlight_ctrl(uint8_t enable)
131{
132 uint8_t slave_id = 3; /* lpg at pmi */
133
134 if (enable) {
135 /* lpg channel 4 */
136
137 /* LPG_ENABLE_CONTROL */
138 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0x0);
139 mdelay(100);
140
141 /* LPG_VALUE_LSB, duty cycle = 0x80/0x200 = 1/4 */
142 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x44, 0x80);
143 /* LPG_VALUE_MSB */
144 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x45, 0x00);
145 /* LPG_PWM_SYNC */
146 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x47, 0x01);
147
148 /* LPG_PWM_SIZE_CLK, */
149 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x41, 0x13);
150 /* LPG_PWM_FREQ_PREDIV */
151 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x42, 0x02);
152 /* LPG_PWM_TYPE_CONFIG */
153 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x43, 0x20);
154 /* LPG_ENABLE_CONTROL */
155 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0x04);
156
157 /* SEC_ACCESS */
158 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0xD0, 0xA5);
159 /* DTEST4, OUT_HI */
160 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0xE5, 0x01);
161 /* LPG_ENABLE_CONTROL */
162 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0xA4);
163 } else {
164 /* LPG_ENABLE_CONTROL */
165 pm8x41_lpg_write_sid(slave_id, PWM_BL_LPG_CHAN_ID, 0x46, 0x0);
166 }
167
168 return NO_ERROR;
169}
170
171static void lcd_reg_enable(void)
172{
173 uint8_t slave_id = 2; /* gpio at pmi */
174
175 struct pm8x41_gpio gpio = {
176 .direction = PM_GPIO_DIR_OUT,
177 .function = PM_GPIO_FUNC_HIGH,
178 .vin_sel = 2, /* VIN_2 */
179 .output_buffer = PM_GPIO_OUT_CMOS,
180 .out_strength = PM_GPIO_OUT_DRIVE_MED,
181 };
182
183 pm8x41_gpio_config_sid(slave_id, lcd_reg_en.pin_id, &gpio);
184 pm8x41_gpio_set_sid(slave_id, lcd_reg_en.pin_id, 1);
185}
186
187static void lcd_reg_disable(void)
188{
189 uint8_t slave_id = 2; /* gpio at pmi */
190
191 pm8x41_gpio_set_sid(slave_id, lcd_reg_en.pin_id, 0);
192}
193
194static void lcd_bklt_reg_enable(void)
195{
196 struct pm8x41_gpio gpio = {
197 .direction = PM_GPIO_DIR_OUT,
198 .function = PM_GPIO_FUNC_HIGH,
199 .vin_sel = 2, /* VIN_2 */
200 .output_buffer = PM_GPIO_OUT_CMOS,
201 .out_strength = PM_GPIO_OUT_DRIVE_LOW,
202 };
203
204 pm8x41_gpio_config(bklt_gpio.pin_id, &gpio);
205 pm8x41_gpio_set(bklt_gpio.pin_id, 1);
206}
207
208static void lcd_bklt_reg_disable(void)
209{
210 pm8x41_gpio_set(bklt_gpio.pin_id, 0);
211}
212
213int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
214{
215 uint32_t ret = NO_ERROR;
216 struct pm8x41_mpp mpp;
217 int rc;
218
219 if (!bl) {
220 dprintf(CRITICAL, "backlight structure is not available\n");
221 return ERR_INVALID_ARGS;
222 }
223
224 switch (bl->bl_interface_type) {
225 case BL_WLED:
226 /* Enable MPP4 */
227 pmi8994_config_mpp_slave_id(PMIC_MPP_SLAVE_ID);
228 mpp.base = PM8x41_MMP4_BASE;
229 mpp.vin = MPP_VIN2;
230 if (enable) {
231 pm_pwm_enable(false);
232 rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
233 if (rc < 0) {
234 mpp.mode = MPP_HIGH;
235 } else {
236 mpp.mode = MPP_DTEST1;
237 pm_pwm_enable(true);
238 }
239 pm8x41_config_output_mpp(&mpp);
240 pm8x41_enable_mpp(&mpp, MPP_ENABLE);
241 } else {
242 pm_pwm_enable(false);
243 pm8x41_enable_mpp(&mpp, MPP_DISABLE);
244 }
Dhaval Patelb95039c2015-03-16 11:14:06 -0700245 /* Enable WLED backlight control */
246 ret = thulium_wled_backlight_ctrl(enable);
247 break;
248 case BL_PWM:
249 /* Enable MPP1 */
250 pmi8994_config_mpp_slave_id(PMIC_MPP_SLAVE_ID);
251 mpp.base = PM8x41_MMP1_BASE;
252 mpp.vin = MPP_VIN2;
253 mpp.mode = MPP_DTEST4;
254 if (enable) {
255 pm8x41_config_output_mpp(&mpp);
256 pm8x41_enable_mpp(&mpp, MPP_ENABLE);
257 } else {
258 pm8x41_enable_mpp(&mpp, MPP_DISABLE);
259 }
Dhaval Patelb95039c2015-03-16 11:14:06 -0700260 ret = thulium_pwm_backlight_ctrl(enable);
261 break;
262 default:
263 dprintf(CRITICAL, "backlight type:%d not supported\n",
264 bl->bl_interface_type);
265 return ERR_NOT_SUPPORTED;
266 }
267
268 return ret;
269}
270
271int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
272{
Aravind Venkateswaran9586be62015-05-20 00:51:06 -0700273 uint32_t flags, dsi_phy_pll_out;
Dhaval Patelb95039c2015-03-16 11:14:06 -0700274 uint32_t ret = NO_ERROR;
275 uint32_t board_version = board_soc_version();
276
277 if (pinfo->dest == DISPLAY_2) {
278 flags = MMSS_DSI_CLKS_FLAG_DSI1;
279 if (pinfo->mipi.dual_dsi)
280 flags |= MMSS_DSI_CLKS_FLAG_DSI0;
281 } else {
282 flags = MMSS_DSI_CLKS_FLAG_DSI0;
283 if (pinfo->mipi.dual_dsi)
284 flags |= MMSS_DSI_CLKS_FLAG_DSI1;
285 }
286
287 if (!enable) {
288 /* stop pll */
289 writel(0x0, pinfo->mipi.phy_base + 0x48);
290 dmb();
291
292 mmss_dsi_clock_disable(flags);
293 goto clks_disable;
294 }
295
296 if (board_version == 0x20000 || board_version == 0x20001)
297 video_gdsc_enable();
298 mmss_gdsc_enable();
299 mmss_bus_clock_enable();
300 mdp_clock_enable();
301 mdss_dsi_auto_pll_thulium_config(pinfo);
302
303 if (!thulium_dsi_pll_enable_seq(pinfo->mipi.phy_base,
304 pinfo->mipi.pll_base)) {
305 ret = ERROR;
306 dprintf(CRITICAL, "PLL failed to lock!\n");
307 goto clks_disable;
308 }
Aravind Venkateswaran9586be62015-05-20 00:51:06 -0700309
310 if (pinfo->mipi.use_dsi1_pll)
311 dsi_phy_pll_out = DSI1_PHY_PLL_OUT;
312 else
313 dsi_phy_pll_out = DSI0_PHY_PLL_OUT;
314 mmss_dsi_clock_enable(dsi_phy_pll_out, flags);
315
Dhaval Patelb95039c2015-03-16 11:14:06 -0700316 return NO_ERROR;
317
318clks_disable:
319 mdp_clock_disable();
320 mmss_bus_clock_disable();
321 mmss_gdsc_disable();
322 if (board_version == 0x20000 || board_version == 0x20001)
323 video_gdsc_disable();
324
325 return ret;
326}
327
328int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
329 struct msm_panel_info *pinfo)
330{
331 uint32_t i = 0;
332
333 if (enable) {
334 gpio_tlmm_config(reset_gpio.pin_id, 0,
335 reset_gpio.pin_direction, reset_gpio.pin_pull,
336 reset_gpio.pin_strength, reset_gpio.pin_state);
337 /* reset */
338 for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
339 if (resetseq->pin_state[i] == GPIO_STATE_LOW)
340 gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
341 else
342 gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
343 mdelay(resetseq->sleep[i]);
344 }
345 lcd_bklt_reg_enable();
346 } else {
347 lcd_bklt_reg_disable();
348 gpio_set(reset_gpio.pin_id, 0);
349 }
350
351 return NO_ERROR;
352}
353
354static void wled_init(struct msm_panel_info *pinfo)
355{
356 struct qpnp_wled_config_data config = {0};
357 struct labibb_desc *labibb;
358 int display_type = 0;
359
360 labibb = pinfo->labibb;
361
362 if (labibb)
363 display_type = labibb->amoled_panel;
364
365 config.display_type = display_type;
366 config.lab_init_volt = 4600000; /* fixed, see pmi register */
367 config.ibb_init_volt = 1400000; /* fixed, see pmi register */
368
369 if (labibb && labibb->force_config) {
370 config.lab_min_volt = labibb->lab_min_volt;
371 config.lab_max_volt = labibb->lab_max_volt;
372 config.ibb_min_volt = labibb->ibb_min_volt;
373 config.ibb_max_volt = labibb->ibb_max_volt;
374 config.pwr_up_delay = labibb->pwr_up_delay;
375 config.pwr_down_delay = labibb->pwr_down_delay;
376 config.ibb_discharge_en = labibb->ibb_discharge_en;
377 } else {
378 /* default */
379 config.pwr_up_delay = 3;
380 config.pwr_down_delay = 3;
381 config.ibb_discharge_en = 1;
382 if (display_type) { /* amoled */
383 config.lab_min_volt = 4600000;
384 config.lab_max_volt = 4600000;
385 config.ibb_min_volt = 4000000;
386 config.ibb_max_volt = 4000000;
387 } else { /* lcd */
388 config.lab_min_volt = 5500000;
389 config.lab_max_volt = 5500000;
390 config.ibb_min_volt = 5500000;
391 config.ibb_max_volt = 5500000;
392 }
393 }
394
395 dprintf(SPEW, "%s: %d %d %d %d %d %d %d %d %d %d\n", __func__,
396 config.display_type,
397 config.lab_min_volt, config.lab_max_volt,
398 config.ibb_min_volt, config.ibb_max_volt,
399 config.lab_init_volt, config.ibb_init_volt,
400 config.pwr_up_delay, config.pwr_down_delay,
401 config.ibb_discharge_en);
402
403
404 /* QPNP WLED init for display backlight */
405 pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID);
406
407 qpnp_wled_init(&config);
408}
409
410int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
411{
412 uint32_t val = BIT(1) | BIT(13) | BIT(27);
413
414 if (enable) {
415 regulator_enable(val);
416 mdelay(10);
417 wled_init(pinfo);
418 qpnp_ibb_enable(true); /* +5V and -5V */
Dhaval Patel77d06852015-08-04 11:00:01 -0700419 mdelay(20);
Dhaval Patelb95039c2015-03-16 11:14:06 -0700420
421 if (pinfo->lcd_reg_en)
422 lcd_reg_enable();
423 } else {
424 if (pinfo->lcd_reg_en)
425 lcd_reg_disable();
426
427 regulator_disable(val);
428 }
429
430 return NO_ERROR;
431}
432
433int target_display_pre_on()
434{
435 writel(0xC0000CCC, MDP_CLK_CTRL0);
436 writel(0xC0000CCC, MDP_CLK_CTRL1);
437 writel(0x00CCCCCC, MDP_CLK_CTRL2);
438 writel(0x000000CC, MDP_CLK_CTRL6);
439 writel(0x0CCCC0C0, MDP_CLK_CTRL3);
440 writel(0xCCCCC0C0, MDP_CLK_CTRL4);
441 writel(0xCCCCC0C0, MDP_CLK_CTRL5);
442 writel(0x00CCC000, MDP_CLK_CTRL7);
443
444 return NO_ERROR;
445}
446
447int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db)
448{
449 memcpy(phy_db->strength, panel_strength_ctrl, STRENGTH_SIZE_IN_BYTES_8996 *
450 sizeof(uint32_t));
451 memcpy(phy_db->regulator, panel_regulator_settings,
452 REGULATOR_SIZE_IN_BYTES_8996 * sizeof(uint32_t));
453 memcpy(phy_db->laneCfg, panel_lane_config, LANE_SIZE_IN_BYTES_8996);
454 return NO_ERROR;
455}
456
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530457bool target_display_panel_node(char *pbuf, uint16_t buf_size)
Dhaval Patelb95039c2015-03-16 11:14:06 -0700458{
459 int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
460 bool ret = true;
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530461 struct oem_panel_data oem = mdss_dsi_get_oem_data();
Dhaval Patelb95039c2015-03-16 11:14:06 -0700462
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530463 if (!strcmp(oem.panel, HDMI_PANEL_NAME)) {
Dhaval Patelb95039c2015-03-16 11:14:06 -0700464 if (buf_size < (prefix_string_len + LK_OVERRIDE_PANEL_LEN +
465 strlen(HDMI_CONTROLLER_STRING))) {
466 dprintf(CRITICAL, "command line argument is greater than buffer size\n");
467 return false;
468 }
469
470 strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
471 buf_size -= prefix_string_len;
472 strlcat(pbuf, LK_OVERRIDE_PANEL, buf_size);
473 buf_size -= LK_OVERRIDE_PANEL_LEN;
474 strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
475 } else {
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530476 ret = gcdb_display_cmdline_arg(pbuf, buf_size);
Dhaval Patelb95039c2015-03-16 11:14:06 -0700477 }
478
479 return ret;
480}
481
482void target_display_init(const char *panel_name)
483{
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530484 struct oem_panel_data oem;
Dhaval Patelb95039c2015-03-16 11:14:06 -0700485
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530486 set_panel_cmd_string(panel_name);
487 oem = mdss_dsi_get_oem_data();
488 if (!strcmp(oem.panel, NO_PANEL_CONFIG)
489 || !strcmp(oem.panel, SIM_VIDEO_PANEL)
490 || !strcmp(oem.panel, SIM_DUALDSI_VIDEO_PANEL)
491 || !strcmp(oem.panel, SIM_CMD_PANEL)
492 || !strcmp(oem.panel, SIM_DUALDSI_CMD_PANEL)
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530493 || oem.skip) {
Dhaval Patelb95039c2015-03-16 11:14:06 -0700494 dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530495 oem.panel);
Dhaval Patelb95039c2015-03-16 11:14:06 -0700496 return;
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530497 } else if (!strcmp(oem.panel, HDMI_PANEL_NAME)) {
Dhaval Patelb95039c2015-03-16 11:14:06 -0700498 return;
499 }
500
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530501 if (gcdb_display_init(oem.panel, MDP_REV_50, (void *)MIPI_FB_ADDR)) {
Dhaval Patelb95039c2015-03-16 11:14:06 -0700502 target_force_cont_splash_disable(true);
503 msm_display_off();
504 }
505
Padmanabhan Komandurubccbcdc2015-06-30 16:19:24 +0530506 if (!oem.cont_splash) {
Dhaval Patelb95039c2015-03-16 11:14:06 -0700507 dprintf(INFO, "Forcing continuous splash disable\n");
508 target_force_cont_splash_disable(true);
509 }
510}
511
512void target_display_shutdown(void)
513{
514 gcdb_display_shutdown();
515}