| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _PLATFORM_MSMTITANIUM_IOMAP_H_ |
| 30 | #define _PLATFORM_MSMTITANIUM_IOMAP_H_ |
| 31 | |
| 32 | #define MSM_IOMAP_BASE 0x00000000 |
| 33 | #define MSM_IOMAP_END 0x08000000 |
| 34 | |
| 35 | #define SDRAM_START_ADDR 0x80000000 |
| 36 | |
| 37 | #define MSM_SHARED_BASE 0x86300000 |
| 38 | #define MSM_SHARED_IMEM_BASE 0x08600000 |
| 39 | |
| 40 | #define BS_INFO_OFFSET (0x6B0) |
| 41 | #define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET) |
| 42 | |
| 43 | #define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C) |
| 44 | |
| 45 | #define APPS_SS_BASE 0x0B000000 |
| P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 46 | #define APPS_SS_END 0x0B200000 |
| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 47 | |
| 48 | #define MSM_GIC_DIST_BASE APPS_SS_BASE |
| 49 | #define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000) |
| 50 | #define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000) |
| 51 | #define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000) |
| 52 | #define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE |
| 53 | #define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00111008) |
| 54 | |
| 55 | #define PERIPH_SS_BASE 0x07800000 |
| 56 | |
| 57 | #define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000) |
| 58 | #define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000) |
| 59 | |
| 60 | #define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000) |
| 61 | #define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000) |
| 62 | #define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000) |
| 63 | |
| 64 | #define CLK_CTL_BASE 0x1800000 |
| 65 | |
| 66 | #define SPMI_BASE 0x02000000 |
| 67 | #define SPMI_GENI_BASE (SPMI_BASE + 0xA000) |
| 68 | #define SPMI_PIC_BASE (SPMI_BASE + 0x01800000) |
| 69 | #define PMIC_ARB_CORE 0x200F000 |
| 70 | |
| 71 | #define TLMM_BASE_ADDR 0x1000000 |
| 72 | #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000) |
| 73 | #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000) |
| 74 | |
| 75 | #define MPM2_MPM_CTRL_BASE 0x004A0000 |
| 76 | #define MPM2_MPM_PS_HOLD 0x004AB000 |
| 77 | #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000 |
| 78 | |
| c_wufeng | 79c0646 | 2016-01-14 17:51:40 +0800 | [diff] [blame^] | 79 | #define PMI_SLAVE_BASE 2 |
| 80 | #define PMI_FIRST_SLAVE_OFFSET 0 |
| 81 | #define PMI_SECOND_SLAVE_OFFSET 1 |
| 82 | #define PMI_FIRST_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_FIRST_SLAVE_OFFSET ) << 16) |
| 83 | #define PMI_SECOND_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_SECOND_SLAVE_OFFSET) << 16) |
| 84 | |
| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 85 | /* CRYPTO ENGINE */ |
| 86 | #define MSM_CE1_BASE 0x073A000 |
| 87 | #define MSM_CE1_BAM_BASE 0x0704000 |
| P.V. Phani Kumar | 40fa135 | 2015-08-13 18:15:03 +0530 | [diff] [blame] | 88 | #define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000) |
| 89 | #define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004) |
| 90 | #define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008) |
| 91 | #define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C) |
| 92 | #define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020) |
| 93 | #define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024) |
| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 94 | |
| 95 | |
| 96 | /* GPLL */ |
| P.V. Phani Kumar | d017bb9 | 2015-11-26 18:31:03 +0530 | [diff] [blame] | 97 | #define GPLL0_MODE (CLK_CTL_BASE + 0x21000) |
| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 98 | #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000) |
| 99 | #define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004) |
| P.V. Phani Kumar | 40fa135 | 2015-08-13 18:15:03 +0530 | [diff] [blame] | 100 | #define GPLL4_MODE (CLK_CTL_BASE + 0x24000) |
| 101 | #define GPLL4_STATUS (CLK_CTL_BASE + 0x24024) |
| P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame] | 102 | #define GPLL6_STATUS (CLK_CTL_BASE + 0x37024) |
| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 103 | |
| 104 | /* SDCC */ |
| 105 | #define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000) |
| 106 | #define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/ |
| 107 | #define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */ |
| 108 | #define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C) |
| 109 | #define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */ |
| 110 | #define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */ |
| 111 | #define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */ |
| 112 | #define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */ |
| 113 | #define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */ |
| 114 | |
| P.V. Phani Kumar | 40fa135 | 2015-08-13 18:15:03 +0530 | [diff] [blame] | 115 | /* SDHCI */ |
| 116 | #define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900) |
| 117 | #define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900) |
| 118 | |
| 119 | #define SDCC_MCI_HC_MODE (0x00000078) |
| 120 | #define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC) |
| 121 | #define SDCC_HC_PWRCTL_MASK_REG (0x000000E0) |
| 122 | #define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4) |
| 123 | #define SDCC_HC_PWRCTL_CTL_REG (0x000000E8) |
| 124 | |
| 125 | #define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */ |
| 126 | #define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */ |
| 127 | #define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C) |
| 128 | #define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */ |
| 129 | #define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */ |
| 130 | #define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */ |
| 131 | #define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */ |
| 132 | #define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */ |
| 133 | |
| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 134 | /* UART */ |
| 135 | #define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008) |
| P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame] | 136 | #define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x203C) |
| 137 | #define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2044) |
| 138 | #define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x2048) |
| 139 | #define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x204C) |
| 140 | #define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x2050) |
| 141 | #define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x2054) |
| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 142 | #define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C) |
| 143 | #define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034) |
| 144 | #define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038) |
| 145 | #define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C) |
| 146 | #define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040) |
| 147 | #define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044) |
| 148 | |
| 149 | /* USB */ |
| 150 | #define USB_HS_BCR (CLK_CTL_BASE + 0x41000) |
| 151 | #define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004) |
| 152 | #define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008) |
| 153 | #define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010) |
| 154 | #define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014) |
| P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame] | 155 | #define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x4103C) |
| 156 | #define MSM_USB30_QSCRATCH_BASE 0x070F8800 |
| 157 | #define MSM_USB30_BASE 0x7000000 |
| 158 | #define USB2_PHY_SEL 0x01937000 |
| 159 | #define QUSB2_PHY_BASE 0X79000 |
| 160 | |
| 161 | /* SS QMP (Qulacomm Multi Protocol) */ |
| 162 | #define QMP_PHY_BASE 0x78000 |
| 163 | |
| 164 | #define AHB2_PHY_BASE 0x0007e000 |
| 165 | #define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10) |
| 166 | |
| 167 | /* USB3 clocks */ |
| 168 | #define USB_30_BCR (CLK_CTL_BASE + 0x3F070) |
| 169 | #define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x3F078) |
| 170 | #define USB30_MASTER_CBCR (CLK_CTL_BASE + 0x3F000) |
| 171 | #define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x3F004) |
| 172 | #define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x3F008) |
| 173 | #define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x3F00C) |
| 174 | #define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x3F010) |
| 175 | #define USB30_MASTER_M (CLK_CTL_BASE + 0x3F014) |
| 176 | #define USB30_MASTER_N (CLK_CTL_BASE + 0x3F018) |
| 177 | #define USB30_MASTER_D (CLK_CTL_BASE + 0x3F01C) |
| 178 | #define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0x3F020) |
| 179 | #define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0x3F024) |
| 180 | #define PC_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x3F038) |
| 181 | |
| 182 | #define USB3_AUX_CMD_RCGR (CLK_CTL_BASE + 0x3F05C) |
| 183 | #define USB3_AUX_CFG_RCGR (CLK_CTL_BASE + 0x3F060) |
| 184 | #define USB3_AUX_CBCR (CLK_CTL_BASE + 0x3F044) |
| 185 | #define USB3_AUX_M (CLK_CTL_BASE + 0x3F064) |
| 186 | #define USB3_AUX_N (CLK_CTL_BASE + 0x3F068) |
| 187 | #define USB3_AUX_D (CLK_CTL_BASE + 0x3F06C) |
| 188 | #define USB3_PIPE_CBCR (CLK_CTL_BASE + 0x3F040) |
| 189 | #define USB3_PHY_BCR (CLK_CTL_BASE + 0x3F034) |
| 190 | #define USB3PHY_PHY_BCR (CLK_CTL_BASE + 0x3F03C) |
| 191 | #define USB_PHY_CFG_AHB_CBCR (CLK_CTL_BASE + 0x3F080) |
| 192 | |
| 193 | /* QMP rev registers */ |
| 194 | #define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x988) |
| 195 | #define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x98C) |
| 196 | #define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x990) |
| 197 | #define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x994) |
| 198 | |
| 199 | /* Dummy macro needed for compilation only */ |
| 200 | #define PLATFORM_QMP_OFFSET 0x0 |
| 201 | |
| 202 | #define USB3_PHY_STATUS 0x78974 |
| 203 | /* Register for finding out if single ended or differential clock enablement */ |
| 204 | #define TCSR_PHY_CLK_SCHEME_SEL 0x0193F044 |
| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 205 | |
| P.V. Phani Kumar | a843c9f | 2015-09-08 11:19:34 +0530 | [diff] [blame] | 206 | /* RPMB send receive buffer needs to be mapped |
| 207 | * as device memory, define the start address |
| 208 | * and size in MB |
| 209 | */ |
| 210 | #define RPMB_SND_RCV_BUF 0x90000000 |
| 211 | #define RPMB_SND_RCV_BUF_SZ 0x1 |
| 212 | |
| 213 | /* QSEECOM: Secure app region notification */ |
| 214 | #define APP_REGION_ADDR 0x85E00000 |
| 215 | #define APP_REGION_SIZE 0x500000 |
| 216 | |
| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 217 | #define TCSR_TZ_WONCE 0x193D000 |
| 218 | #define TCSR_BOOT_MISC_DETECT 0x193D100 |
| 219 | |
| lijuang | 6e6aec5 | 2016-01-14 15:37:55 +0800 | [diff] [blame] | 220 | #define DDR_START get_ddr_start() |
| Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 221 | #define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000 |
| 222 | #define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000 |
| 223 | #define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000 |
| 224 | #define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000 |
| 225 | #endif |