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Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +05301/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_MSMTITANIUM_IOMAP_H_
30#define _PLATFORM_MSMTITANIUM_IOMAP_H_
31
32#define MSM_IOMAP_BASE 0x00000000
33#define MSM_IOMAP_END 0x08000000
34
35#define SDRAM_START_ADDR 0x80000000
36
37#define MSM_SHARED_BASE 0x86300000
38#define MSM_SHARED_IMEM_BASE 0x08600000
39
40#define BS_INFO_OFFSET (0x6B0)
41#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
42
43#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
44
45#define APPS_SS_BASE 0x0B000000
P.V. Phani Kumara053a322015-08-13 18:36:05 +053046#define APPS_SS_END 0x0B200000
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +053047
48#define MSM_GIC_DIST_BASE APPS_SS_BASE
49#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
50#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
51#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
52#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
53#define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00111008)
54
55#define PERIPH_SS_BASE 0x07800000
56
57#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
58#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000)
59
60#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
61#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
62#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000)
63
64#define CLK_CTL_BASE 0x1800000
65
66#define SPMI_BASE 0x02000000
67#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
68#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
69#define PMIC_ARB_CORE 0x200F000
70
71#define TLMM_BASE_ADDR 0x1000000
72#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
73#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
74
75#define MPM2_MPM_CTRL_BASE 0x004A0000
76#define MPM2_MPM_PS_HOLD 0x004AB000
77#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
78
79/* CRYPTO ENGINE */
80#define MSM_CE1_BASE 0x073A000
81#define MSM_CE1_BAM_BASE 0x0704000
P.V. Phani Kumar40fa1352015-08-13 18:15:03 +053082#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
83#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
84#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
85#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
86#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
87#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +053088
89
90/* GPLL */
91#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
92#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
93#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
P.V. Phani Kumar40fa1352015-08-13 18:15:03 +053094#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
95#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
96#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +053097
98/* SDCC */
99#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
100#define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/
101#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */
102#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C)
103#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */
104#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */
105#define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */
106#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
107#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
108
P.V. Phani Kumar40fa1352015-08-13 18:15:03 +0530109/* SDHCI */
110#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
111#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
112
113#define SDCC_MCI_HC_MODE (0x00000078)
114#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
115#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
116#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
117#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
118
119#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
120#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
121#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
122#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
123#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
124#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
125#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
126#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
127
Aparna Mallavarapu01fc00a2015-06-01 20:37:05 +0530128/* UART */
129#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
130#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
131#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
132#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
133#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
134#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
135#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
136
137/* USB */
138#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
139#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
140#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
141#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
142#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
143#define MSM_USB30_QSCRATCH_BASE 0x070F8800
144#define MSM_USB30_BASE 0x7000000
145#define USB2_PHY_SEL 0x01937000
146
147#define TCSR_TZ_WONCE 0x193D000
148#define TCSR_BOOT_MISC_DETECT 0x193D100
149
150#define DDR_START 0x80000000
151#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
152#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
153#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000
154#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000
155#endif