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gerrit-public.fairphone.software / kernel / lk / 80389724f879a317a2dc0be91529d2b59cbd08fb / . / platform / msm8952 / include / platform / iomap.h
blob: 69925229cbf033b6c8924505ddf7851bec3b06e7 [file] [log] [blame]
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]1/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_MSM8952_IOMAP_H_
30#define _PLATFORM_MSM8952_IOMAP_H_
31
32#define MSM_IOMAP_BASE 0x00000000
33#define MSM_IOMAP_END 0x08000000
34
35#define SDRAM_START_ADDR 0x80000000
36
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]37#define DDR_START get_ddr_start()
38#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
39#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
40#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000
41#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000
42
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]43#define MSM_SHARED_BASE 0x86300000
44#define MSM_SHARED_IMEM_BASE 0x08600000
45
46#define BS_INFO_OFFSET (0x6B0)
47#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
48
49#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
50
51#define APPS_SS_BASE 0x0B000000
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]52#define APPS_SS_END 0x0B200000
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]53
54#define MSM_GIC_DIST_BASE APPS_SS_BASE
55#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
56#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
57#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
58#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
Aparna Mallavarapufa5f8a72015-03-31 06:21:36 +0530[diff] [blame]59#define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00111008)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]60
61#define PERIPH_SS_BASE 0x07800000
62
63#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
64#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000)
65
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]66/* UART */
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]67#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
68#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
69#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000)
70
71#define CLK_CTL_BASE 0x1800000
72
73#define SPMI_BASE 0x02000000
74#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
75#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
76#define PMIC_ARB_CORE 0x200F000
77
78#define TLMM_BASE_ADDR 0x1000000
79#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
80#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
81
82#define MPM2_MPM_CTRL_BASE 0x004A0000
83#define MPM2_MPM_PS_HOLD 0x004AB000
84#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
85
86/* CRYPTO ENGINE */
87#define MSM_CE1_BASE 0x073A000
88#define MSM_CE1_BAM_BASE 0x0704000
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]89#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
90#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
91#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
92#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
93#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
94#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]95
96/* GPLL */
97#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
98#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
99#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]100#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]101
102/* SDCC */
103#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
104#define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/
105#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */
106#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C)
107#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */
108#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */
109#define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */
110#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
111#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
112
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]113/* SDHCI */
114#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
115#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
116
117#define SDCC_MCI_HC_MODE (0x00000078)
118#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
119#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
120#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
121#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
122
123#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
124#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
125#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
126#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
127#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
128#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
129#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
130#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
131
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]132/* UART */
133#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
134#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
135#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
136#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
137#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
138#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
139#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
140
141/* USB */
142#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
143#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
144#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
145#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
146#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
147
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame^]148/* MDSS */
149#define MIPI_DSI_BASE (0x1A98000)
150#define MIPI_DSI0_BASE MIPI_DSI_BASE
151#define MIPI_DSI1_BASE MIPI_DSI_BASE
152#define DSI0_PHY_BASE (0x1A98500)
153#define DSI1_PHY_BASE DSI0_PHY_BASE
154#define DSI0_PLL_BASE (0x1A98300)
155#define DSI1_PLL_BASE DSI0_PLL_BASE
156#define DSI0_REGULATOR_BASE (0x1A98780)
157#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
158#define MDP_BASE (0x1A00000)
159#define REG_MDP(off) (MDP_BASE + (off))
160
161#ifdef MDP_HW_REV
162#undef MDP_HW_REV
163#endif
164#define MDP_HW_REV REG_MDP(0x1000)
165
166#ifdef MDP_INTR_EN
167#undef MDP_INTR_EN
168#endif
169#define MDP_INTR_EN REG_MDP(0x1010)
170
171#ifdef MDP_INTR_CLEAR
172#undef MDP_INTR_CLEAR
173#endif
174#define MDP_INTR_CLEAR REG_MDP(0x1018)
175
176#ifdef MDP_HIST_INTR_EN
177#undef MDP_HIST_INTR_EN
178#endif
179#define MDP_HIST_INTR_EN REG_MDP(0x101C)
180
181#ifdef MDP_VP_0_VIG_0_BASE
182#undef MDP_VP_0_VIG_0_BASE
183#endif
184#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
185
186#ifdef MDP_VP_0_VIG_1_BASE
187#undef MDP_VP_0_VIG_1_BASE
188#endif
189#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
190
191#ifdef MDP_VP_0_RGB_0_BASE
192#undef MDP_VP_0_RGB_0_BASE
193#endif
194#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
195
196#ifdef MDP_VP_0_RGB_1_BASE
197#undef MDP_VP_0_RGB_1_BASE
198#endif
199#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
200
201#ifdef MDP_VP_0_DMA_0_BASE
202#undef MDP_VP_0_DMA_0_BASE
203#endif
204#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
205
206#ifdef MDP_VP_0_DMA_1_BASE
207#undef MDP_VP_0_DMA_1_BASE
208#endif
209#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
210
211#ifdef MDP_VP_0_MIXER_0_BASE
212#undef MDP_VP_0_MIXER_0_BASE
213#endif
214#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
215
216#ifdef MDP_VP_0_MIXER_1_BASE
217#undef MDP_VP_0_MIXER_1_BASE
218#endif
219#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
220
221#ifdef MDP_DISP_INTF_SEL
222#undef MDP_DISP_INTF_SEL
223#endif
224#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
225
226#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
227#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
228#endif
229#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
230
231#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
232#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
233#endif
234#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
235
236#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
237#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
238#endif
239#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
240
241#ifdef MDP_CTL_0_BASE
242#undef MDP_CTL_0_BASE
243#endif
244#define MDP_CTL_0_BASE REG_MDP(0x2000)
245
246#ifdef MDP_CTL_1_BASE
247#undef MDP_CTL_1_BASE
248#endif
249#define MDP_CTL_1_BASE REG_MDP(0x2200)
250
251#ifdef MDP_CLK_CTRL0
252#undef MDP_CLK_CTRL0
253#endif
254#define MDP_CLK_CTRL0 REG_MDP(0x012AC)
255
256#ifdef MDP_CLK_CTRL1
257#undef MDP_CLK_CTRL1
258#endif
259#define MDP_CLK_CTRL1 REG_MDP(0x012B4)
260
261#ifdef MDP_CLK_CTRL2
262#undef MDP_CLK_CTRL2
263#endif
264#define MDP_CLK_CTRL2 REG_MDP(0x012BC)
265
266#ifdef MDP_CLK_CTRL3
267#undef MDP_CLK_CTRL3
268#endif
269#define MDP_CLK_CTRL3 REG_MDP(0x013A8)
270
271#ifdef MDP_CLK_CTRL4
272#undef MDP_CLK_CTRL4
273#endif
274#define MDP_CLK_CTRL4 REG_MDP(0x013B0)
275
276#ifdef MDP_CLK_CTRL5
277#undef MDP_CLK_CTRL5
278#endif
279#define MDP_CLK_CTRL5 REG_MDP(0x013B8)
280
281#ifdef MDP_INTF_1_BASE
282#undef MDP_INTF_1_BASE
283#endif
284#define MDP_INTF_1_BASE REG_MDP(0x12700)
285
286#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
287#undef MMSS_MDP_SMP_ALLOC_W_BASE
288#endif
289#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
290
291#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
292#undef MMSS_MDP_SMP_ALLOC_R_BASE
293#endif
294#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
295
296#ifdef MDP_QOS_REMAPPER_CLASS_0
297#undef MDP_QOS_REMAPPER_CLASS_0
298#endif
299#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
300
301#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
302#undef VBIF_VBIF_DDR_FORCE_CLK_ON
303#endif
304#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
305
306#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
307#undef VBIF_VBIF_DDR_OUT_MAX_BURST
308#endif
309#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
310
311#ifdef VBIF_VBIF_DDR_ARB_CTRL
312#undef VBIF_VBIF_DDR_ARB_CTRL
313#endif
314#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
315
316#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
317#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
318#endif
319#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
320
321#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
322#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
323#endif
324#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
325
326#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
327#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
328#endif
329#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
330
331#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
332#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
333#endif
334#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
335
336#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
337#undef VBIF_VBIF_DDR_OUT_AX_AOOO
338#endif
339#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
340
341#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
342#undef VBIF_VBIF_IN_RD_LIM_CONF0
343#endif
344#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
345
346#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
347#undef VBIF_VBIF_IN_RD_LIM_CONF1
348#endif
349#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
350
351#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
352#undef VBIF_VBIF_IN_WR_LIM_CONF0
353#endif
354#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
355
356#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
357#undef VBIF_VBIF_IN_WR_LIM_CONF1
358#endif
359#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
360
361#define SOFT_RESET 0x118
362#define CLK_CTRL 0x11C
363#define TRIG_CTRL 0x084
364#define CTRL 0x004
365#define COMMAND_MODE_DMA_CTRL 0x03C
366#define COMMAND_MODE_MDP_CTRL 0x040
367#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
368#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
369#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
370#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
371#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
372#define ERR_INT_MASK0 0x10C
373
374#define LANE_CTL 0x0AC
375#define LANE_SWAP_CTL 0x0B0
376#define TIMING_CTL 0x0C4
377
378#define VIDEO_MODE_ACTIVE_H 0x024
379#define VIDEO_MODE_ACTIVE_V 0x028
380#define VIDEO_MODE_TOTAL 0x02C
381#define VIDEO_MODE_HSYNC 0x030
382#define VIDEO_MODE_VSYNC 0x034
383#define VIDEO_MODE_VSYNC_VPOS 0x038
384
385#define DMA_CMD_OFFSET 0x048
386#define DMA_CMD_LENGTH 0x04C
387
388#define INT_CTRL 0x110
389#define CMD_MODE_DMA_SW_TRIGGER 0x090
390
391#define EOT_PACKET_CTRL 0x0CC
392#define MISR_CMD_CTRL 0x0A0
393#define MISR_VIDEO_CTRL 0x0A4
394#define VIDEO_MODE_CTRL 0x010
395#define HS_TIMER_CTRL 0x0BC
396
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]397#define TCSR_TZ_WONCE 0x193D000
398#define TCSR_BOOT_MISC_DETECT 0x193D100
399#endif