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Travis Geiselbrecht1d0df692008-09-01 02:26:09 -07001/*
2 * Copyright (c) 2008 Travis Geiselbrecht
3 *
Channagoud Kadabi87fbe8d2014-04-08 14:14:23 -07004 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
Channagoud Kadabi5fd4efa2013-04-23 14:30:17 -07005 *
Travis Geiselbrecht1d0df692008-09-01 02:26:09 -07006 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files
8 * (the "Software"), to deal in the Software without restriction,
9 * including without limitation the rights to use, copy, modify, merge,
10 * publish, distribute, sublicense, and/or sell copies of the Software,
11 * and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be
15 * included in all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
21 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25#ifndef __ARCH_CPU_H
26#define __ARCH_CPU_H
27
28/* arm specific stuff */
29#define PAGE_SIZE 4096
30
Amol Jadi9ef9b732011-05-23 16:00:17 -070031#if defined(ARM_CPU_ARM1136)
32 #define CACHE_LINE 32
33#elif defined(ARM_CPU_CORE_A5)
34 #define CACHE_LINE 32
35#elif defined(ARM_CPU_CORE_SCORPION)
36 #define CACHE_LINE 32
David Ng296fc0c2013-01-17 12:04:58 -080037#elif defined(ARM_CPU_CORE_KRAIT) || defined(ARM_CPU_CORE_A7)
Amol Jadi9ef9b732011-05-23 16:00:17 -070038 #define CACHE_LINE 64
Travis Geiselbrecht1d0df692008-09-01 02:26:09 -070039#else
Amol Jadi9ef9b732011-05-23 16:00:17 -070040 #error unknown cpu
Travis Geiselbrecht1d0df692008-09-01 02:26:09 -070041#endif
42
Channagoud Kadabi5fd4efa2013-04-23 14:30:17 -070043#define IS_CACHE_LINE_ALIGNED(addr) !((uint32_t) (addr) & (CACHE_LINE - 1))
Channagoud Kadabic9f8da62013-08-05 15:27:13 -070044
45#if ARM_ISA_ARMV7
46#define dsb() __asm__ volatile ("dsb" : : : "memory");
Channagoud Kadabi87fbe8d2014-04-08 14:14:23 -070047#define dmb() __asm__ volatile ("dmb" : : : "memory");
Channagoud Kadabic9f8da62013-08-05 15:27:13 -070048#elif ARM_ISA_ARMV6
49#define dsb() __asm__ volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0): "memory");
Channagoud Kadabi87fbe8d2014-04-08 14:14:23 -070050#define dmb() __asm__ volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0): "memory");
Channagoud Kadabic9f8da62013-08-05 15:27:13 -070051#endif
52
Deepa Dinamani65df1502013-07-29 13:23:04 -070053#define GET_CAHE_LINE_START_ADDR(addr) ROUNDDOWN(addr, CACHE_LINE)
Travis Geiselbrecht1d0df692008-09-01 02:26:09 -070054
Deepa Dinamani65df1502013-07-29 13:23:04 -070055#endif