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Channagoud Kadabi6608d022015-04-20 11:31:56 -07001/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
Joonwoo Park451dca32014-04-02 11:47:03 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <assert.h>
30#include <reg.h>
31#include <err.h>
32#include <clock.h>
33#include <clock_pll.h>
34#include <clock_lib2.h>
35#include <platform/clock.h>
36#include <platform/iomap.h>
37
38
39/* Mux source select values */
40#define cxo_source_val 0
41#define gpll0_source_val 1
42#define usb30_pipe_source_val 2
43
44struct clk_freq_tbl rcg_dummy_freq = F_END;
45
46
47/* Clock Operations */
48static struct clk_ops clk_ops_reset =
49{
50 .reset = clock_lib2_reset_clk_reset,
51};
52
53static struct clk_ops clk_ops_branch =
54{
55 .enable = clock_lib2_branch_clk_enable,
56 .disable = clock_lib2_branch_clk_disable,
57 .set_rate = clock_lib2_branch_set_rate,
Channagoud Kadabi1b69e482014-09-23 15:20:22 -070058 .reset = clock_lib2_branch_clk_reset,
Joonwoo Park451dca32014-04-02 11:47:03 -070059};
60
61static struct clk_ops clk_ops_rcg_mnd =
62{
63 .enable = clock_lib2_rcg_enable,
64 .set_rate = clock_lib2_rcg_set_rate,
65};
66
67static struct clk_ops clk_ops_rcg =
68{
69 .enable = clock_lib2_rcg_enable,
70 .set_rate = clock_lib2_rcg_set_rate,
71};
72
73static struct clk_ops clk_ops_cxo =
74{
75 .enable = cxo_clk_enable,
76 .disable = cxo_clk_disable,
77};
78
79static struct clk_ops clk_ops_pll_vote =
80{
81 .enable = pll_vote_clk_enable,
82 .disable = pll_vote_clk_disable,
83 .auto_off = pll_vote_clk_disable,
84 .is_enabled = pll_vote_clk_is_enabled,
85};
86
87static struct clk_ops clk_ops_vote =
88{
89 .enable = clock_lib2_vote_clk_enable,
90 .disable = clock_lib2_vote_clk_disable,
91};
92
93/* Clock Sources */
94static struct fixed_clk cxo_clk_src =
95{
96 .c = {
97 .rate = 19200000,
98 .dbg_name = "cxo_clk_src",
99 .ops = &clk_ops_cxo,
100 },
101};
102
103static struct pll_vote_clk gpll0_clk_src =
104{
105 .en_reg = (void *) APCS_GPLL_ENA_VOTE,
106 .en_mask = BIT(0),
107 .status_reg = (void *) GPLL0_STATUS,
108 .status_mask = BIT(30),
109 .parent = &cxo_clk_src.c,
110
111 .c = {
112 .rate = 800000000,
113 .dbg_name = "gpll0_clk_src",
114 .ops = &clk_ops_pll_vote,
115 },
116};
117
118/* SDCC Clocks */
119static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
120{
121 F( 144000, cxo, 16, 3, 25),
122 F( 400000, cxo, 12, 1, 4),
Joonwoo Park095007a2014-06-27 17:57:45 -0700123 F( 20000000, gpll0, 15, 1, 2),
124 F( 25000000, gpll0, 12, 1, 2),
125 F( 50000000, gpll0, 12, 0, 0),
126 F(100000000, gpll0, 6, 0, 0),
Channagoud Kadabi6608d022015-04-20 11:31:56 -0700127 F(171430000, gpll0, 3, 50, 0),
Joonwoo Park095007a2014-06-27 17:57:45 -0700128 F(200000000, gpll0, 3, 0, 0),
Joonwoo Park451dca32014-04-02 11:47:03 -0700129 F_END
130};
131
132static struct rcg_clk sdcc1_apps_clk_src =
133{
134 .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
135 .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
136 .m_reg = (uint32_t *) SDCC1_M,
137 .n_reg = (uint32_t *) SDCC1_N,
138 .d_reg = (uint32_t *) SDCC1_D,
139
140 .set_rate = clock_lib2_rcg_set_rate_mnd,
141 .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
142 .current_freq = &rcg_dummy_freq,
143
144 .c = {
145 .dbg_name = "sdc1_clk",
146 .ops = &clk_ops_rcg_mnd,
147 },
148};
149
150static struct branch_clk gcc_sdcc1_apps_clk =
151{
152 .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
153 .parent = &sdcc1_apps_clk_src.c,
154
155 .c = {
156 .dbg_name = "gcc_sdcc1_apps_clk",
157 .ops = &clk_ops_branch,
158 },
159};
160
161static struct branch_clk gcc_sdcc1_ahb_clk =
162{
163 .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
164 .has_sibling = 1,
165
166 .c = {
167 .dbg_name = "gcc_sdcc1_ahb_clk",
168 .ops = &clk_ops_branch,
169 },
170};
171
172/* UART Clocks */
173static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
174{
Joonwoo Park095007a2014-06-27 17:57:45 -0700175 F( 3686400, gpll0, 1, 96, 15625),
176 F( 7372800, gpll0, 1, 192, 15625),
177 F(14745600, gpll0, 1, 384, 15625),
178 F(16000000, gpll0, 5, 2, 15),
Joonwoo Park451dca32014-04-02 11:47:03 -0700179 F(19200000, cxo, 1, 0, 0),
Joonwoo Park095007a2014-06-27 17:57:45 -0700180 F(24000000, gpll0, 5, 1, 5),
181 F(32000000, gpll0, 1, 4, 75),
182 F(40000000, gpll0, 15, 0, 0),
183 F(46400000, gpll0, 1, 29, 375),
184 F(48000000, gpll0, 12.5, 0, 0),
185 F(51200000, gpll0, 1, 32, 375),
186 F(56000000, gpll0, 1, 7, 75),
187 F(58982400, gpll0, 1, 1536, 15625),
188 F(60000000, gpll0, 10, 0, 0),
189 F(63160000, gpll0, 9.5, 0, 0),
Joonwoo Park451dca32014-04-02 11:47:03 -0700190 F_END
191};
192
Channagoud Kadabi1b69e482014-09-23 15:20:22 -0700193static struct rcg_clk blsp1_uart3_apps_clk_src =
Joonwoo Park451dca32014-04-02 11:47:03 -0700194{
Channagoud Kadabi1b69e482014-09-23 15:20:22 -0700195 .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR,
196 .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR,
197 .m_reg = (uint32_t *) BLSP1_UART3_APPS_M,
198 .n_reg = (uint32_t *) BLSP1_UART3_APPS_N,
199 .d_reg = (uint32_t *) BLSP1_UART3_APPS_D,
Joonwoo Park451dca32014-04-02 11:47:03 -0700200
201 .set_rate = clock_lib2_rcg_set_rate_mnd,
202 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
203 .current_freq = &rcg_dummy_freq,
204
205 .c = {
Channagoud Kadabi1b69e482014-09-23 15:20:22 -0700206 .dbg_name = "blsp1_uart3_apps_clk",
Joonwoo Park451dca32014-04-02 11:47:03 -0700207 .ops = &clk_ops_rcg_mnd,
208 },
209};
210
Channagoud Kadabi1b69e482014-09-23 15:20:22 -0700211static struct branch_clk gcc_blsp1_uart3_apps_clk =
Joonwoo Park451dca32014-04-02 11:47:03 -0700212{
Channagoud Kadabi1b69e482014-09-23 15:20:22 -0700213 .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR,
214 .parent = &blsp1_uart3_apps_clk_src.c,
Joonwoo Park451dca32014-04-02 11:47:03 -0700215
216 .c = {
Channagoud Kadabi1b69e482014-09-23 15:20:22 -0700217 .dbg_name = "gcc_blsp1_uart3_apps_clk",
Joonwoo Park451dca32014-04-02 11:47:03 -0700218 .ops = &clk_ops_branch,
219 },
220};
221
222static struct vote_clk gcc_blsp1_ahb_clk = {
223 .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
224 .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
225 .en_mask = BIT(10),
226
227 .c = {
228 .dbg_name = "gcc_blsp1_ahb_clk",
229 .ops = &clk_ops_vote,
230 },
231};
232
233/* USB Clocks */
Joonwoo Park451dca32014-04-02 11:47:03 -0700234static struct branch_clk gcc_sys_noc_usb30_axi_clk =
235{
236 .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR,
237 .has_sibling = 1,
238
239 .c = {
240 .dbg_name = "gcc_sys_noc_usb3_axi_clk",
241 .ops = &clk_ops_branch,
242 },
243};
244
245static struct branch_clk gcc_usb_phy_cfg_ahb_clk = {
246 .cbcr_reg = (uint32_t *) USB_PHY_CFG_AHB_CBCR,
247 .has_sibling = 1,
248
249 .c = {
250 .dbg_name = "gcc_usb_phy_cfg_ahb_clk",
251 .ops = &clk_ops_branch,
252 },
253};
254
255static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
256{
257 F(125000000, gpll0, 1, 5, 24),
258 F_END
259};
260
261static struct rcg_clk usb30_master_clk_src =
262{
263 .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR,
264 .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR,
265 .m_reg = (uint32_t *) GCC_USB30_MASTER_M,
266 .n_reg = (uint32_t *) GCC_USB30_MASTER_N,
267 .d_reg = (uint32_t *) GCC_USB30_MASTER_D,
268
269 .set_rate = clock_lib2_rcg_set_rate_mnd,
270 .freq_tbl = ftbl_gcc_usb30_master_clk,
271 .current_freq = &rcg_dummy_freq,
272
273 .c = {
274 .dbg_name = "usb30_master_clk_src",
275 .ops = &clk_ops_rcg,
276 },
277};
278
Joonwoo Park451dca32014-04-02 11:47:03 -0700279static struct branch_clk gcc_usb30_master_clk =
280{
281 .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR,
Channagoud Kadabifdfee232015-10-07 11:55:47 -0700282 .bcr_reg = (uint32_t *) USB_30_BCR,
Joonwoo Park451dca32014-04-02 11:47:03 -0700283 .parent = &usb30_master_clk_src.c,
284
285 .c = {
286 .dbg_name = "gcc_usb30_master_clk",
287 .ops = &clk_ops_branch,
288 },
289};
290
291static struct clk_freq_tbl ftbl_gcc_usb30_pipe_clk[] = {
292 F( 19200000, cxo, 1, 0, 0),
293 F_EXT_SRC( 125000000, usb30_pipe, 1, 0, 0),
294 F_END
295};
296
297static struct rcg_clk usb30_pipe_clk_src = {
298 .cmd_reg = (uint32_t *) USB3_PIPE_CMD_RCGR,
299 .cfg_reg = (uint32_t *) USB3_PIPE_CFG_RCGR,
300 .set_rate = clock_lib2_rcg_set_rate_hid,
301 .freq_tbl = ftbl_gcc_usb30_pipe_clk,
302 .current_freq = &rcg_dummy_freq,
303
304 .c = {
305 .dbg_name = "usb30_pipe_clk_src",
306 .ops = &clk_ops_rcg,
307 },
308};
309
310static struct branch_clk gcc_usb30_pipe_clk = {
311 .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
Channagoud Kadabi1b69e482014-09-23 15:20:22 -0700312 .bcr_reg = (uint32_t *) USB3_PIPE_BCR,
Joonwoo Park451dca32014-04-02 11:47:03 -0700313 .parent = &usb30_pipe_clk_src.c,
314 .has_sibling = 0,
315
316 .c = {
317 .dbg_name = "gcc_usb30_pipe_clk",
318 .ops = &clk_ops_branch,
319 },
320};
321
Channagoud Kadabifdfee232015-10-07 11:55:47 -0700322
323static struct branch_clk gcc_usb30_pipe_clk_mdmcalifornium = {
324 .bcr_reg = (uint32_t *) USB3_PIPE_BCR,
325 .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
326 .has_sibling = 1,
327 .halt_check = 0,
328
329 .c = {
330 .dbg_name = "usb30_pipe_clk_mdmcalifornium",
331 .ops = &clk_ops_branch,
332 },
333};
334
Joonwoo Park451dca32014-04-02 11:47:03 -0700335static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = {
336 F( 1000000, cxo, 1, 5, 96),
337 F_END
338};
339
340static struct rcg_clk usb30_aux_clk_src = {
341 .cmd_reg = (uint32_t *) USB3_AUX_CMD_RCGR,
342 .cfg_reg = (uint32_t *) USB3_AUX_CFG_RCGR,
343 .m_reg = (uint32_t *) USB3_AUX_M,
344 .n_reg = (uint32_t *) USB3_AUX_N,
345 .d_reg = (uint32_t *) USB3_AUX_D,
346
347 .set_rate = clock_lib2_rcg_set_rate_mnd,
348 .freq_tbl = ftbl_gcc_usb30_aux_clk,
349 .current_freq = &rcg_dummy_freq,
350
351 .c = {
352 .dbg_name = "usb30_aux_clk_src",
353 .ops = &clk_ops_rcg_mnd,
354 },
355};
356
357static struct branch_clk gcc_usb30_aux_clk = {
358 .cbcr_reg = (uint32_t *) USB3_AUX_CBCR,
359 .parent = &usb30_aux_clk_src.c,
360
361 .c = {
362 .dbg_name = "gcc_usb30_aux_clk",
363 .ops = &clk_ops_branch,
364 },
365};
366
367static struct reset_clk gcc_usb30_phy_reset = {
Sridhar Parasuram673c6bb2014-12-29 13:39:35 -0800368 .bcr_reg = (uint32_t) USB3_PHY_BCR,
Joonwoo Park451dca32014-04-02 11:47:03 -0700369
370 .c = {
371 .dbg_name = "usb30_phy_reset",
372 .ops = &clk_ops_reset,
373 },
374};
375
Joonwoo Park76641c72014-05-22 16:37:10 -0700376static struct reset_clk gcc_usb2a_phy_sleep_clk = {
Sridhar Parasuram673c6bb2014-12-29 13:39:35 -0800377 .bcr_reg = (uint32_t) QUSB2A_PHY_BCR,
Joonwoo Park76641c72014-05-22 16:37:10 -0700378
379 .c = {
380 .dbg_name = "usb2b_phy_sleep_clk",
381 .ops = &clk_ops_reset,
382 },
383};
384
Channagoud Kadabifdfee232015-10-07 11:55:47 -0700385static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
386 F( 60000000, gpll0, 10, 0, 0),
387 F_END
388};
389
390static struct rcg_clk usb30_mock_utmi_clk_src = {
391 .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR,
392 .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR,
393 .set_rate = clock_lib2_rcg_set_rate_hid,
394 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
395 .current_freq = &rcg_dummy_freq,
396
397 .c = {
398 .dbg_name = "usb30_mock_utmi_clk_src",
399 .ops = &clk_ops_rcg,
400 },
401};
402
403static struct branch_clk gcc_usb30_mock_utmi_clk = {
404 .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR,
405 .has_sibling = 0,
406 .parent = &usb30_mock_utmi_clk_src.c,
407
408 .c = {
409 .dbg_name = "usb30_mock_utmi_clk",
410 .ops = &clk_ops_branch,
411 },
412};
413
414static struct branch_clk gcc_usb30_sleep_clk = {
415 .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR,
416 .has_sibling = 1,
417
418 .c = {
419 .dbg_name = "usb30_sleep_clk",
420 .ops = &clk_ops_branch,
421 },
422};
423
424
425
anisha agarwaldd04af62014-11-17 10:57:49 -0800426static struct clk_lookup msm_clocks_9640[] =
Joonwoo Park451dca32014-04-02 11:47:03 -0700427{
428 CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
429 CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
430
Channagoud Kadabi1b69e482014-09-23 15:20:22 -0700431 CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c),
432 CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c),
Joonwoo Park451dca32014-04-02 11:47:03 -0700433
Joonwoo Park451dca32014-04-02 11:47:03 -0700434 CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
435 CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
436 CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
Channagoud Kadabifdfee232015-10-07 11:55:47 -0700437 CLK_LOOKUP("usb30_pipe_clk_mdmcalifornium", gcc_usb30_pipe_clk_mdmcalifornium.c),
Joonwoo Park451dca32014-04-02 11:47:03 -0700438 CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c),
439
Joonwoo Park76641c72014-05-22 16:37:10 -0700440 CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c),
Joonwoo Park451dca32014-04-02 11:47:03 -0700441 CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
442
Channagoud Kadabifdfee232015-10-07 11:55:47 -0700443 CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
Joonwoo Park451dca32014-04-02 11:47:03 -0700444 CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c),
Channagoud Kadabifdfee232015-10-07 11:55:47 -0700445 CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
Joonwoo Park451dca32014-04-02 11:47:03 -0700446};
447
448void platform_clock_init(void)
449{
anisha agarwaldd04af62014-11-17 10:57:49 -0800450 clk_init(msm_clocks_9640, ARRAY_SIZE(msm_clocks_9640));
Joonwoo Park451dca32014-04-02 11:47:03 -0700451}