Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | #include <platform.h> |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define gpll4_source_val 2 |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 43 | #define gpll6_source_val 1 |
| 44 | #define gpll0_out_main_div2_source_val 4 |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 45 | #define cxo_mm_source_val 0 |
| 46 | #define gpll0_mm_source_val 6 |
| 47 | #define gpll6_mm_source_val 3 |
| 48 | |
| 49 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 50 | |
| 51 | |
| 52 | /* Clock Operations */ |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 53 | |
| 54 | static struct clk_ops clk_ops_reset = |
| 55 | { |
| 56 | .reset = clock_lib2_reset_clk_reset, |
| 57 | }; |
| 58 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 59 | static struct clk_ops clk_ops_branch = |
| 60 | { |
| 61 | .enable = clock_lib2_branch_clk_enable, |
| 62 | .disable = clock_lib2_branch_clk_disable, |
| 63 | .set_rate = clock_lib2_branch_set_rate, |
| 64 | }; |
| 65 | |
| 66 | static struct clk_ops clk_ops_rcg_mnd = |
| 67 | { |
| 68 | .enable = clock_lib2_rcg_enable, |
| 69 | .set_rate = clock_lib2_rcg_set_rate, |
| 70 | }; |
| 71 | |
| 72 | static struct clk_ops clk_ops_rcg = |
| 73 | { |
| 74 | .enable = clock_lib2_rcg_enable, |
| 75 | .set_rate = clock_lib2_rcg_set_rate, |
| 76 | }; |
| 77 | |
| 78 | static struct clk_ops clk_ops_cxo = |
| 79 | { |
| 80 | .enable = cxo_clk_enable, |
| 81 | .disable = cxo_clk_disable, |
| 82 | }; |
| 83 | |
| 84 | static struct clk_ops clk_ops_pll_vote = |
| 85 | { |
| 86 | .enable = pll_vote_clk_enable, |
| 87 | .disable = pll_vote_clk_disable, |
| 88 | .auto_off = pll_vote_clk_disable, |
| 89 | .is_enabled = pll_vote_clk_is_enabled, |
| 90 | }; |
| 91 | |
| 92 | static struct clk_ops clk_ops_vote = |
| 93 | { |
| 94 | .enable = clock_lib2_vote_clk_enable, |
| 95 | .disable = clock_lib2_vote_clk_disable, |
| 96 | }; |
| 97 | |
| 98 | /* Clock Sources */ |
| 99 | static struct fixed_clk cxo_clk_src = |
| 100 | { |
| 101 | .c = { |
| 102 | .rate = 19200000, |
| 103 | .dbg_name = "cxo_clk_src", |
| 104 | .ops = &clk_ops_cxo, |
| 105 | }, |
| 106 | }; |
| 107 | |
| 108 | static struct pll_vote_clk gpll0_clk_src = |
| 109 | { |
| 110 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 111 | .en_mask = BIT(0), |
P.V. Phani Kumar | d017bb9 | 2015-11-26 18:31:03 +0530 | [diff] [blame] | 112 | .status_reg = (void *) GPLL0_MODE, |
| 113 | .status_mask = BIT(30), |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 114 | .parent = &cxo_clk_src.c, |
| 115 | |
| 116 | .c = { |
| 117 | .rate = 800000000, |
| 118 | .dbg_name = "gpll0_clk_src", |
| 119 | .ops = &clk_ops_pll_vote, |
| 120 | }, |
| 121 | }; |
| 122 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 123 | static struct pll_vote_clk gpll0_out_main_div2_clk_src = |
| 124 | { |
| 125 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 126 | .en_mask = BIT(0), |
| 127 | .status_reg = (void *) GPLL0_MODE, |
| 128 | .status_mask = BIT(30), |
| 129 | .parent = &cxo_clk_src.c, |
| 130 | |
| 131 | .c = { |
| 132 | .rate = 400000000, |
| 133 | .dbg_name = "gpll0_out_main_div2_clk_src", |
| 134 | .ops = &clk_ops_pll_vote, |
| 135 | }, |
| 136 | }; |
| 137 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 138 | static struct pll_vote_clk gpll4_clk_src = |
| 139 | { |
| 140 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 141 | .en_mask = BIT(5), |
| 142 | .status_reg = (void *) GPLL4_MODE, |
| 143 | .status_mask = BIT(30), |
| 144 | .parent = &cxo_clk_src.c, |
| 145 | |
| 146 | .c = { |
| 147 | .rate = 1152000000, |
| 148 | .dbg_name = "gpll4_clk_src", |
| 149 | .ops = &clk_ops_pll_vote, |
| 150 | }, |
| 151 | }; |
| 152 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 153 | static struct pll_vote_clk gpll6_clk_src = |
| 154 | { |
| 155 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 156 | .en_mask = BIT(7), |
| 157 | .status_reg = (void *) GPLL6_STATUS, |
| 158 | .status_mask = BIT(17), |
| 159 | .parent = &cxo_clk_src.c, |
| 160 | |
| 161 | .c = { |
| 162 | .rate = 1080000000, |
| 163 | .dbg_name = "gpll6_clk_src", |
| 164 | .ops = &clk_ops_pll_vote, |
| 165 | }, |
| 166 | }; |
| 167 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 168 | /* SDCC Clocks */ |
| 169 | static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = |
| 170 | { |
| 171 | F( 144000, cxo, 16, 3, 25), |
| 172 | F( 400000, cxo, 12, 1, 4), |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 173 | F( 20000000, gpll0_out_main_div2, 5, 1, 2), |
| 174 | F( 25000000, gpll0_out_main_div2, 16, 0, 0), |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 175 | F( 50000000, gpll0, 16, 0, 0), |
| 176 | F(100000000, gpll0, 8, 0, 0), |
| 177 | F(177770000, gpll0, 4.5, 0, 0), |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 178 | F(192000000, gpll4, 6, 0, 0), |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 179 | F(384000000, gpll4, 3, 0, 0), |
| 180 | F_END |
| 181 | }; |
| 182 | |
| 183 | static struct rcg_clk sdcc1_apps_clk_src = |
| 184 | { |
| 185 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 186 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 187 | .m_reg = (uint32_t *) SDCC1_M, |
| 188 | .n_reg = (uint32_t *) SDCC1_N, |
| 189 | .d_reg = (uint32_t *) SDCC1_D, |
| 190 | |
| 191 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 192 | .freq_tbl = ftbl_gcc_sdcc1_apps_clk, |
| 193 | .current_freq = &rcg_dummy_freq, |
| 194 | |
| 195 | .c = { |
| 196 | .dbg_name = "sdc1_clk", |
| 197 | .ops = &clk_ops_rcg_mnd, |
| 198 | }, |
| 199 | }; |
| 200 | |
| 201 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 202 | { |
| 203 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 204 | .parent = &sdcc1_apps_clk_src.c, |
| 205 | |
| 206 | .c = { |
| 207 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 208 | .ops = &clk_ops_branch, |
| 209 | }, |
| 210 | }; |
| 211 | |
| 212 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 213 | { |
| 214 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 215 | .has_sibling = 1, |
| 216 | |
| 217 | .c = { |
| 218 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 219 | .ops = &clk_ops_branch, |
| 220 | }, |
| 221 | }; |
| 222 | |
| 223 | static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = |
| 224 | { |
| 225 | F( 144000, cxo, 16, 3, 25), |
| 226 | F( 400000, cxo, 12, 1, 4), |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 227 | F( 20000000, gpll0_out_main_div2, 5, 1, 2), |
| 228 | F( 25000000, gpll0_out_main_div2, 16, 0, 0), |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 229 | F( 50000000, gpll0, 16, 0, 0), |
| 230 | F(100000000, gpll0, 8, 0, 0), |
| 231 | F(177770000, gpll0, 4.5, 0, 0), |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 232 | F(192000000, gpll4, 6, 0, 0), |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 233 | F_END |
| 234 | }; |
| 235 | |
| 236 | static struct rcg_clk sdcc2_apps_clk_src = |
| 237 | { |
| 238 | .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR, |
| 239 | .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR, |
| 240 | .m_reg = (uint32_t *) SDCC2_M, |
| 241 | .n_reg = (uint32_t *) SDCC2_N, |
| 242 | .d_reg = (uint32_t *) SDCC2_D, |
| 243 | |
| 244 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 245 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk, |
| 246 | .current_freq = &rcg_dummy_freq, |
| 247 | |
| 248 | .c = { |
| 249 | .dbg_name = "sdc2_clk", |
| 250 | .ops = &clk_ops_rcg_mnd, |
| 251 | }, |
| 252 | }; |
| 253 | |
| 254 | static struct branch_clk gcc_sdcc2_apps_clk = |
| 255 | { |
| 256 | .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR, |
| 257 | .parent = &sdcc2_apps_clk_src.c, |
| 258 | |
| 259 | .c = { |
| 260 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 261 | .ops = &clk_ops_branch, |
| 262 | }, |
| 263 | }; |
| 264 | |
| 265 | static struct branch_clk gcc_sdcc2_ahb_clk = |
| 266 | { |
| 267 | .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR, |
| 268 | .has_sibling = 1, |
| 269 | |
| 270 | .c = { |
| 271 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 272 | .ops = &clk_ops_branch, |
| 273 | }, |
| 274 | }; |
| 275 | |
| 276 | /* UART Clocks */ |
| 277 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = |
| 278 | { |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 279 | F( 3686400, gpll0_out_main_div2, 1, 144, 15625), |
| 280 | F( 7372800, gpll0_out_main_div2, 1, 288, 15625), |
| 281 | F(14745600, gpll0_out_main_div2, 1, 576, 15625), |
| 282 | F(16000000, gpll0_out_main_div2, 5, 1, 5), |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 283 | F(19200000, cxo, 1, 0, 0), |
| 284 | F(24000000, gpll0, 1, 3, 100), |
| 285 | F(25000000, gpll0, 16, 1, 2), |
| 286 | F(32000000, gpll0, 1, 1, 25), |
| 287 | F(40000000, gpll0, 1, 1, 20), |
| 288 | F(46400000, gpll0, 1, 29, 500), |
| 289 | F(48000000, gpll0, 1, 3, 50), |
| 290 | F(51200000, gpll0, 1, 8, 125), |
| 291 | F(56000000, gpll0, 1, 7, 100), |
| 292 | F(58982400, gpll0, 1,1152, 15625), |
| 293 | F(60000000, gpll0, 1, 3, 40), |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 294 | F(64000000, gpll0, 12, 1, 2), |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 295 | F_END |
| 296 | }; |
| 297 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 298 | static struct rcg_clk blsp1_uart1_apps_clk_src = |
| 299 | { |
| 300 | .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR, |
| 301 | .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR, |
| 302 | .m_reg = (uint32_t *) BLSP1_UART1_APPS_M, |
| 303 | .n_reg = (uint32_t *) BLSP1_UART1_APPS_N, |
| 304 | .d_reg = (uint32_t *) BLSP1_UART1_APPS_D, |
| 305 | |
| 306 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 307 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk, |
| 308 | .current_freq = &rcg_dummy_freq, |
| 309 | |
| 310 | .c = { |
| 311 | .dbg_name = "blsp1_uart1_apps_clk", |
| 312 | .ops = &clk_ops_rcg_mnd, |
| 313 | }, |
| 314 | }; |
| 315 | |
| 316 | static struct branch_clk gcc_blsp1_uart1_apps_clk = |
| 317 | { |
| 318 | .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR, |
| 319 | .parent = &blsp1_uart1_apps_clk_src.c, |
| 320 | |
| 321 | .c = { |
| 322 | .dbg_name = "gcc_blsp1_uart1_apps_clk", |
| 323 | .ops = &clk_ops_branch, |
| 324 | }, |
| 325 | }; |
| 326 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 327 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 328 | { |
| 329 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 330 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 331 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 332 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 333 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 334 | |
| 335 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 336 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk, |
| 337 | .current_freq = &rcg_dummy_freq, |
| 338 | |
| 339 | .c = { |
| 340 | .dbg_name = "blsp1_uart2_apps_clk", |
| 341 | .ops = &clk_ops_rcg_mnd, |
| 342 | }, |
| 343 | }; |
| 344 | |
| 345 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 346 | { |
| 347 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 348 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 349 | |
| 350 | .c = { |
| 351 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 352 | .ops = &clk_ops_branch, |
| 353 | }, |
| 354 | }; |
| 355 | |
| 356 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 357 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 358 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 359 | .en_mask = BIT(10), |
| 360 | |
| 361 | .c = { |
| 362 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 363 | .ops = &clk_ops_vote, |
| 364 | }, |
| 365 | }; |
| 366 | |
| 367 | /* USB Clocks */ |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 368 | static struct branch_clk gcc_pc_noc_usb30_axi_clk = |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 369 | { |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 370 | .cbcr_reg = (uint32_t *) PC_NOC_USB3_AXI_CBCR, |
| 371 | .has_sibling = 1, |
| 372 | |
| 373 | .c = { |
| 374 | .dbg_name = "gcc_pc_noc_usb3_axi_clk", |
| 375 | .ops = &clk_ops_branch, |
| 376 | }, |
| 377 | }; |
| 378 | |
| 379 | static struct branch_clk gcc_usb_phy_cfg_ahb_clk = { |
| 380 | .cbcr_reg = (uint32_t *) USB_PHY_CFG_AHB_CBCR, |
| 381 | .has_sibling = 1, |
| 382 | |
| 383 | .c = { |
| 384 | .dbg_name = "gcc_usb_phy_cfg_ahb_clk", |
| 385 | .ops = &clk_ops_branch, |
| 386 | }, |
| 387 | }; |
| 388 | |
| 389 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = |
| 390 | { |
| 391 | F(100000000, gpll0, 8, 0, 0), |
| 392 | F(133330000, gpll0, 6, 0, 0), |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 393 | F_END |
| 394 | }; |
| 395 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 396 | static struct rcg_clk usb30_master_clk_src = { |
| 397 | .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR, |
| 398 | .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR, |
| 399 | .m_reg = (uint32_t *) USB30_MASTER_M, |
| 400 | .n_reg = (uint32_t *) USB30_MASTER_N, |
| 401 | .d_reg = (uint32_t *) USB30_MASTER_D, |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 402 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 403 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 404 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 405 | .current_freq = &rcg_dummy_freq, |
| 406 | |
| 407 | .c = { |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 408 | .dbg_name = "usb30_master_clk_src", |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 409 | .ops = &clk_ops_rcg, |
| 410 | }, |
| 411 | }; |
| 412 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 413 | static struct branch_clk gcc_usb30_master_clk = |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 414 | { |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 415 | .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR, |
| 416 | .bcr_reg = (uint32_t *) USB_30_BCR, |
| 417 | .parent = &usb30_master_clk_src.c, |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 418 | |
| 419 | .c = { |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 420 | .dbg_name = "gcc_usb30_master_clk", |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 421 | .ops = &clk_ops_branch, |
| 422 | }, |
| 423 | }; |
| 424 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 425 | |
| 426 | static struct branch_clk gcc_usb30_pipe_clk = { |
| 427 | .bcr_reg = (uint32_t *) USB3PHY_PHY_BCR, |
| 428 | .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR, |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 429 | .has_sibling = 1, |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 430 | .halt_check = 0, |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 431 | |
| 432 | .c = { |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 433 | .dbg_name = "usb30_pipe_clk", |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 434 | .ops = &clk_ops_branch, |
| 435 | }, |
| 436 | }; |
| 437 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 438 | static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = { |
| 439 | F( 19200000, cxo, 0, 0, 0), |
| 440 | F_END |
| 441 | }; |
| 442 | |
| 443 | static struct rcg_clk usb30_aux_clk_src = { |
| 444 | .cmd_reg = (uint32_t *) USB3_AUX_CMD_RCGR, |
| 445 | .cfg_reg = (uint32_t *) USB3_AUX_CFG_RCGR, |
| 446 | .m_reg = (uint32_t *) USB3_AUX_M, |
| 447 | .n_reg = (uint32_t *) USB3_AUX_N, |
| 448 | .d_reg = (uint32_t *) USB3_AUX_D, |
| 449 | |
| 450 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 451 | .freq_tbl = ftbl_gcc_usb30_aux_clk, |
| 452 | .current_freq = &rcg_dummy_freq, |
| 453 | |
| 454 | .c = { |
| 455 | .dbg_name = "usb30_aux_clk_src", |
| 456 | .ops = &clk_ops_rcg_mnd, |
| 457 | }, |
| 458 | }; |
| 459 | |
| 460 | static struct branch_clk gcc_usb30_aux_clk = { |
| 461 | .cbcr_reg = (uint32_t *) USB3_AUX_CBCR, |
| 462 | .parent = &usb30_aux_clk_src.c, |
| 463 | |
| 464 | .c = { |
| 465 | .dbg_name = "gcc_usb30_aux_clk", |
| 466 | .ops = &clk_ops_branch, |
| 467 | }, |
| 468 | }; |
| 469 | |
| 470 | static struct reset_clk gcc_usb30_phy_reset = { |
| 471 | .bcr_reg = (uint32_t) USB3_PHY_BCR, |
| 472 | |
| 473 | .c = { |
| 474 | .dbg_name = "usb30_phy_reset", |
| 475 | .ops = &clk_ops_reset, |
| 476 | }, |
| 477 | }; |
| 478 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 479 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 480 | F(160000000, gpll0, 5, 0, 0), |
| 481 | F_END |
| 482 | }; |
| 483 | |
| 484 | static struct rcg_clk ce1_clk_src = { |
| 485 | .cmd_reg = (uint32_t *) GCC_CRYPTO_CMD_RCGR, |
| 486 | .cfg_reg = (uint32_t *) GCC_CRYPTO_CFG_RCGR, |
| 487 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 488 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 489 | .current_freq = &rcg_dummy_freq, |
| 490 | |
| 491 | .c = { |
| 492 | .dbg_name = "ce1_clk_src", |
| 493 | .ops = &clk_ops_rcg, |
| 494 | }, |
| 495 | }; |
| 496 | |
| 497 | static struct vote_clk gcc_ce1_clk = { |
| 498 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_CBCR, |
| 499 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 500 | .en_mask = BIT(2), |
| 501 | |
| 502 | .c = { |
| 503 | .dbg_name = "gcc_ce1_clk", |
| 504 | .ops = &clk_ops_vote, |
| 505 | }, |
| 506 | }; |
| 507 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 508 | static struct reset_clk gcc_usb2a_phy_sleep_clk = { |
| 509 | .bcr_reg = (uint32_t) GCC_QUSB2_PHY_BCR, |
| 510 | |
| 511 | .c = { |
| 512 | .dbg_name = "usb2b_phy_sleep_clk", |
| 513 | .ops = &clk_ops_reset, |
| 514 | }, |
| 515 | }; |
| 516 | |
| 517 | static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { |
| 518 | F( 19200000, cxo, 0, 0, 0), |
| 519 | F( 60000000, gpll6, 6, 1, 3), |
| 520 | F_END |
| 521 | }; |
| 522 | |
| 523 | static struct rcg_clk usb30_mock_utmi_clk_src = { |
| 524 | .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR, |
| 525 | .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR, |
| 526 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 527 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, |
| 528 | .current_freq = &rcg_dummy_freq, |
| 529 | |
| 530 | .c = { |
| 531 | .dbg_name = "usb30_mock_utmi_clk_src", |
| 532 | .ops = &clk_ops_rcg, |
| 533 | }, |
| 534 | }; |
| 535 | |
| 536 | static struct branch_clk gcc_usb30_mock_utmi_clk = { |
| 537 | .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR, |
| 538 | .has_sibling = 0, |
| 539 | .parent = &usb30_mock_utmi_clk_src.c, |
| 540 | |
| 541 | .c = { |
| 542 | .dbg_name = "usb30_mock_utmi_clk", |
| 543 | .ops = &clk_ops_branch, |
| 544 | }, |
| 545 | }; |
| 546 | |
| 547 | static struct branch_clk gcc_usb30_sleep_clk = { |
| 548 | .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR, |
| 549 | .has_sibling = 1, |
| 550 | |
| 551 | .c = { |
| 552 | .dbg_name = "usb30_sleep_clk", |
| 553 | .ops = &clk_ops_branch, |
| 554 | }, |
| 555 | }; |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 556 | static struct vote_clk gcc_ce1_ahb_clk = { |
| 557 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR, |
| 558 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 559 | .en_mask = BIT(0), |
| 560 | |
| 561 | .c = { |
| 562 | .dbg_name = "gcc_ce1_ahb_clk", |
| 563 | .ops = &clk_ops_vote, |
| 564 | }, |
| 565 | }; |
| 566 | |
| 567 | static struct vote_clk gcc_ce1_axi_clk = { |
| 568 | .cbcr_reg = (uint32_t *) GCC_CRYPTO_AXI_CBCR, |
| 569 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 570 | .en_mask = BIT(1), |
| 571 | |
| 572 | .c = { |
| 573 | .dbg_name = "gcc_ce1_axi_clk", |
| 574 | .ops = &clk_ops_vote, |
| 575 | }, |
| 576 | }; |
| 577 | |
| 578 | /* Clock lookup table */ |
| 579 | static struct clk_lookup msm_clocks_titanium[] = |
| 580 | { |
| 581 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 582 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 583 | |
| 584 | CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c), |
| 585 | CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c), |
| 586 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 587 | CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c), |
| 588 | CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c), |
| 589 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 590 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 591 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 592 | |
P.V. Phani Kumar | 9451ebe | 2015-12-26 16:31:18 +0530 | [diff] [blame^] | 593 | CLK_LOOKUP("usb30_iface_clk", gcc_pc_noc_usb30_axi_clk.c), |
| 594 | CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c), |
| 595 | CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c), |
| 596 | CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c), |
| 597 | CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c), |
| 598 | CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c), |
| 599 | CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c), |
| 600 | CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c), |
| 601 | CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c), |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 602 | |
| 603 | CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c), |
| 604 | CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c), |
| 605 | CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c), |
| 606 | CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c), |
| 607 | }; |
| 608 | |
| 609 | void platform_clock_init(void) |
| 610 | { |
| 611 | clk_init(msm_clocks_titanium, ARRAY_SIZE(msm_clocks_titanium)); |
| 612 | } |