Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <reg.h> |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 31 | #include <endian.h> |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 32 | #include <mipi_dsi.h> |
| 33 | #include <dev/fbcon.h> |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 34 | #include <stdlib.h> |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 35 | #include <debug.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 36 | #include <target/display.h> |
| 37 | #include <platform/iomap.h> |
| 38 | #include <platform/clock.h> |
| 39 | |
| 40 | extern void mdp_disable(void); |
| 41 | extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, unsigned short num_of_lanes); |
| 42 | extern void mdp_shutdown(void); |
| 43 | extern void mdp_start_dma(void); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 44 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 45 | #if DISPLAY_MIPI_PANEL_TOSHIBA |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 46 | static struct fbcon_config mipi_fb_cfg = { |
| 47 | .height = TSH_MIPI_FB_HEIGHT, |
| 48 | .width = TSH_MIPI_FB_WIDTH, |
| 49 | .stride = TSH_MIPI_FB_WIDTH, |
| 50 | .format = FB_FORMAT_RGB888, |
| 51 | .bpp = 24, |
| 52 | .update_start = NULL, |
| 53 | .update_done = NULL, |
| 54 | }; |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 55 | struct mipi_dsi_panel_config toshiba_panel_info = { |
| 56 | .mode = MIPI_VIDEO_MODE, |
| 57 | .num_of_lanes = 1, |
| 58 | .dsi_phy_config = &mipi_dsi_toshiba_panel_phy_ctrl, |
| 59 | .panel_cmds = toshiba_panel_video_mode_cmds, |
| 60 | .num_of_panel_cmds = ARRAY_SIZE(toshiba_panel_video_mode_cmds), |
| 61 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 62 | #elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
| 63 | static struct fbcon_config mipi_fb_cfg = { |
| 64 | .height = NOV_MIPI_FB_HEIGHT, |
| 65 | .width = NOV_MIPI_FB_WIDTH, |
| 66 | .stride = NOV_MIPI_FB_WIDTH, |
| 67 | .format = FB_FORMAT_RGB888, |
| 68 | .bpp = 24, |
| 69 | .update_start = NULL, |
| 70 | .update_done = NULL, |
| 71 | }; |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 72 | struct mipi_dsi_panel_config novatek_panel_info = { |
| 73 | .mode = MIPI_CMD_MODE, |
| 74 | .num_of_lanes = 2, |
| 75 | .dsi_phy_config = &mipi_dsi_novatek_panel_phy_ctrl, |
| 76 | .panel_cmds = novatek_panel_cmd_mode_cmds, |
| 77 | .num_of_panel_cmds = ARRAY_SIZE(novatek_panel_cmd_mode_cmds), |
| 78 | }; |
| 79 | #elif DISPLAY_MIPI_PANEL_TOSHIBA_MDT61 |
| 80 | static struct fbcon_config mipi_fb_cfg = { |
| 81 | .height = TSH_MDT61_MIPI_FB_HEIGHT, |
| 82 | .width = TSH_MDT61_MIPI_FB_WIDTH, |
| 83 | .stride = TSH_MDT61_MIPI_FB_WIDTH, |
| 84 | .format = FB_FORMAT_RGB888, |
| 85 | .bpp = 24, |
| 86 | .update_start = NULL, |
| 87 | .update_done = NULL, |
| 88 | }; |
| 89 | struct mipi_dsi_panel_config toshiba_mdt61_panel_info = { |
| 90 | .mode = MIPI_VIDEO_MODE, |
| 91 | .num_of_lanes = 3, |
| 92 | .dsi_phy_config = &mipi_dsi_toshiba_mdt61_panel_phy_ctrl, |
| 93 | .panel_cmds = toshiba_mdt61_video_mode_cmds, |
| 94 | .num_of_panel_cmds = ARRAY_SIZE(toshiba_mdt61_video_mode_cmds), |
| 95 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 96 | #else |
| 97 | static struct fbcon_config mipi_fb_cfg = { |
| 98 | .height = 0, |
| 99 | .width = 0, |
| 100 | .stride = 0, |
| 101 | .format = 0, |
| 102 | .bpp = 0, |
| 103 | .update_start = NULL, |
| 104 | .update_done = NULL, |
| 105 | }; |
| 106 | #endif |
| 107 | |
| 108 | static int cmd_mode_status = 0; |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 109 | void secure_writel(uint32_t, uint32_t); |
| 110 | uint32_t secure_readl(uint32_t); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 111 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 112 | int mipi_dsi_phy_ctrl_config(struct mipi_dsi_panel_config *pinfo) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 113 | { |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 114 | unsigned i; |
| 115 | unsigned off = 0; |
| 116 | struct mipi_dsi_phy_ctrl *pd; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 117 | |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 118 | writel(0x00000001, DSIPHY_SW_RESET); |
| 119 | writel(0x00000000, DSIPHY_SW_RESET); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 120 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 121 | pd = (pinfo->dsi_phy_config); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 122 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 123 | off = 0x02cc; /* regulator ctrl 0 */ |
| 124 | for (i = 0; i < 4; i++) { |
| 125 | writel(pd->regulator[i], MIPI_DSI_BASE + off); |
| 126 | off += 4; |
| 127 | } |
| 128 | |
| 129 | off = 0x0260; /* phy timig ctrl 0 */ |
| 130 | for (i = 0; i < 11; i++) { |
| 131 | writel(pd->timing[i], MIPI_DSI_BASE + off); |
| 132 | off += 4; |
| 133 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 134 | |
| 135 | // T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing length should > |
| 136 | // data lane HS timing length |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 137 | writel(0xa1e, DSI_CLKOUT_TIMING_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 138 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 139 | off = 0x0290; /* ctrl 0 */ |
| 140 | for (i = 0; i < 4; i++) { |
| 141 | writel(pd->ctrl[i], MIPI_DSI_BASE + off); |
| 142 | off += 4; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 143 | } |
| 144 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 145 | off = 0x02a0; /* strength 0 */ |
| 146 | for (i = 0; i < 4; i++) { |
| 147 | writel(pd->strength[i], MIPI_DSI_BASE + off); |
| 148 | off += 4; |
| 149 | } |
| 150 | |
| 151 | off = 0x0204; /* pll ctrl 1, skip 0 */ |
| 152 | for (i = 1; i < 21; i++) { |
| 153 | writel(pd->pll[i], MIPI_DSI_BASE + off); |
| 154 | off += 4; |
| 155 | } |
| 156 | |
| 157 | /* pll ctrl 0 */ |
| 158 | writel(pd->pll[0], MIPI_DSI_BASE + 0x200); |
| 159 | writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 160 | |
| 161 | return (0); |
| 162 | } |
| 163 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 164 | struct mipi_dsi_panel_config *get_panel_info(void) |
| 165 | { |
| 166 | #if DISPLAY_MIPI_PANEL_TOSHIBA |
| 167 | return &toshiba_panel_info; |
| 168 | #elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
| 169 | return &novatek_panel_info; |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 170 | #elif DISPLAY_MIPI_PANEL_TOSHIBA_MDT61 |
| 171 | return &toshiba_mdt61_panel_info; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 172 | #endif |
| 173 | return NULL; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 174 | } |
| 175 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 176 | int dsi_cmd_dma_trigger_for_panel() |
| 177 | { |
| 178 | unsigned long ReadValue; |
| 179 | unsigned long count = 0; |
| 180 | int status = 0; |
| 181 | |
| 182 | writel(0x03030303, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 183 | writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER); |
| 184 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 185 | while (ReadValue != 0x00000001) { |
| 186 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 187 | count++; |
| 188 | if (count > 0xffff) { |
| 189 | status = FAIL; |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 190 | dprintf(CRITICAL, "Panel CMD: command mode dma test failed\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 191 | return status; |
| 192 | } |
| 193 | } |
| 194 | |
| 195 | writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 196 | dprintf |
| 197 | (SPEW, "Panel CMD: command mode dma tested successfully\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 198 | return status; |
| 199 | } |
| 200 | |
Chandan Uddaraju | c1df565 | 2011-03-03 21:15:51 -0800 | [diff] [blame] | 201 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 202 | int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 203 | { |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 204 | int ret = 0; |
| 205 | struct mipi_dsi_cmd *cm; |
| 206 | int i = 0; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 207 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 208 | cm = cmds; |
| 209 | for (i = 0; i < count; i++) { |
| 210 | memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL, (cm->payload), cm->size); |
| 211 | writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET); |
| 212 | writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build |
| 213 | ret += dsi_cmd_dma_trigger_for_panel(); |
Kinson Chik | f91907f | 2011-07-15 10:06:48 -0700 | [diff] [blame] | 214 | udelay(80); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 215 | cm++; |
| 216 | } |
| 217 | return ret; |
| 218 | } |
| 219 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 220 | /* |
| 221 | * mipi_dsi_cmd_rx: can receive at most 16 bytes |
| 222 | * per transaction since it only have 4 32bits reigsters |
| 223 | * to hold data. |
| 224 | * therefore Maximum Return Packet Size need to be set to 16. |
| 225 | * any return data more than MRPS need to be break down |
| 226 | * to multiple transactions. |
| 227 | */ |
| 228 | int mipi_dsi_cmds_rx(char **rp, int len) |
| 229 | { |
| 230 | uint32_t *lp, data; |
| 231 | char * dp; |
| 232 | int i, off, cnt; |
| 233 | int rlen, res; |
| 234 | |
| 235 | if(len <= 2) |
| 236 | rlen = 4; /* short read */ |
| 237 | else |
| 238 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
| 239 | |
| 240 | if (rlen > MIPI_DSI_REG_LEN) { |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | res = rlen & 0x03; |
| 245 | |
| 246 | rlen += res; /* 4 byte align */ |
| 247 | lp = (uint32_t *)(*rp); |
| 248 | |
| 249 | cnt = rlen; |
| 250 | cnt += 3; |
| 251 | cnt >>=2; |
| 252 | |
| 253 | if (cnt > 4) |
| 254 | cnt = 4; /* 4 x 32 bits registers only */ |
| 255 | |
| 256 | off = 0x068; /* DSI_RDBK_DATA0 */ |
| 257 | off += ((cnt - 1) * 4); |
| 258 | |
| 259 | for (i = 0; i < cnt; i++) { |
| 260 | data = (uint32_t)readl(MIPI_DSI_BASE + off); |
| 261 | *lp++ = ntohl(data); /* to network byte order */ |
| 262 | off -= 4; |
| 263 | } |
| 264 | |
| 265 | if(len > 2) |
| 266 | { |
| 267 | /*First 4 bytes + paded bytes will be header next len bytes would be payload*/ |
| 268 | for(i = 0; i < len; i++) |
| 269 | { |
| 270 | dp = *rp; |
| 271 | dp[i] = dp[4 + res + i]; |
| 272 | } |
| 273 | } |
| 274 | |
| 275 | return len; |
| 276 | } |
| 277 | |
| 278 | static int mipi_dsi_cmd_bta_sw_trigger(void) |
| 279 | { |
| 280 | uint32_t data; |
| 281 | int cnt = 0; |
| 282 | int err = 0; |
| 283 | |
| 284 | writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */ |
| 285 | while (cnt < 10000) { |
| 286 | data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS*/ |
| 287 | if ((data & 0x0010) == 0) |
| 288 | break; |
| 289 | cnt++; |
| 290 | } |
| 291 | if(cnt == 10000) |
| 292 | err = 1; |
| 293 | return err; |
| 294 | } |
| 295 | |
| 296 | static uint32_t mipi_novatek_manufacture_id(void) |
| 297 | { |
| 298 | char rec_buf[24]; |
| 299 | char *rp = rec_buf; |
| 300 | uint32_t *lp, data; |
| 301 | |
| 302 | mipi_dsi_cmds_tx(&novatek_panel_manufacture_id_cmd, 1); |
| 303 | mipi_dsi_cmds_rx(&rp, 3); |
| 304 | |
| 305 | lp = (uint32_t *)rp; |
| 306 | data = (uint32_t)*lp; |
| 307 | data = ntohl(data); |
| 308 | data = data >> 8; |
| 309 | return data; |
| 310 | } |
| 311 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 312 | int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo) |
| 313 | { |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 314 | unsigned char DMA_STREAM1 = 0; // for mdp display processor path |
| 315 | unsigned char EMBED_MODE1 = 1; // from frame buffer |
| 316 | unsigned char POWER_MODE2 = 1; // from frame buffer |
| 317 | unsigned char PACK_TYPE1 = 1; // long packet |
| 318 | unsigned char VC1 = 0; |
| 319 | unsigned char DT1 = 0; // non embedded mode |
| 320 | unsigned short WC1 = 0; // for non embedded mode only |
| 321 | int status = 0; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 322 | unsigned char DLNx_EN; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 323 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 324 | switch (pinfo->num_of_lanes) { |
| 325 | default: |
| 326 | case 1: |
| 327 | DLNx_EN = 1; // 1 lane |
| 328 | break; |
| 329 | case 2: |
| 330 | DLNx_EN = 3; // 2 lane |
| 331 | break; |
| 332 | case 3: |
| 333 | DLNx_EN = 7; // 3 lane |
| 334 | break; |
| 335 | } |
| 336 | |
| 337 | writel(0x0001, DSI_SOFT_RESET); |
| 338 | writel(0x0000, DSI_SOFT_RESET); |
| 339 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 340 | writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */ |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 341 | writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 342 | // trigger 0x4; dma stream1 |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 343 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 344 | writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 345 | // build |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 346 | writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 347 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 348 | DSI_COMMAND_MODE_DMA_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 349 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 350 | status = mipi_dsi_cmds_tx(pinfo->panel_cmds, pinfo->num_of_panel_cmds); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 351 | |
| 352 | return status; |
| 353 | } |
| 354 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 355 | //TODO: Clean up arguments being passed in not being used |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 356 | int config_dsi_video_mode(unsigned short disp_width, unsigned short disp_height, |
| 357 | unsigned short img_width, unsigned short img_height, |
| 358 | unsigned short hsync_porch0_fp, |
| 359 | unsigned short hsync_porch0_bp, |
| 360 | unsigned short vsync_porch0_fp, |
| 361 | unsigned short vsync_porch0_bp, |
| 362 | unsigned short hsync_width, |
| 363 | unsigned short vsync_width, unsigned short dst_format, |
| 364 | unsigned short traffic_mode, |
| 365 | unsigned short datalane_num) |
| 366 | { |
| 367 | |
| 368 | unsigned char DST_FORMAT; |
| 369 | unsigned char TRAFIC_MODE; |
| 370 | unsigned char DLNx_EN; |
| 371 | // video mode data ctrl |
| 372 | int status = 0; |
| 373 | unsigned long low_pwr_stop_mode = 0; |
| 374 | unsigned char eof_bllp_pwr = 0x9; |
| 375 | unsigned char interleav = 0; |
| 376 | |
| 377 | // disable mdp first |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 378 | mdp_disable(); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 379 | |
| 380 | writel(0x00000000, DSI_CLK_CTRL); |
| 381 | writel(0x00000000, DSI_CLK_CTRL); |
| 382 | writel(0x00000000, DSI_CLK_CTRL); |
| 383 | writel(0x00000000, DSI_CLK_CTRL); |
| 384 | writel(0x00000002, DSI_CLK_CTRL); |
| 385 | writel(0x00000006, DSI_CLK_CTRL); |
| 386 | writel(0x0000000e, DSI_CLK_CTRL); |
| 387 | writel(0x0000001e, DSI_CLK_CTRL); |
| 388 | writel(0x0000003e, DSI_CLK_CTRL); |
| 389 | |
| 390 | writel(0, DSI_CTRL); |
| 391 | |
| 392 | writel(0, DSI_ERR_INT_MASK0); |
| 393 | |
| 394 | DST_FORMAT = 0; // RGB565 |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 395 | dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB565\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 396 | |
| 397 | DLNx_EN = 1; // 1 lane with clk programming |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 398 | dprintf(SPEW, "Data Lane: 1 lane\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 399 | |
| 400 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 401 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 402 | |
| 403 | writel(0x02020202, DSI_INT_CTRL); |
| 404 | |
| 405 | writel(((img_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
| 406 | DSI_VIDEO_MODE_ACTIVE_H); |
| 407 | |
| 408 | writel(((img_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
| 409 | DSI_VIDEO_MODE_ACTIVE_V); |
| 410 | |
| 411 | writel(((img_height + vsync_porch0_fp + vsync_porch0_bp) << 16) |
| 412 | | img_width + hsync_porch0_fp + hsync_porch0_bp, |
| 413 | DSI_VIDEO_MODE_TOTAL); |
| 414 | |
| 415 | writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC); |
| 416 | |
| 417 | writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC); |
| 418 | |
| 419 | writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS); |
| 420 | |
| 421 | writel(1, DSI_EOT_PACKET_CTRL); |
| 422 | |
| 423 | writel(0x00000100, DSI_MISR_VIDEO_CTRL); |
| 424 | |
| 425 | writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | TRAFIC_MODE << 8 |
| 426 | | DST_FORMAT << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
| 427 | |
| 428 | writel(0x67, DSI_CAL_STRENGTH_CTRL); |
| 429 | |
| 430 | writel(0x80006711, DSI_CAL_CTRL); |
| 431 | |
| 432 | writel(0x00010100, DSI_MISR_VIDEO_CTRL); |
| 433 | |
| 434 | writel(0x00010100, DSI_INT_CTRL); |
| 435 | writel(0x02010202, DSI_INT_CTRL); |
| 436 | |
| 437 | writel(0x02030303, DSI_INT_CTRL); |
| 438 | |
| 439 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 |
| 440 | | 0x103, DSI_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 441 | mdelay(10); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 442 | |
| 443 | return status; |
| 444 | } |
| 445 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 446 | int config_dsi_cmd_mode(unsigned short disp_width, unsigned short disp_height, |
| 447 | unsigned short img_width, unsigned short img_height, |
| 448 | unsigned short dst_format, |
| 449 | unsigned short traffic_mode, |
| 450 | unsigned short datalane_num) |
| 451 | { |
| 452 | unsigned char DST_FORMAT; |
| 453 | unsigned char TRAFIC_MODE; |
| 454 | unsigned char DLNx_EN; |
| 455 | // video mode data ctrl |
| 456 | int status = 0; |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 457 | unsigned char interleav = 0; |
| 458 | unsigned char ystride = 0x03; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 459 | // disable mdp first |
| 460 | |
| 461 | writel(0x00000000, DSI_CLK_CTRL); |
| 462 | writel(0x00000000, DSI_CLK_CTRL); |
| 463 | writel(0x00000000, DSI_CLK_CTRL); |
| 464 | writel(0x00000000, DSI_CLK_CTRL); |
| 465 | writel(0x00000002, DSI_CLK_CTRL); |
| 466 | writel(0x00000006, DSI_CLK_CTRL); |
| 467 | writel(0x0000000e, DSI_CLK_CTRL); |
| 468 | writel(0x0000001e, DSI_CLK_CTRL); |
| 469 | writel(0x0000003e, DSI_CLK_CTRL); |
| 470 | |
| 471 | writel(0x10000000, DSI_ERR_INT_MASK0); |
| 472 | |
| 473 | // writel(0, DSI_CTRL); |
| 474 | |
| 475 | // writel(0, DSI_ERR_INT_MASK0); |
| 476 | |
| 477 | DST_FORMAT = 8; // RGB888 |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 478 | dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 479 | |
| 480 | DLNx_EN = 3; // 2 lane with clk programming |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 481 | dprintf(SPEW, "Data Lane: 2 lane\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 482 | |
| 483 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 484 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 485 | |
| 486 | writel(0x02020202, DSI_INT_CTRL); |
| 487 | |
| 488 | writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); |
| 489 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 490 | DSI_COMMAND_MODE_MDP_STREAM0_CTRL); |
| 491 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 492 | DSI_COMMAND_MODE_MDP_STREAM1_CTRL); |
| 493 | writel(img_height << 16 | img_width, DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 494 | writel(img_height << 16 | img_width, DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 495 | writel(0xEE, DSI_CAL_STRENGTH_CTRL); |
| 496 | writel(0x80000000, DSI_CAL_CTRL); |
| 497 | writel(0x40, DSI_TRIG_CTRL); |
| 498 | writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); |
| 499 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, |
| 500 | DSI_CTRL); |
| 501 | mdelay(10); |
| 502 | writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL); |
| 503 | writel(0x10000000, DSI_MISR_CMD_CTRL); |
| 504 | writel(0x00000040, DSI_ERR_INT_MASK0); |
| 505 | writel(0x1, DSI_EOT_PACKET_CTRL); |
| 506 | // writel(0x0, MDP_OVERLAYPROC0_START); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 507 | mdp_start_dma(); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 508 | mdelay(10); |
| 509 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
| 510 | |
| 511 | status = 1; |
| 512 | return status; |
| 513 | } |
| 514 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 515 | int mipi_dsi_video_config(unsigned short num_of_lanes) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 516 | { |
| 517 | |
| 518 | int status = 0; |
| 519 | unsigned long ReadValue; |
| 520 | unsigned long count = 0; |
| 521 | unsigned long low_pwr_stop_mode = 0; // low power mode 0x1111 start from |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 522 | // bit16, high spd mode 0x0 |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 523 | unsigned char eof_bllp_pwr = 0x9; // bit 12, 15, 1:low power stop mode or |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 524 | // let cmd mode eng send packets in hs |
| 525 | // or lp mode |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 526 | unsigned short display_wd = mipi_fb_cfg.width; |
| 527 | unsigned short display_ht = mipi_fb_cfg.height; |
| 528 | unsigned short image_wd = mipi_fb_cfg.width; |
| 529 | unsigned short image_ht = mipi_fb_cfg.height; |
| 530 | unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK; |
| 531 | unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK; |
| 532 | unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES; |
| 533 | unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES; |
| 534 | unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH; |
| 535 | unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH; |
| 536 | unsigned short dst_format = 0; |
| 537 | unsigned short traffic_mode = 0; |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 538 | unsigned short pack_pattern = 0x12; //BGR |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 539 | unsigned char ystride = 3; |
| 540 | |
| 541 | low_pwr_stop_mode = 0x1111; // low pwr mode bit16:HSA, bit20:HBA, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 542 | // bit24:HFP, bit28:PULSE MODE, need enough |
| 543 | // time for swithc from LP to HS |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 544 | eof_bllp_pwr = 0x9; // low power stop mode or let cmd mode eng send |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 545 | // packets in hs or lp mode |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 546 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 547 | #if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61 |
| 548 | pack_pattern = 0x21; //RGB |
| 549 | config_mdt61_dsi_video_mode(); |
| 550 | |
| 551 | /* Two functions make up mdp_setup_dma_p_video_mode with mdt61 panel functions*/ |
| 552 | mdp_setup_dma_p_video_config(pack_pattern, image_wd, image_ht, MIPI_FB_ADDR, image_wd, ystride); |
| 553 | mdp_setup_mdt61_video_dsi_config(); |
| 554 | #else |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 555 | status += config_dsi_video_mode(display_wd, display_ht, image_wd, image_ht, |
| 556 | hsync_porch_fp, hsync_porch_bp, |
| 557 | vsync_porch_fp, vsync_porch_bp, hsync_width, |
| 558 | vsync_width, dst_format, traffic_mode, |
| 559 | num_of_lanes); |
| 560 | |
| 561 | status += |
| 562 | mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd, image_ht, |
| 563 | hsync_porch_fp, hsync_porch_bp, |
| 564 | vsync_porch_fp, vsync_porch_bp, hsync_width, |
| 565 | vsync_width, MIPI_FB_ADDR, image_wd, |
| 566 | pack_pattern, ystride); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 567 | #endif |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 568 | |
| 569 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 570 | while (ReadValue != 0x00010000) { |
| 571 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 572 | count++; |
| 573 | if (count > 0xffff) { |
| 574 | status = FAIL; |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 575 | dprintf(CRITICAL, "Toshiba Video lane test failed\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 576 | return status; |
| 577 | } |
| 578 | } |
| 579 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 580 | dprintf(SPEW, "Toshiba Video lane tested successfully\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 581 | return status; |
| 582 | } |
| 583 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 584 | int is_cmd_mode_enabled(void) |
| 585 | { |
| 586 | return cmd_mode_status; |
| 587 | } |
| 588 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 589 | #if DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 590 | void mipi_dsi_cmd_mode_trigger(void) |
| 591 | { |
| 592 | int status = 0; |
| 593 | unsigned short display_wd = mipi_fb_cfg.width; |
| 594 | unsigned short display_ht = mipi_fb_cfg.height; |
| 595 | unsigned short image_wd = mipi_fb_cfg.width; |
| 596 | unsigned short image_ht = mipi_fb_cfg.height; |
| 597 | unsigned short dst_format = 0; |
| 598 | unsigned short traffic_mode = 0; |
| 599 | struct mipi_dsi_panel_config *panel_info = &novatek_panel_info; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 600 | status += mipi_dsi_cmd_config(mipi_fb_cfg, panel_info->num_of_lanes); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 601 | mdelay(50); |
| 602 | config_dsi_cmd_mode(display_wd, display_ht, image_wd, image_ht, |
| 603 | dst_format, traffic_mode, |
| 604 | panel_info->num_of_lanes /* num_of_lanes */ ); |
| 605 | } |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 606 | #endif |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 607 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 608 | void mipi_dsi_shutdown(void) |
| 609 | { |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 610 | mdp_shutdown(); |
Ajay Dudani | 8fb3609 | 2011-01-27 18:09:50 -0800 | [diff] [blame] | 611 | writel(0x01010101, DSI_INT_CTRL); |
Chandan Uddaraju | c1df565 | 2011-03-03 21:15:51 -0800 | [diff] [blame] | 612 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 613 | writel(0, DSIPHY_PLL_CTRL(0)); |
Ajay Dudani | 8fb3609 | 2011-01-27 18:09:50 -0800 | [diff] [blame] | 614 | writel(0, DSI_CLK_CTRL); |
| 615 | writel(0, DSI_CTRL); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 616 | #if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61 |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 617 | writel(0x0, DSI_CC_REG); |
| 618 | writel(0x0, PIXEL_CC_REG); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 619 | #else |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 620 | secure_writel(0x0, DSI_CC_REG); |
| 621 | secure_writel(0x0, PIXEL_CC_REG); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 622 | #endif |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 623 | } |
| 624 | |
| 625 | struct fbcon_config *mipi_init(void) |
| 626 | { |
| 627 | int status = 0; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 628 | struct mipi_dsi_panel_config *panel_info = get_panel_info(); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 629 | /* Enable MMSS_AHB_ARB_MATER_PORT_E for arbiter master0 and master 1 request */ |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 630 | writel(0x00001800, MMSS_SFPB_GPREG); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 631 | |
| 632 | #if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61 |
| 633 | mipi_dsi_phy_init(panel_info); |
| 634 | #else |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 635 | mipi_dsi_phy_ctrl_config(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 636 | #endif |
| 637 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 638 | status += mipi_dsi_panel_initialize(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 639 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 640 | #if DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
| 641 | mipi_dsi_cmd_bta_sw_trigger(); |
| 642 | mipi_novatek_manufacture_id(); |
| 643 | #endif |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 644 | mipi_fb_cfg.base = MIPI_FB_ADDR; |
| 645 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 646 | if (panel_info->mode == MIPI_VIDEO_MODE) |
| 647 | status += mipi_dsi_video_config(panel_info->num_of_lanes); |
| 648 | |
| 649 | if (panel_info->mode == MIPI_CMD_MODE) |
| 650 | cmd_mode_status = 1; |
| 651 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 652 | return &mipi_fb_cfg; |
| 653 | } |